Sofics has verified its TakeCharge ESD protection clamps on technology nodes between 0.25um CMOS down to 3nm across various fabs and foundries. The ESD clamps are silicon and product proven in more than 5000 mass produced IC-products. The cells provide competitive advantage through improved yield, reduced silicon footprint and enable low-leakage, high-speed or high voltage tolerant interfaces.
The ESD protection described in this document can be used for 1.6V chiplet (die-2-die) interface pads in the GF 22nm FDX technology. The ESD robustness is strongly reduced in order to reduce the size and capacitance.
