All IPs > Wireline Communication > Error Correction/Detection > 256B ECC Error Correction for MRAM
The G12 BCH IP is tailored for 256-byte correction blocks and supports up to 16 bits of error correction, suiting niche applications with smaller block sizes. This design supports dynamic block sizes ranging from 2 to 450 bytes and allows optimization by specifying a maximum ECC level via parameters. The IP supports various configurations and is available in Verilog source with SystemVerilog Assertions.
| Class | Value |
|---|---|
| Categories |
Wireline Communication > Error Correction/Detection Security IP > Cryptography Cores Platform Level IP > Processor Core Independent |
| Error Correction Bits | Up to 16 bits |
| Availability | All Countries & Regions |
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