The G12 is a highly optimized BCH error correction solution focused on 256-byte correction blocks. Particularly beneficial for specialized applications that require smaller block sizes, this IP offers dynamic flexibility with block sizes ranging from 2 to 450 bytes. Users can maximize area efficiency by specifying the ECC level, supporting both single and multi-channel configurations. Delivered as Verilog source with SystemVerilog Assertions, the G12 can accommodate higher ECC levels upon request.
