All IPs > Wireline Communication > Error Correction/Detection > 512B ECC Error Correction for NAND
The G13 and G13X IP cores are engineered to accomplish 512-bit correction blocks, which are commonly used in NAND devices with 2KB and 4KB page sizes. As SLC NAND transitions toward smaller geometries, this IP extends existing controller capabilities to meet more demanding ECC requirements. Not only available in standard configurations, Cyclic Design can tailor this IP to perfectly align with the specific needs of any controller hardware, addressing latency, bandwidth, and area prerequisites.
| Class | Value |
|---|---|
| Categories |
Wireline Communication > Error Correction/Detection Memory Controller & PHY > NVM Express Memory Controller & PHY > SDRAM Controller Memory Controller & PHY > Flash Controller Security IP > Cryptography Cores Platform Level IP > Processor Core Independent |
| Max ECC Level | 64 bits |
| Part Number | G13/G13X |
| Availability | All Countries & Regions |
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