ADICSYS, a subsidiary of EASii IC, offers customizable Field Programmable Gate Array (FPGA) technology. This venture bridges the gap between ASIC design and FPGA solutions, boasting over a decade of experience in eFPGA projects and cutting-edge semiconductor products. The soft eFPGA IP is designed for ASICs and SOCs, independent of specific technology, and seamlessly integrates with standard RTL design processes.
The main features of ADICSYS's offering include synthesizable IP that fits smoothly into standard design flows, allowing RTL to FPGA bitstream translation. These eFPGAs are known for their scalability and customizable nature, developed through a robust RTL to bitstream compilation flow. This design flexibility helps reduce the risk of errors, accelerates development, and enhances debugging capabilities in complex systems.
The soft FPGA IP can be customized in terms of architecture parameters such as Look-Up Table (LUT) count and routing density, and it can be adapted for specific design constraints like power and area. By incorporating ADICSYS's solutions, users benefit from decreased time to market and increased reliability and adaptability in the field.
