All IPs > Wireline Communication > Ethernet
The wireline communication category of Ethernet semiconductor IPs is pivotal in the development of modern high-speed data transfer technologies. Ethernet technology, a mainstay in networking, facilitates the connection of computers to local networks (LANs) and wide-area networks (WANs). This category focuses on semiconductor IPs that implement Ethernet protocols, enabling manufacturers to integrate high-performance networking capabilities into their electronic devices efficiently and cost-effectively.
Ethernet semiconductor IPs are crucial for designing networking chips used in a variety of enterprise, consumer, and industrial applications. These IPs provide the foundational building blocks for implementing Ethernet standards from legacy 10/100 Mbps to the latest Multi-Gigabit Ethernet, including 1G, 10G, 25G, and beyond. Enhanced with features like Energy Efficient Ethernet (EEE) and advanced security mechanisms, these semiconductor IPs ensure optimized performance and reliability essential for today’s data-intensive applications.
The products in this category include a diverse range of Ethernet MAC(medium access control) cores, PHY(physical layer) cores, and network interface controllers, among others. These components work together to manage data packet transmission over Ethernet networks, ensuring seamless communication between connected devices. Designers leverage these Ethernet IPs to create routers, switches, servers, and Internet of Things (IoT) devices that require sophisticated data handling capabilities.
By integrating Ethernet semiconductor IPs, developers and OEMs can achieve faster time-to-market while reducing design risk and cost. These IPs are pre-verified, ensuring compliance with the current Ethernet standards, which accelerates the development cycle for networking equipment. Consequently, Ethernet semiconductor IPs are indispensable for any entity aiming to innovate within the competitive landscape of wireline communication technologies.
Axelera AI's Metis AIPU PCIe AI Accelerator Card is engineered to deliver top-tier inference performance in AI tasks aimed at heavy computational loads. This PCIe card is designed with the industry’s highest standards, offering exceptional processing power packaged onto a versatile PCIe form factor, ideal for integration into various computing systems including workstations and servers.<br><br>Equipped with a quad-core Metis AI Processing Unit (AIPU), the card delivers unmatched capabilities for handling complex AI models and extensive data streams. It efficiently processes multiple camera inputs and supports independent parallel neural network operations, making it indispensable for dynamic fields such as industrial automation, surveillance, and high-performance computing.<br><br>The card's performance is significantly enhanced by the Voyager SDK, which facilitates a seamless AI model deployment experience, allowing developers to focus on model logic and innovation. It offers extensive compatibility with mainstream AI frameworks, ensuring flexibility and ease of integration across diverse use cases. With a power-efficient design, this PCIe AI Accelerator Card bridges the gap between traditional GPU solutions and today's advanced AI demands.
The "1G to 224G SerDes" solution from Alphawave Semi offers an extensive range of multi-standard connectivity IPs, designed to deliver optimal high-speed data transfer. These full-featured building blocks can be integrated into various chip designs, providing scalability and reliability across numerous protocols and standards. Supporting data rates from 1 Gbps to 224 Gbps, this SerDes solution accommodates diverse signaling schemes, including PAM2, PAM4, PAM6, and PAM8. Alphawave Semi's SerDes IP is engineered to meet the demands of modern communication systems, ensuring connectivity across a wide spectrum of applications. These include data centers, telecom networks, and advanced networking systems where high data transfer speeds are a necessity. This solution is crafted with energy efficiency in mind, helping reduce power consumption while maintaining a robust data connection. The SerDes solutions come equipped with advanced features like low latency and noise resilience, which are crucial for maintaining signal integrity over various transmission distances. This facilitates seamless integration into enterprises looking to boost their processing capabilities while minimizing downtime and operational inefficiencies. These capabilities make Alphawave Semi's SerDes IP a vital component in the evolving landscape of technology connectivity applications.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
Ethernet MAC 10M/100M/1G/2.5G IP is a solution that enables the host to communicate data using the IEEE 802.3 standard for 10M, 100M, 1G, 2.5G speeds and is suited for use in networking equipment such as switches and routers. The Client-side interface for the IP is AXI-S and the Ethernet MAC IP comes with GMII, RGMII or MII interfaces on the PHY side. The Ethernet MAC 10M/100M/1G/2.5G IP features a compact and low latency solution, it is highly configurable and can optionally include IEEE 1588 Timestamping Unit (TSU). The Silicon agnostic Ethernet MAC IP, suitable for ASICs and FPGAs, is prepared for easy integration with Ethernet PCS 10M/ 100M/1G/2.5G IP from Comcores.
The ARINC 818 Product Suite is a comprehensive solution designed for professionals working with advanced avionics systems. It provides a robust framework for implementing, testing, and simulating ARINC 818 systems. The product suite includes a variety of tools and resources tailored for the lifecycle of ARINC 818 systems, ensuring that clients can develop mission-critical systems with confidence. With a primary focus on performance and scalability, the ARINC 818 Product Suite is developed to cater to complex requirements and to seamlessly integrate within existing technology stacks. Users benefit from its extensive compatibility and the ability to manage high-speed data effectively, making it a vital asset for those working in aviation and defense sectors.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
TTTech's Time-Triggered Ethernet (TTEthernet) is a breakthrough communication technology that combines the reliability of traditional Ethernet with the precision of time-triggered protocols. Designed to meet stringent safety requirements, this IP is fundamental in environments where fail-safe operations are absolute, such as human spaceflight, nuclear facilities, and other high-risk settings. TTEthernet integrates seamlessly with existing Ethernet infrastructure while providing deterministic control over data transmission times, allowing for real-time application support. Its primary advantage lies in supporting triple-redundant networks, which ensures dual fault-tolerance, an essential feature exemplified in its use by NASA's Orion spacecraft. The integrity and precision offered by Time-Triggered Ethernet make it ideal for implementing ECSS Engineering standards in space applications. It not only permits robust redundancy and high bandwidth (exceeding 10 Gbps) but also supports interoperability with various commercial off-the-shelf components, making it a versatile solution for complex network architectures.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The ePHY-5616 is a versatile SerDes solution tailored to support data rates from 1 to 56Gbps, making it suitable for a variety of applications across different technology sectors. Designed with flexibility in mind, it operates efficiently on 16nm and 12nm nodes, providing scalability to adapt to varying insertion losses and data rate requirements. This product is engineered to deliver superior performance in enterprise equipment such as routers and switches, as well as for network interface cards. Its robustness in Clock Data Recovery (CDR) and minimal latency make it a preferred choice for data centers that require reliable high-speed data transmissions. The ePHY-5616 capitalizes on advanced DSP techniques to ensure extreme resistance to interference and data rate variability, offering a scalable architecture that can be customized to fit specific deployment scenarios. The inclusion of a comprehensive set of diagnostic features further aids in system bring-up and performance tuning, enabling operators to maintain optimal operational conditions.
RapidGPT is a next-generation electronic design automation tool powered by AI. Designed for those in the hardware engineering field, it allows for a seamless transition from ideas to physical hardware without the usual complexities of traditional design tools. The interface is highly intuitive, engaging users with natural language interaction to enhance productivity and reduce the time required for design iterations.\n\nEnhancing the entire design process, RapidGPT begins with concept development and guides users through to the final stages of bitstream or GDSII generation. This tool effectively acts as a co-pilot for engineers, allowing them to easily incorporate third-party IPs, making it adaptable for various project requirements. This adaptability is paramount for industries where speed and precision are of the essence.\n\nPrimisAI has integrated novel features such as AutoReview™, which provides automated HDL audits; AutoComment™, which generates AI-driven comments for HDL files; and AutoDoc™, which helps create comprehensive project documentation effortlessly. These features collectively make RapidGPT not only a design tool but also a comprehensive project management suite.\n\nThe effectiveness of RapidGPT is made evident in its robust support for various design complexities, providing a scalable solution that meets specific user demands from individual developers to large engineering teams seeking enterprise-grade capabilities.
Digital Predistortion (DPD) is a sophisticated technology crafted to optimize the power efficiency of RF power amplifiers. The flagship product, FlexDPD, presents a complete, adaptable sub-system that can be customized to any ASIC or FPGA/SoC platform. Thanks to its scalability, it is compatible with various device vendors. Designed for high performance, this DPD solution significantly boosts RF efficiencies by counteracting signal distortion, ensuring clear and effective transmission. The core of the DPD solution lies in its adaptability to a broad range of systems including 5G, multi-carrier platforms, and O-RAN frameworks. It's built to handle transmission bandwidths exceeding 1 GHz, making it a versatile and future-proof technology. This capability not only enhances system robustness but also offers a seamless integration pathway for next-generation communication standards. Additionally, Systems4Silicon’s DPD solution is field-tested, ensuring reliability in real-world applications. The solution is particularly beneficial for projects that demand high signal integrity and efficiency, providing a tangible advantage in competitive markets. Its compatibility with both ASIC and FPGA implementations offers flexibility and choice to partners, significantly reducing development time and cost.
The SerDes PHY is a high-performance solution designed to facilitate high-speed data transmission within sophisticated data infrastructures. Offering support for various signaling options from 28G to 224G, this PHY is engineered to provide reliable, high-bandwidth communication required by next-generation AI and data centers. With the highly adaptable architecture, it ensures seamless integration into multiple designs including those that require long reach and very short reach plus options. Its design emphasis is on achieving low latency and high reliability, making it indispensable in environments demanding maximum uptime and efficiency. Incorporating cutting-edge mixed signal DSP technology, the SerDes PHY can effectively manage high data rates, making it ideal for switch fabric ASICs, AI ASICs, and machine learning applications. The underlying technology is manufactured on advanced process nodes, which enhances both the performance and power efficiency of the solutions. Through its innovative design, the SerDes PHY supports a range of applications that include interconnecting AI clusters, supporting cloud infrastructures, and enhancing hyperscale networking systems. It stands out for its ability to support seamless operation at various data rates, ensuring future-proofing for scaling AI and data center demands. Utilizing this PHY can enable the development of high-performance, optimized solutions that push the boundaries of current technological capabilities.
The AXI4 DMA Controller is a highly versatile IP core that supports multi-channel data transfers, ranging from 1 to 16 channels, depending on system requirements. Optimized for high throughput, this controller excels in transferring both small and large data sets effectively. It features independent DMA Read and Write Controllers for enhanced data handling with options for FIFO transfers to a diverse array of memory and peripheral configurations. This IP core offers significant flexibility with its programmable burst sizes, supporting up to 256 beats and adhering to critical boundary crossings in the AXI specification.
The EZiD211, also known as Oxford-2, is a leading-edge demodulator and modulator developed by EASii IC to facilitate advanced satellite communications. It embodies a sophisticated DVB-S2X wideband tuner capable of supporting LEO, MEO, and GEO satellites, integrating proprietary features like Beam Hopping, VLSNR, and Super Frame applications. With EZiD211 at the helm, satellite communications undergo a transformation in efficiency and capacity, addressing both current and future demands for fixed data infrastructures, mobility, IoT, and M2M applications. Its technological forefront facilitates seamless operations in varied European space programs, validated by its full production readiness. EZiD211's design offers a unique capability to manage complex satellite links, enhance performance, and ensure robust and reliable data transmission. EASii IC provides comprehensive support through evaluation boards and samples, allowing smooth integration and testing to meet evolving satellite communication standards.
The HOTLink II Product Suite is designed to facilitate high-speed connectivity and data transfer in demanding environments. This suite of products offers robust solutions for those needing reliable and fast data links, catering to industries where performance and precision are crucial. As part of Great River Technology's offerings, HOTLink II stands out by providing comprehensive support throughout product lifecycles and ensuring compatibility with various systems. With HOTLink II, users can expect exceptional levels of performance and reliability thanks to its advanced design, which is geared towards meeting the rigorous demands of aerospace and defense applications. Whether implementing new systems or upgrading existing infrastructures, the HOTLink II Product Suite provides the versatility and capability needed to meet diverse clients' needs. The suite is particularly beneficial for engineers requiring high-performance link solutions that integrate seamlessly within larger systems, enhancing operational effectiveness and efficiency. It includes all the necessary tools to ensure a smooth deployment process while minimizing potential downtime associated with new technology integration.
This IP core is engineered for applications where minimal latency is of paramount importance. The Ultra-Low Latency 10G Ethernet MAC features an optimized architecture to provide rapid data transmission and reception capabilities, ensuring that all processes occur smoothly and efficiently. It is tailored specifically for real-time operations where every millisecond counts, like high-frequency trading and real-time monitoring systems. By focusing on reducing latency, this Ethernet MAC core delivers exceptional performance, making it an excellent choice for demanding environments that cannot afford delayed communication. The core's architecture reduces overhead and maximizes throughput, leveraging Chevin Technology's advanced design expertise to minimize signal interference and processing delays. Its seamless integration with both AMD and Intel FPGA platforms makes it versatile for a variety of implementations across industry sectors. Moreover, it's designed to maintain optimal performance while managing high data loads, showcasing a consistent ability to handle extensive network traffic efficiently.
The Digital Radio (GDR) from GIRD Systems is an advanced software-defined radio (SDR) platform that offers extensive flexibility and adaptability. It is characterized by its multi-channel capabilities and high-speed signal processing resources, allowing it to meet a diverse range of system requirements. Built on a core single board module, this radio can be configured for both embedded and standalone operations, supporting a wide frequency range. The GDR can operate with either one or two independent transceivers, with options for full or half duplex configurations. It supports single channel setups as well as multiple-input multiple-output (MIMO) configurations, providing significant adaptability in communication scenarios. This flexibility makes it an ideal choice for systems that require rapid reconfiguration or scalability. Known for its robust construction, the GDR is designed to address challenging signal processing needs in congested environments, making it suitable for a variety of applications. Whether used in defense, communications, or electronic warfare, the GDR's ability to seamlessly switch configurations ensures it meets the evolving demands of modern communications technology.
High-Speed SerDes for Chiplets is engineered to provide exceptional interconnect solutions tailored for chiplet architectures. This product offers ultra-low power consumption while maintaining high data transfer rates, essential for modern multi-die systems. By facilitating rapid communication between chiplets, it enhances overall system efficiency and performance. This SerDes solution is optimized for integration with a range of tech nodes, ensuring compatibility with various semiconductor manufacturing processes. Its design is focused on providing robust data integrity and reducing latency, which are crucial for efficient system operation in complex, integrated circuits. High-Speed SerDes addresses the growing demand for advanced interconnect solutions in chiplet architectures, making it an indispensable tool for developing next-generation semiconductor devices. Its ability to support high data throughput while keeping power use minimal makes it a standout choice in high-performance design environments.
This core is designed for high-performance applications requiring robust Ethernet connectivity with a high data throughput. The 10G Ethernet MAC and PCS solutions are developed to reliably handle speeds up to 10Gbps, optimizing the interface between Ethernet transmission and physical network layers. These IPs provide key functionality that helps maintain efficient data handling and transfer across networks, ensuring minimal latency and maximum productivity. Featuring refined architecture and robust design, this solution integrates seamlessly into FPGA frameworks, especially targeting Intel and AMD platforms. Its compatibility and reliability make it ideal for advanced networking tasks in a broad range of applications—from data centers to complex cloud infrastructures. The efficient management of data streams through this MAC and PCS combination ensures high-speed communication and responsiveness critical to high-demand environments. Its plug-and-play usability allows it to be quickly incorporated into existing systems, providing a flexible solution that maintains the scalability and performance needs of high-end systems. Additionally, Chevin Technology's expertise ensures that these cores come with comprehensive support tailored to enhance product integration and deployment efficiency.
The 2D FFT core is designed to efficiently handle two-dimensional FFT processing, ideal for applications in image and video processing where data is inherently two-dimensional. This core is engineered to integrate both internal and external memory configurations, which optimize data handling for complex multimedia processing tasks, ensuring a high level of performance is maintained throughout. Utilizing sophisticated algorithms, the 2D FFT core processes data through two FFT engines. This dual approach maximizes throughput, typically limiting bottlenecks to memory bandwidth constraints rather than computational delays. This efficiency is critical for applications handling large volumes of multimedia data where real-time processing is a requisite. The capacity of the 2D FFT core to adapt to varying processing environments marks its versatility in the digital processing landscape. By ensuring robust data processing capabilities, it addresses the challenges of dynamic data movement, providing the reliability necessary for multimedia systems. Its strategic design supports the execution of intensive computational tasks while maintaining the operational flow integral to real-time applications.
The Time-Triggered Protocol (TTP) designed by TTTech is an advanced communication protocol meant to enhance the reliability of data transmission in critical systems. Developed in compliance with the SAE AS6003 standard, this protocol is ideally suited for environments requiring synchronized operations, such as aeronautics and high-stakes energy sectors. TTP allows for precise scheduling of communication tasks, creating a deterministic communication environment where the timing of data exchanges is predictable and stable. This predictability is crucial in eliminating delays and minimizing data loss in safety-critical applications. The protocol lays the groundwork for robust telecom infrastructures in airplanes and offers a high level of system redundancy and fault tolerance. TTTech’s TTP IP core is integral to their TTP-Controller ASICs and is designed to comply with stringent integrity and safety requirements, including those outlined in RTCA DO-254 / EUROCAE ED-80. The versatility of TTP allows it to be implemented across varying FPGA platforms, broadening its applicability to a wide range of safety-critical industrial systems.
The DisplayPort 1.4 IP-core offered by Parretto B.V. is a compact yet potent solution for DisplayPort connectivity needs. Supporting a range of link rates from 1.62 to 8.1 Gbps, this IP-core accommodates varied setups with ease, including embedded DisplayPort (eDP) applications. It provides support for multiple lane configurations and both native video and AXI stream interfaces. The inclusion of Single and Multi Stream transport modes enhances its versatility for different video applications. Tailored for modern FPGA devices, the core supports a comprehensive video format range, including RGB and various YCbCr colorspaces. A standout feature is the secondary data packet interface, enabling audio and metadata transport alongside video signals. This makes it a full-fledged solution for video-centric applications, complemented by a Video Toolbox geared for video processing tasks like timing and test pattern generation. Parretto ensures the IP-core's adaptability by offering it with a thin host driver and API for seamless integration. The core is compatible with an extensive list of FPGA devices, such as AMD UltraScale+ and Intel Arria 10 GX. Customers benefit from the availability of source code via GitHub, promoting easier customization and deep integration into diverse systems. Comprehensive documentation supports the IP-core, ensuring efficient setup and utilization.
The GNSS ICs AST 500 and AST GNSS-RF are crafted by Accord Software & Systems as part of their extensive lineup of GNSS-centric products. These ICs are pivotal for applications requiring precision navigation, especially where stringent environmental and operational parameters are paramount. Built for robustness and accuracy, these ICs thrive under challenging conditions, providing users with reliable GPS and GNSS solutions. The AST 500 and AST GNSS-RF are tailored for seamless integration into complex systems, ensuring they meet the high demands of precision and performance. They offer enhanced capabilities for both time-sensitive and location-critical applications across various sectors, including aerospace, defense, and commercial industries. These integrated circuits leverage Accord's cutting-edge technology to maintain precise positioning and timing, which is essential for applications demanding unfailing synchronization and navigation. These ICs support various navigation systems and are designed to accommodate multiple constellation signals, including GPS, GLONASS, and more. Their comprehensive design encompasses complete GNSS functionality, which includes signal acquisition, tracking, and data output, ensuring continuous performance even in environments with high interference or dynamics. Providing both user-friendly integration and exceptional performance, these ICs form the backbone for Accord's reliable GNSS modules. In addition to interoperability across a range of navigation systems, the ICs are optimized for low-power consumption, making them suitable for portable and power-sensitive applications. This energy efficiency, coupled with advanced signal processing capabilities, ensures that the AST 500 and AST GNSS-RF remain at the forefront of GNSS technology.
Designed for seamless integration, High PHY Accelerators from AccelerComm encapsulate top-tier signal processing blocks critical for 5G solutions. Available as FPGA and ASIC ready IP cores, they are tailored for rapid deployment with minimal risk. These accelerators are supported by accurate simulation models and designed to use standardized interfaces for integration. Notably, they also provide support for space-hardened platforms, ensuring robust performance in diverse settings.
The Ethernet Real-Time Publish-Subscribe (RTPS) IP Core provides a comprehensive hardware implementation of the Ethernet RTPS protocol, facilitating real-time data sharing in network systems. It is designed to enable efficient and synchronized communications crucial in time-sensitive applications. Ideal for environments where timing precision and reliability are paramount, this core supports high-speed data exchanges with low latency performance. This ensures that critical data is published and subscribed to in real-time, meeting rigorous industry standards for communication efficiency. Moreover, the RTPS IP Core is constructed to seamlessly integrate into existing infrastructures, allowing for enhanced operations across diverse platforms while ensuring data flow consistency and system interoperability.
The RISCV SoC developed by Dyumnin Semiconductors is engineered with a 64-bit quad-core server-class RISCV CPU, aiming to bridge various application needs with an integrated, holistic system design. Each subsystem of this SoC, from AI/ML capabilities to automotive and multimedia functionalities, is constructed to deliver optimal performance and streamlined operations. Designed as a reference model, this SoC enables quick adaptation and deployment, significantly reducing the time-to-market for clients. The AI Accelerator subsystem enhances AI operations with its collaboration of a custom central processing unit, intertwined with a specialized tensor flow unit. In the multimedia domain, the SoC boasts integration capabilities for HDMI, Display Port, MIPI, and other advanced graphic and audio technologies, ensuring versatile application across various multimedia requirements. Memory handling is another strength of this SoC, with support for protocols ranging from DDR and MMC to more advanced interfaces like ONFI and SD/SDIO, ensuring seamless connectivity with a wide array of memory modules. Moreover, the communication subsystem encompasses a broad spectrum of connectivity protocols, including PCIe, Ethernet, USB, and SPI, crafting an all-rounded solution for modern communication challenges. The automotive subsystem, offering CAN and CAN-FD protocols, further extends its utility into automotive connectivity.
The LightningBlu solution from Blu Wireless is a premier mmWave technology specifically designed to cater to the rigorous demands of high-speed rail connectivity. It provides multi-gigabit, continuous communication solutions between tracksides and trains. This connectivity ensures reliable on-board services such as internet access, entertainment, and passenger information systems. The versatile solution is engineered to perform seamlessly even at speeds greater than 300 km/h, enhancing the passenger experience by delivering consistent, high-speed internet and data services. Built to leverage the 57-71 GHz mmWave spectrum, LightningBlu guarantees carrier-grade connectivity that accommodates the surge of digital devices passengers bring aboard. The technology facilitates a robust communication network that empowers high-speed rail services amidst challenging dynamics and ensures that passengers enjoy uninterrupted service across wide geographic expanses. This significant technical prowess positions LightningBlu as an indispensable asset for the future of rail transport, effectively shaping the industry's move towards digital transformation. With a focus on sustainability, LightningBlu also supports the transition to a carbon-free transport ecosystem, providing an advanced data communication solution that interlinks seamless connectivity with environmentally responsible operation. Its application in rail systems positions it at the heart of modernizing rail services, fostering an era of enhanced rider satisfaction and operational efficiency.
The TSN Switch for Automotive Ethernet is designed to manage real-time data traffic within automotive networks. This high-performance switch provides low-latency communications, making it ideal for modern vehicle architectures that rely heavily on seamless integration and timing precision. Utilizing Time-Sensitive Networking (TSN) protocols, this switch offers enhanced coordination among automotive components, ensuring safety and efficiency in complex vehicular systems. With its robust configuration capabilities, the switch supports the intensive data rates and reliability demands of automotive networks. It's perfectly tailored for the increasingly data-centric environment of smart vehicles, where system reliability and network redundancy are paramount. The TSN Switch excels in providing guaranteed data delivery, essential for applications such as autonomous driving and advanced driver-assistance systems. The integration of this switch into vehicle networks aids in simplifying complex electronic environments, offering manufacturers a scalable solution that adapts to varying production needs. This flexibility ensures that manufacturers can optimize for both current requirements and future advancements in automotive technology. The TSN Switch's comprehensive feature set is aligned with the strict safety requirements of the automotive industry, ensuring compliance with global standards and enhancing vehicle intelligence.
This platform stands out for its ability to offload and accelerate network protocol processing at an impressive speed of up to 100 Gbps using FPGA technology. The Network Protocol Accelerator Platform is designed to enhance network-related tasks, providing distinct performance advantages by leveraging MLE's patented technology. This IP is highly suitable for those requiring efficient data processing in high-speed networking applications, offering scalable solutions from point-to-point connections to complex network systems. The platform's innovation lies in its ability to seamlessly manage a wide array of network protocols, making communication between devices efficient and effective. With its high-speed capability, the platform aids in reducing data processing time significantly. The robustness of this platform ensures that data integrity is maintained across various network tasks, including data acceleration and offloading critical network processes. Furthermore, this platform is particularly useful for industries like telecommunications and data centers where processing large volumes of data rapidly is crucial. The ability to upgrade and maintain such technology provides users with flexibility and adaptability in response to changing network demands. With its broad applicability, the Network Protocol Accelerator Platform remains a strategic asset for enhancing operational efficiency in digital infrastructure management.
The High Speed Data Bus (HSDB) IP Core offers a robust hardware implementation featuring PHY and MAC layers, optimized for high-speed data transmission. This IP core ensures seamless integration and supports F-22 compatible interface implementations, making it indispensable for advanced military communication systems. This core is instrumental in providing high throughput and low latency, crucial for applications that manage complex data transmissions. Its design caters to environments that require secure and efficient data handling, meeting the rigorous requirements of modern defense systems. The HSDB IP Core is particularly suited for situations where data integrity and transmission speed are pivotal, addressing the needs of platforms reliant on effective real-time communications. Its deployment aids in stabilizing operations across varied legacy and state-of-the-art systems, offering flexibility and reliability.
The PRACH IP Suite is a comprehensive solution optimized for 5G NR O-RAN Split 7.2X design. It includes a complete MATLAB model, RTL implementation, and a robust verification environment for bit-exact simulation and testing. This suite supports seamless integration and speeds up the development process with its 5G NR O-RAN compatibility, catering to the evolving needs of modern telecommunications infrastructure.
VeriSyno Microelectronics Co., Ltd. offers a comprehensive range of high-speed interface solutions. These IPs are well-suited for systems requiring reliable and quick data transfer capabilities. Their high-speed interface technologies support various advanced manufacturing processes, from 28nm to 90nm, making them adaptable to modern semiconductor needs. They also provide customized migration services to meet specific process requirements ranging from 90nm to 180nm, ensuring optimal performance across different technology standards. The high-speed interfaces offered by VeriSyno cater to applications that demand elevated data processing rates and robust connectivity. These solutions facilitate seamless integration with components like USB, DDR, MIPI, HDMI, PCIe, and SATA. Each interface is engineered to minimize power consumption while maximizing throughput, allowing for efficient and effective communication between digital systems. By providing adaptable IP solutions that meet the rigorous demands of current and future electronic devices and systems, VeriSyno aims to enhance both the speed and reliability of data transmission. Their high-speed interfaces not only meet current industry standards but also pave the way for innovation, encouraging the development of smarter and faster technologies of tomorrow.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The FCM1401 Dual-Drive™ Power Amplifier is tailored for Ku-band applications, utilizing CMOS technology to deliver solutions between 12.4 to 16 GHz. This product is designed to optimize power output while maintaining a compact silicon footprint. Notable for its excellent efficiency, the FCM1401 addresses the specific demands of telecom and satellite communications applications. The amplifier provides reliable performance characterized by a gain of 22 dB and a Psat of 19.2 dBm, achieving a power-added efficiency of 47% while operating at a supply voltage of 1.8V. Through these specifications, it positions itself as an ideal solution for applications requiring high power output and minimal heat generation. This product benefits from world-class CMOS integration, ensuring compatibility with modern telecom systems, enhancing their range and reducing their energy costs. The FCM1401 is equipped with a QFN/EVB package, allowing for straightforward implementation in various industrial contexts. It sets itself apart by offering an increased frequency range while delivering robust power handling capabilities, facilitating the high RF power needs of contemporary communication systems. The dual-drive capability of the FCM1401 means that it can effectively double the input signal power into the output without losing efficiency, making it highly suited for use in mission-critical operations where reliability and performance are paramount. Its high power-added efficiency also translates to cooler operation, reducing the need for extensive thermal management solutions, thus lowering associated costs.
The SiFive Performance family is dedicated to offering high-throughput, low-power processor solutions, suitable for a wide array of applications from data centers to consumer devices. This family includes a range of 64-bit, out-of-order cores configured with options for vector computations, making it ideal for tasks that demand significant processing power alongside efficiency. Performance cores provide unmatched energy efficiency while accommodating a breadth of workload requirements. Their architecture supports up to six-wide out-of-order processing with tailored options that include multiple vector engines. These cores are designed for flexibility, enabling various implementations in consumer electronics, network storage solutions, and complex multimedia processing. The SiFive Performance family facilitates a mix of high performance and low power usage, allowing users to balance the computational needs with power consumption effectively. It stands as a testament to SiFive’s dedication to enabling flexible tech solutions by offering rigorous processing capabilities in compact, scalable packages.
The L5-Direct GNSS Receiver by oneNav offers cutting-edge performance by exclusively leveraging L5-band signals for navigation. This receiver directly captures signals in the L5 band, bypassing traditional L1 signals, which are often susceptible to interference and jamming. Designed for modern GNSS applications, it provides unmatched accuracy and robustness in urban areas and other challenging environments. The L5-direct technology boasts innovative features such as an Application Specific Array Processor (ASAP), which ensures rapid location acquisition without sacrificing sensitivity. It supports over 70 satellite signals across multiple constellations, including GPS, Galileo, BeiDou, and QZSS. This capability guarantees reliable positioning, making it ideal for users who require accurate and tamper-resistant navigation data. One of the unique aspects of the L5-Direct GNSS Receiver is its low power consumption, thanks to its optimized processing efficiencies. It is crafted to cater to applications with stringent size and cost restrictions, such as wearables and IoT devices. Furthermore, the receiver offers a single RF chain design, simplifying integration and reducing system complexity. This innovation makes oneNav's solution a compelling choice for next-generation GNSS receivers in diverse technological contexts.
ntRSE core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
Engineered to enhance data processing efficiency, the TCP/IP Offload Engine by Chevin Technology offers a significant boost in networking tasks by transferring processing workloads from CPUs to faster-processing hardware. This IP core supports 10 and 25Gbps data rates, allowing it to handle substantial data transfer needs frequently seen in distributed systems and cloud environments, reducing latency and freeing up CPU resources for other critical functions. Achieving optimal throughput and low latency, this offload engine is ideal for high-performance computing environments where speed and efficiency are non-negotiable. It excels in scenarios where large sets of data need to be managed efficiently, ensuring that network performance is not a bottleneck in overall system performance. Key to its operation is the ability to maintain consistent performance across various implementations, particularly those that leverage advanced FPGA platforms. This core streamlines networking tasks while simultaneously supporting scalability, making it a practical and efficient solution for enterprise-level networking projects.
The 10G TCP Offload Engine from Intilop brings a transformative approach to network protocol processing. Designed to handle TCP processing tasks, this engine ensures efficient data transmission by offloading TCP processing from the CPU, thus optimizing the resources available for other critical computing tasks. With features focused on reducing latency and increasing throughput, the 10G TOE is ideal for high-performance computing environments and data centers where speed and efficiency are paramount. The engine showcases Intilop's core expertise in delivering ultra-reliable and rapid networking solutions, providing support for multiple concurrent sessions with consistent low latency. Professionals in cloud services and enterprise networking will find the integration capabilities of the 10G TOE highly beneficial, as it supports a comprehensive suite of features that extend beyond traditional TCP processing, reinforcing security and operational efficiency.
ntRSD_UF core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length, maximum number of parity symbols as well as I/O data width, internal datapath and decoding engines parallelism. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD_UF core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The core is designed and optimized for applications that need very high throughput data rates. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
CLOP Technologies' 60GHz Wireless Solution offers businesses an impressive alternative to traditional networking systems. Leveraging the IEEE 802.11ad WiFi standard and Wireless Gigabit Alliance MAC/PHY specifications, this solution achieves a peak data rate of up to 4.6Gbps. This makes it particularly suited for applications that require significant bandwidth, such as real-time, uncompressed HD video streaming and high-speed data transfers — operations that are notably quicker compared to current WiFi systems. The solution is engineered to support 802.11ad IP networking, providing a platform for IP-based applications like peer-to-peer data transfer and serving as a router or access point. Its architecture includes a USB 3.0 host interface and mechanisms for RF impairment compensation, ensuring both ease of access for host compatibility and robust performance even under high data rate operations. Operating on a frequency band ranging from 57GHz to 66GHz, the wireless solution utilizes modulation modes such as BPSK, QPSK, and 16QAM. It incorporates forward error correction (FEC) with LDPC codes, providing various coding rates for enhanced data integrity. Furthermore, the system boasts AES-128 hardware security, with quality of service maintained through IEEE 802.11e standards.
The Complete 5G NR Physical Layer solution by AccelerComm is meticulously optimized for 3GPP 5G NTN networks, aiming to enhance link performance with leading SWaP (Size, Weight, and Power) parameters. This solution supports a variety of applications including broadband, D2D (Direct to Device), and defense. With its openly licensable IP, available across multiple platforms such as arm processors, AI engines, and FPGA, it ensures the necessary flexibility for broad architecture compatibility. Complete reference systems facilitate early integration and testing, while additional consulting services provide expertise in early project phases.
The eSi-Comms suite from EnSilica stands as a highly parametizable set of communications IP, integral for developing devices in the RF and communications sectors. This suite focuses on enhancing wireless performance and maintaining effective communication channels across various standards. The modular design ensures adaptability to multiple air interface standards such as Wi-Fi, LTE, and others, emphasizing flexibility and customizability.\n\nThis communication IP suite includes robust components optimized for low-power operation while ensuring high data throughput. These capabilities are particularly advantageous in designing devices where energy efficiency is as critical as communication reliability, such as in wearables and healthcare devices.\n\nMoreover, eSi-Comms integrates seamlessly into broader system architectures, offering a balanced approach between performance and resource utilization. Thus, it plays a pivotal role in enabling state-of-the-art wireless and RF solutions, whether for next-gen industrial applications or advanced consumer electronics.
SMPTE ST 2110 is a sophisticated protocol designed to facilitate the transport of media over IP networks, commonly used in broadcast and professional AV settings. This IP solution enhances the ability to transmit a variety of media types such as video, audio, and ancillary data via IP, leveraging the modularity to achieve optimal resource efficiency. Supporting an array of sub-standards, including uncompressed video (ST 2110-20) and compressed video (ST 2110-22), this IP bolsters transmission quality and reliability, ensuring consistent system timing and seamless traffic shaping. With its robust support for both gateway and synthetic essence operations, SMPTE ST 2110 enables effective integration with legacy systems and ensures a future-ready setup for the transmission of high-quality media content over IP. The core is highly configurable, allowing users to tailor features according to specific broadcast requirements while maintaining resource efficiency. By utilizing only necessary RTL logic, it minimizes overhead while offering a versatile solution for both professional AV equipment and broadcast systems. Integrated into an ecosystem of proven interoperable standards, this IP ensures smooth transitions between digital and traditional workflows, establishing itself as a pivotal component in AV-over-IP infrastructures. The design includes capabilities to handle various media types, making it adaptable to different operational needs. Nextera’s SMPTE ST 2110 IP is supported by a comprehensive reference design project, inclusive of necessary drivers and control software, enabling rapid system prototyping and deployment. Customers benefit from a well-documented setup that fosters swift development cycles and reduces time-to-market, underpinned by Nextera's emphasis on sustained performance and innovation within IP media experiences.
The IPM-NVMe Device is crafted to empower developers to build custom hardware accelerators and SSD-like applications. Offering a high degree of customization, it acts as a foundation upon which cutting-edge applications can be realized. With its NVMe compliance, developers can integrate this IP to create high-performance storage solutions that are both adaptable and efficient. This module's versatility is exemplified by its support for enhanced data transfer rates, making it a suitable choice for environments demanding rapid data processing. The IPM-NVMe Device can be deployed in scenarios that require robust data handling capabilities while maintaining performance integrity. Designed with modularity in mind, the IPM-NVMe Device IP allows for the implementation of custom features, facilitating innovations such as new data management protocols, hardware accelerations, and more. Its deployment simplifies the challenging task of creating bespoke SSD solutions tailored to specific market needs and technological advancements.
The Centralized Network Configurator (CNC) developed by Comcores serves as a pivotal component of Time-Sensitive Networking (TSN) infrastructure. Aimed at coordinating TSN-based Ethernet networks, the CNC is designed to manage and optimize traffic flows, synchronizing network behaviors across various devices and network nodes. This synchronization is vital for applications requiring precise timing and reliable data exchange, especially in automotive, industrial, and aerospace environments. The CNC supports advanced TSN standards, ensuring network components work harmoniously by scheduling network resources with minimal delay and maximum efficiency. Through such precise configuration, it enhances the overall resiliency and adaptability of the network, meeting stringent demands for data integrity and timing accuracy.
Naneng Microelectronics offers a versatile Universal High-Speed SERDES capable of operating in a broad range of speeds from 1Gbps to 12.5Gbps. This SERDES is engineered to provide seamless and agile data transmission, underpinning critical communications infrastructure in various applications. The high-speed capabilities of this serializer/deserializer underline its suitability for high-performance networking solutions. Its flexible deployment options make it an ideal candidate for integration in a variety of system architectures, promoting a balance between speed and signal integrity. The design includes robust features to counter signal degradation and maintain the integrity of transmitted data, ensuring reliable operation across extensive data networks. Support for high data rates ensures this SERDES component meets and exceeds industry standards, delivering enhanced data throughput and supporting next-generation electronic systems. With adaptability at its core, the Universal High-Speed SERDES exemplifies comprehensive technological solutions in the semiconductor industry.
Offering a seamless radio communication solution, ShortLink’s Complete RF Transceiver for 433, 868, and 915 MHz comes packed with a robust set of features crafted to enhance wireless connectivity. This transceiver complies with the IEEE 802.15.4 standard, offering reliable data transfer in Sub-GHz bands renowned for their long-range capabilities. With transmit power adjustable from -20 to +8 dBm, the transceiver excels in scenarios demanding energy efficiency and vast reach. Supporting data rates up to 250 kbps, it's ideal for various IoT applications offering dependable indoor and outdoor connectivity. Designed for easy integration, the RF transceiver incorporates built-in voltage regulators, a bandgap reference, and bias generation to simplify system-level implementation. One of its standout capabilities is its ability to adopt custom radio protocols, enabling tailored communication paths that can significantly reduce power consumption and extend battery life. With its support for multiple global frequencies, the design ensures a wide applicability range across different regions, making it the perfect choice for developers looking to harness Sub-GHz for expansive communication reach. The crystal oscillators within provide high stability for clock generation, ensuring precise system operation. This tightly integrated RF solution does away with the need for additional radio chips, allowing for a reduced bill-of-materials (BOM) and a more compact final product footprint. The transceiver is compatible with a variety of process technologies, adding another layer of flexibility for system designers to achieve the perfect balance between performance and energy efficiency.
The 5G NR LDPC Decoder resource by Mobiveil supports advanced LDPC decoding capabilities optimized for modern telecommunication needs. Employing the Min-Sum LDPC decoding algorithm, it allows for programmable bit widths and features early exit iteration capabilities. Support for Hybrid Automatic Repeat Request (HARQ) ensures robustness by accumulating computed LLR values, increasing its efficacy in error correction scenarios.
The RecAccel N3000 AI Inference Chip is at the forefront of AI technology, specifically crafted to handle vast amounts of data for real-time inference tasks. Aimed at enhancing machine learning deployments, this chip offers impeccable efficiency and speed, allowing enterprises to harness the full potential of AI-driven insights. With its fine-tuned ASIC design, the chip is ideal for deep learning models, particularly in recommendation systems that demand quick, accurate results. It effectively distributes workloads away from traditional CPUs, reducing computational stress and improving overall performance across digital platforms. Such optimization is critical for businesses that are scaling AI capabilities in competitive markets. Designed for flexibility, the RecAccel N3000 can seamlessly integrate into a variety of system configurations, providing a reliable base for expanding AI functions. Its energy-efficient operation supports sustainable IT strategies, ensuring that companies can pursue innovative solutions without incurring excessive energy usage costs.
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