The Atrevido is a 64-bit RISC-V core designed for out-of-order processing, providing exceptional performance for applications needing high bandwidth and low latency. It features a 2/3/4-wide configurable out-of-order issue and completion mechanism, ensuring a seamless handling of complex, memory-intensive operations. The core is multiprocessor ready, equipped with direct hardware support for unaligned memory accesses, and supports various RISC-V extensions for enhanced functionality.
This IP is particularly adept at handling machine learning workloads, key-value stores, and recommendation systems, thanks to its integration with Semidynamics' Gazzillion Misses™ technology. This technology enables the Atrevido core to sustain full memory bandwidth even with smaller processing cores, minimizing the need for a large silicon footprint. With support for the RISC-V Vector Specification 1.0, Atrevido is vector-ready, allowing for dense encoding of computational instructions and efficient handling of sparse tensor weights.
Additional features of the Atrevido core include its Linux readiness, with full MMU support, and its compatibility with cache-coherent multiprocessing environments. This makes it beneficial for constructing systems on chips that require numerous cores, delivering scalability and performance tailored to extensive processing needs.
