Avispado is a sophisticated 64-bit RISC-V core that emphasizes efficiency and adaptability within in-order execution frameworks. It's engineered to cater to energy-efficient SoC designs, making it an excellent choice for machine learning applications with its compact design and ability to seamlessly communicate with RISC-V Vector Units. By utilizing the Gazzillion Misses™ technology, the Avispado core effectively handles high sparsity in tensor weights, resulting in superior energy efficiency per operation.
This core features a 2-wide in-order configuration and supports the RISC-V Vector Specification 1.0 as well as Semidynamics' Open Vector Interface. With support for large memory capacities, it includes complete MMU features and is Linux-ready, ensuring it's prepared for demanding computational tasks. The core's native CHI interface can be fine-tuned to AXI, promoting cache-coherent multiprocessing capabilities.
Avispado is optimized for various demanding workloads, with optional extensions for specific needs such as bit manipulation and cryptography. The core's customizable configuration allows changes to its instruction and data cache sizes (I$ and D$ from 8KB to 32KB), ensuring it meets specific application demands while retaining operational efficiency.
