The BlueLynx Chiplet Interconnect offers an advanced die-to-die interconnect solution, tailored to meet the rigorous demands of contemporary chiplet designs. With support for Universal Chiplet Interconnect Express (UCIe) and the Open Compute Project's Bunch of Wires (BoW), this IP establishes a robust physical and link layer interface for chiplet communications. It's built to connect efficiently with on-die bus standards like AMBA AXI and ACE, streamlining the process of linking chiplets within advanced package configurations.
Technologically sophisticated, BlueLynx supports a variety of fabrication nodes ranging from 16nm down to 3nm, ensuring compatibility across multiple semiconductor foundries. This interconnect solution is silicon-proven and enables not only rapid development but also minimizes the traditional risks associated with new designs. Clients receive a comprehensive ASIC integration package, including platform software and design references, which allows for swift silicon bring-up and ensures that first-pass silicon achieves expected operational standards.
The architecture of BlueLynx is designed to be both customizable and efficient. With data rates stretching from 2 Gb/s up to over 40 Gb/s, and low power consumption underpinning its design, BlueLynx manages to provide a high bandwidth density of over 15 Tbps/mm². This results in optimal performance scaling across diverse applications while accommodating advanced 3D packaging options. The PHY component of the IP is specifically designed for high compatibility and minimal latency, built on the architecture that supports configurable serialization and deserialization ratios, multiple PHY slices, along with detailed specifications for bump pitch and package applications.
