The CT25205 Digital IP core is engineered to provide the core building blocks for 10BASE-T1S Ethernet applications, including PMA, PCS, and PLCA Reconciliation Sublayer adherence. Written in Verilog 2005 HDL, it is fully synthesizable with standard cells and FPGA, working cohesively with standard IEEE CSMA/CD Ethernet MAC via MII. The unit supports advanced PLCA features, enabling seamless communication with existing MAC devices. Connectivity is ensured through a standard OPEN Alliance 10BASE-T1S PMD Interface, creating an optimal solution for Zonal Gateway SoCs and MCUs adopting innovative 10BASE-T1S communication.
