CVC is a comprehensive Verilog Hardware Description Language (HDL) simulator compliant with IEEE 1364 2005 standards. This simulator is capable of compiling Verilog into native machine instructions for X86_64 architecture, producing a fast-executing native Linux binary. Known for its speed, CVC matches or exceeds the performance of any commercial full 1364 2005 simulator available.
This simulator supports large-scale gate and RTL designs with its 64-bit CVC64 version, which, while faster than the 32-bit version, results in larger binaries. Key features include the latest VCD/EVCD/FST design state dump formats and parallel FST generation capabilities using up to two additional X86 cores for enhanced performance. It also supports a range of simulation modes and evaluation algorithms, ensuring adaptability and fast elaboration during initial design phases.
Furthermore, CVC includes comprehensive features like built-in toggle coverage, full PLI support, and options to simulate in both compiled and interpreted modes. It's tailored for integration with software such as GTKWave, making it an ideal solution for machine-generated Verilog simulations, ensuring seamless and speedy execution. CVC's open-source licensing allows for widespread, editable use among electronic designers.
