All IPs > Security IP > Cryptography Cores
In today's interconnected world, the importance of secure communication and data protection cannot be overstated. Cryptography cores are a crucial subset of semiconductor IPs designed to provide foundational security solutions across a variety of electronic systems. At their core, these IPs implement complex algorithms that ensure the confidentiality, integrity, and authenticity of data being processed and exchanged.
The cryptography cores available in this category offer a diverse range of features tailored to different security needs. From symmetric-key algorithms like AES to asymmetric-key systems such as RSA and ECC, these cores ensure that systems can securely encrypt and decrypt information, protecting it from unauthorized access and tampering. By embedding these cryptographic functions directly into hardware, it becomes possible to achieve faster processing speeds and higher levels of security compared to software implementations.
These semiconductor IPs are widely used in applications where data security is paramount. This includes, but is not limited to, industries such as finance, telecommunications, and healthcare. Devices utilizing cryptography cores can range from secure payment systems, ensuring safe financial transactions, to mobile devices for secure communications, to medical devices that safeguard sensitive health information. Additionally, with the rise of the Internet of Things (IoT), cryptography cores are increasingly crucial in providing secure connections for a myriad of smart devices.
By integrating cryptography cores into your designs, you not only improve security but also future-proof your products against many potential vulnerabilities. As security threats continue to evolve, having robust cryptography solutions is essential for maintaining trust and reliability in your products and services. Whether you're developing a new application or enhancing an existing one, our category of cryptography cores offers the semiconductor IP solutions you need to meet today's stringent security demands.
The Akida IP is a groundbreaking neural processor designed to emulate the cognitive functions of the human brain within a compact and energy-efficient architecture. This processor is specifically built for edge computing applications, providing real-time AI processing for vision, audio, and sensor fusion tasks. The scalable neural fabric, ranging from 1 to 128 nodes, features on-chip learning capabilities, allowing devices to adapt and learn from new data with minimal external inputs, enhancing privacy and security by keeping data processing localized. Akida's unique design supports 4-, 2-, and 1-bit weight and activation operations, maximizing computational efficiency while minimizing power consumption. This flexibility in configuration, combined with a fully digital neuromorphic implementation, ensures a cost-effective and predictable design process. Akida is also equipped with event-based acceleration, drastically reducing the demands on the host CPU by facilitating efficient data handling and processing directly within the sensor network. Additionally, Akida's on-chip learning supports incremental learning techniques like one-shot and few-shot learning, making it ideal for applications that require quick adaptation to new data. These features collectively support a broad spectrum of intelligent computing tasks, including object detection and signal processing, all performed at the edge, thus eliminating the need for constant cloud connectivity.
Overview: Cybersecurity IPs offer a range of essential security features to protect your digital assets and sensitive information. From True Random Number Generators (TRNG) to advanced encryption algorithms like AES, DES, 3DES, and cryptographic hash functions like SHA, as well as RSA for secure key exchange and digital signatures, the IPs provide a comprehensive suite of tools to safeguard your data. Key Features: True Random Number Generator (TRNG): Generates unpredictable and unbiased random numbers for cryptographic applications. Advanced Encryption Standard (AES): Provides robust encryption with symmetric key algorithms for securing data. Data Encryption Standard (DES) and Triple DES (3DES): Implement legacy encryption algorithms for data protection. Hash Functions: Includes secure cryptographic hash functions like SHA (Secure Hash Algorithm) for data integrity verification. RSA: Enables secure key exchange, encryption, and digital signatures for secure communication. These cybersecurity IPs are designed to meet the stringent security requirements of modern applications, ensuring the confidentiality, integrity, and authenticity of your data.
The aiWare Neural Processing Unit (NPU) is an advanced hardware solution engineered for the automotive sector, highly regarded for its efficiency in neural network acceleration tailored for automated driving technologies. This NPU is designed to handle a broad scope of AI applications, including complex neural network models like CNNs and RNNs, offering scalability across diverse performance tiers from L2 to more demanding L4 systems. With its industry-leading efficiency, the aiWare hardware IP achieves up to 98% effectiveness over various automotive neural networks. It supports vast sensor configurations typical in automotive contexts, maintaining reliable performance under rigorous conditions validated by ISO 26262 ASIL B certification. aiWare is not only power-efficient but designed with a scalable architecture, providing up to 1024 TOPS, ensuring that it meets the demands of high-performance processing requirements. Furthermore, aiWare is meticulously crafted to facilitate integration into safety-critical environments, deploying high determinism in its operations. It minimizes external memory dependencies through an innovative dataflow approach, maximizing on-chip memory utilization and minimizing system power. Featuring extensive documentation for integration and customization, aiWare stands out as a crucial component for OEMs and Tier1s looking to optimize advanced driver-assist functionalities.
The Talamo Software Development Kit (SDK) is a comprehensive toolset designed to streamline the development and deployment of neuromorphic AI applications. Leveraging a PyTorch-integrated environment, Talamo simplifies the creation of powerful AI models for deployment on the Spiking Neural Processor. It provides developers with a user-friendly workflow, reducing the complexity usually associated with spiking neural networks. This SDK facilitates the construction of end-to-end application pipelines through a familiar PyTorch framework. By grounding development in this standard workflow, Talamo removes the need for deep expertise in spiking neural networks, offering pre-built models that are ready to use. The SDK also includes capabilities for compiling and mapping trained models onto the processor's hardware, ensuring efficient integration and utilization of computing resources. Moreover, Talamo supports an architecture simulator which allows developers to emulate hardware performance during the design phase. This feature enables rapid prototyping and iterative design, which is crucial for optimizing applications for performance and power efficiency. Thus, Talamo not only empowers developers to build sophisticated AI solutions but also ensures these solutions are practical for deployment across various devices and platforms.
The Polar ID Biometric Security System offers an advanced, secure face unlock capability for smartphones, utilizing groundbreaking meta-optics technology to capture the full polarization state of light. Unlike traditional biometric systems, Polar ID distinguishes the unique polarization signature of human facial features, which adds an additional security layer by detecting the presence of non-human elements like sophisticated 3D masks. This system eliminates the need for multiple complex optical modules, thus simplifying smartphone design while enhancing security. Designed to fit the most compact form factors, Polar ID uses a near-infrared polarization camera at 940nm paired with active illumination. This configuration ensures functionality across various lighting conditions, from bright outdoor environments to complete darkness, and operates effectively even when users wear sunglasses or face masks. Smartphone OEMs can integrate this secure and cost-effective solution onto a wide range of devices, surpassing traditional fingerprint sensors in reliability. Polar ID not only offers a higher resolution than existing solutions but does so at a reduced cost compared to structured light setups, democratizing access to secure biometric authentication across consumer devices. The system's efficiency and compactness are achieved through Metalenz's meta-optic innovations, offering consistent performance regardless of external impediments such as lighting changes.
Securyzr iSSP is an integrated Security Services Platform designed by Secure-IC to offer comprehensive lifecycle management of device security. It provides zero-touch security lifecycle services that encompass provisioning, firmware updates, security monitoring, and device identity management. The platform employs a cloud-based architecture, enabling real-time updates and management of security protocols across a fleet of devices. Securyzr iSSP supports Post-Quantum Cryptography standards, ensuring readiness for future cryptographic challenges. This platform integrates seamlessly into diverse system environments, facilitating the protection of sensitive data through robust secure boot processes and key isolation techniques. It structures security around a core Root-of-Trust component named Securyzr iSE neo, which offers anti-tampering protection and dual computation for enhanced security. The platform aligns with an organization's security goals by providing customizable protective measures that are scalable to various applications. Securyzr iSSP is designed to maintain high security levels without compromising system performance or efficiency. By leveraging the latest advancements in cryptography and security protocols, it ensures the resiliency of systems against both physical and remote threats. This platform aids organizations in navigating the increasingly complex landscape of digital security challenges, providing a robust foundation for their cybersecurity strategies.
FIPS 140-3 CAVP-compliant, compact PQC hardware acceleration for subsystems PQPlatform-CoPro combines hash-based and lattice-based post-quantum cryptography that can be added to an existing security subsystem. It can be optimized for minimum area, maintaining high-performance, and is designed to be run by an existing CPU using PQShield-supplied firmware, meaning it involves low integration effort and flexible configurations to support a wide variety of use cases, including quantum-safe secure boot. Solutions are available for hardware acceleration of SHA-3, SHAKE, ML-KEM, ML-DSA, alongside traditional cryptography. In addition, PQPlatform-CoPro can be configured with side-channel protection. PQPlatform-CoPro is covered by multiple PQShield implementation patents.
Post-quantum Software Development Kit Provides easy-to-use software implementations of both post-quantum and classical cryptographic primitives. It’s designed with prototyping and experimentation in mind, consisting of an integration of PQShield’s PQCryptoLib library with two popular high-level cryptography libraries: OpenSSL and mbedTLS. OpenSSL: a widely-adopted secure-communication library mbedTLS: primarily intended for use in embedded system and IoT deployments
Secure Hash Algorithms (SHA) play a critical role in data integrity and security. The SHA family, including SHA-1, SHA-2, and the widely used SHA-256, provides a method for verifying data through unique hash values that represent original content. Helion Technology designs high-performance and resource-efficient hash cores that cater to both high-speed and low-power applications. Hash functions are integral in digital signatures, message authentication, and integrity verification, ensuring that transmitted or stored data remains unchanged and secure. By aligning the hashing capabilities with robust FPGA and ASIC technologies, Helion offers solutions that enhance data security without imposing hefty resource demands. These cores are engineered for low area and power consumption, making them ideal for compact and energy-sensitive applications.
The AES-XTS standard, as outlined by NIST and IEEE, provides a critical security layer for disk-level data encryption. Through its unique 'tweakable' cipher design, AES-XTS is particularly effective in securing data at rest on disk drives. Helion's AES-XTS solutions are tailored for applications ranging from single drives to extensive storage arrays, offering configurations that balance speed and hardware resource use. With throughput capacities exceeding 64 Gbps, these cores can support both high and low-speed storage applications. Benefiting from Helion's dedication to flexible and efficient designs, these cores ensure consistent data protection across various environments, making them suitable for use in both commercial and industrial sectors. They are available for implementation in leading FPGA and ASIC technologies, ensuring adaptability and integration ease.
Up to 1M KeyEnc/sec with improved power efficiency PQPerform-Lattice is a powerful hardware-based product designed for high throughput, high-performance, and high speed. It adds post-quantum cryptography for applications that typically handle a large number of transactions, such as high-capacity network hardware applications and secure key management HSMs. Optimizable for secure boot, as well as other use-cases, PQPerform-Lattice supports FIPS 204 ML-DSA for quantum-secure digital signature verification, as well as FIPS 203 ML-KEM for quantum key exchange. PQPerform-Lattice supports AXI4, PCIe, and is deployable in multiple instances, making it a powerful solution for existing systems and infrastructure requirements.
Specially engineered for the automotive industry, the NA Class IP by Nuclei complies with the stringent ISO26262 functional safety standards. This processor is crafted to handle complex automotive applications, offering flexibility and rigorous safety protocols necessary for mission-critical transportation technologies. Incorporating a range of functional safety features, the NA Class IP is equipped to ensure not only performance but also reliability and safety in high-stakes vehicular environments.
FIPS 140-3 CAVP-compliant, compact lattice-based hardware PQC engine PQPlatform-Lattice is a compact FIPS 140-3 CAVP-compliant, PQC engine that adds post-quantum support for hardware components and embedded devices, using lattice-based cryptographic algorithms such as ML-KEM (FIPS 203) for post-quantum key exchange, and ML-DSA (FIPS 204) – post-quantum digital signature verification. It provides secure acceleration of lattice-based PQC alongside support for traditional cryptography. Its use cases include strong user authentication, protecting hardware keys, and small-footprint, configurable side-channel protection. PQPlatform-Lattice is designed for minimal area as well as maximum compatibility and can be deployed with optional firmware-backed side-channel countermeasures. It is covered by multiple PQShield implementation patents.
AES-GCM, or AES Galois Counter Mode, combines encryption with authentication to provide both data confidentiality and integrity. Originally developed for high-throughput applications, it can efficiently use pipelining and parallel processing to achieve exceptional speeds. Helion's AES-GCM solutions are tailored to meet diverse data rate requirements, ranging from several megabits to over 40 Gbps. The solutions are versatile across various technologies, offering unparalleled flexibility and performance. Beyond speed, Helion's AES-GCM cores are noted for their compact design, ensuring minimal resource utilization in both FPGA and ASIC implementations. Designed to fit scalable applications, these cores ensure robust data protection in high-demand environments, like networking and data storage.
Trilinear Technologies' HDCP Encryption-Decryption Engine is a sophisticated solution designed to safeguard digital content as it traverses various transmission channels. This engine is compliant with the HDCP standards 1.4 and 2.3, offering robust protection mechanisms to ensure that digital media investments are secure from unauthorized access and piracy. The engine’s hardware acceleration capabilities represent a crucial advantage, significantly reducing the load on the system processor while maintaining real-time encryption and decryption functions. This not only enhances performance but also extends the operational life of the hardware involved, making it suitable for high-demand media applications across sectors such as broadcast, entertainment, and corporate environments. Trilinear’s HDCP Encryption-Decryption Engine ensures compatibility with a wide array of consumer and professional-grade video equipment, providing seamless protection without interference in media quality or transmission speed. Its flexible integration options allow it to be smoothly incorporated into existing infrastructures, whether in standalone media devices or complex SoC architectures. Supported by comprehensive software resources, the HDCP Encryption-Decryption Engine provides an all-encompassing solution that includes necessary software stacks for managing device authentication and link maintenance. Its ability to safeguard high-definition content effectively makes it an invaluable asset for entities focused on secure content delivery and rights management.
FIPS 140-3 CAVP compliant ultra-fast, compact, and power efficient secure hash acceleration PQPlatform-Hash is a power side-channel accelerator, supporting a wide range of Hash-Based Signature Schemes (HBSS). PQPlatform-Hash deploys tried-and-tested HBSS including quantum-safe LMS and XMSS (not hybrid). It provides acceleration of HBSS in embedded devices, especially where high throughput is required, or resource constraints necessitate minimal additional area. For example, PQPlatform-Hash is a solution for secure first-stage boot loading with hash-based signature schemes. HBSS offer different trade-offs of memory/area to lattice-based schemes, and as a result, PQPlatform-Hash is ideally suited for smaller key sizes, larger signature sizes, and processing times for key generation, signature generation and verification.
The eSi-Crypto suite by EnSilica is a comprehensive collection of cryptographic IP cores designed for both ASIC and FPGA architectures, aiming for minimal resource consumption while ensuring high throughput. A key component within this suite is the True Random Number Generator (TRNG), which adheres to NIST 800-22 standards and is offered as a hard macro in target technologies. Its configurable options are tailored to balance resource efficiency with throughput, making it essential for robust encryption solutions. These IP cores are available as stand-alone modules or integrated with AMBA APB/AHB or AXI bus interfaces.\n\nThe suite supports a variety of cryptographic algorithms such as CRYSTALS Kyber, CRYSTALS Dilithium, elliptic curve cryptography (ECC/ECDSA), RSA, AES, SHA1/SHA2/SHA3, ChaCha20, Poly1305, and TDES/DES. These diverse implementations can be tailored for specific use cases, including high-throughput core configurations ideal for applications like V2X communications. Additionally, the suite's ECC/ECDSA capabilities provide secured digital signature mechanisms, critical for applications requiring stringent data integrity and authenticity.\n\nEnSilica's dedication to cryptographic excellence is further evidenced in their sophisticated handling of secure web-server implementations. By leveraging their ultra-low-power accelerators, particularly for algorithms like ChaCha20 and Poly1305, eSi-Crypto reduces computational overhead while optimizing security performance. This makes the suite a preferred choice for customers seeking efficient and reliable cryptographic solutions across varied technology platforms.
The NS Class is Nuclei's crucial offering for applications prioritizing security and fintech solutions. This RISC-V CPU IP securely manages IoT environments with its highly customizable and secure architecture. Equipped to support advanced security protocols and functional safety features, the NS Class is particularly suited for payment systems and other fintech applications, ensuring robust protection and reliable operations. Its design follows the RISC-V standards and is accompanied by customizable configuration options tailored to meet specific security requirements.
The FPGA Lock Core is an innovative FPGA solution designed to secure FPGAs and hardware against unauthorized access and counterfeiting, leveraging a Microchip ATSHA204A crypto authentication IC. It reads a unique ID, generates a 256-bit challenge, and uses secure hashing to verify the hardware's authenticity, ensuring hardware integrity in sensitive applications like military and medical fields. This solution allows hardware protection against IP theft by enforcing authentication and disables FPGA functionality if unauthorized access is detected. The core utilizes minimal logic resources and one FPGA pin, communicating through a bidirectional open drain link. The clarity of this system is enhanced by providing the core in VHDL, allowing users to thoroughly understand its functionality, supported by example designs on Cyclone10 and Artix 7 boards, catering to both Intel and Xilinx FPGA platforms. Complementing this security measure is the Key Writer Core, which allows programming of custom secret keys into the ATSHA204A in situ on assembled boards, ensuring a seamless integration with the FPGA Lock system. Available for various FPGA platforms, the Efinix version, distributed with TRS Star, expands its applicability, with webinars and user guides offering in-depth implementation insights.
The Advanced Encryption Standard (AES) provides robust encryption for data security applications. Originally chosen by the National Institute of Standards and Technology (NIST) in the late 1990s, AES became the standard for encryption, replacing the older DES system. Helion Technology was at the forefront of this shift, offering a variety of AES IP cores suitable for ASIC and FPGA technologies. Helion's range of AES solutions can address different application needs from minimal area to high-speed data processing. This allows customization and scalability to fit specific encryption requirements. AES includes multiple operational modes, such as CBC, CTR, OFB, and more, enabling users to choose based on throughput and security priorities. With core offerings that cover ultra-low gate count applications to high throughput scenarios, Helion's AES cores are designed to fit seamlessly into a wide range of systems. Furthermore, by embracing process nodes from leading foundry groups, these cores ensure efficient implementation in diverse commercial settings.
Belonging to the AONSens™ Neural Network series, the AON1020 is crafted for both voice and audio recognition alongside other sensor applications. Recognized for its hectic performance in minimal power environments, AON1020's AI processing engine is available in Verilog RTL, making it accessible for use in ASIC and FPGA technologies. Engineered for scenarios like human activity detection through sensor applications, this IP provides always-on multi-wake-word detection and on-device voice command recognition. Its features ensure adaptability even in environments characterized by noise, offering stable performance irrespective of user or environmental changes. The AON1020's robust architecture accommodates sensor fusion applications, enhancing its capability in multi-sensor environments where it can decipher activities like running or walking. This offers developers potent solutions in expanding markets such as smart home automation and industrial IoT applications.
The AES Core by Algotronix is a sophisticated solution tailored for securing data using advanced encryption methods. This core supports various encryption modes such as ECB, CBC, CTR, CFB, OFB, CCM, GCM, and XTS, which cater to a wide array of applications requiring different levels and methods of data protection. The flexibility in supported modes allows for tailored implementations in different security-critical environments. This encryption core is known for its deployment among prominent defense electronics organizations, and it has been operational within several NATO member states, testifying to its high-level security assurance and operational readiness in sensitive global contexts. Offered typically in source code form, the AES Core ensures that users can perform thorough security audits and tailor enhancements specific to their security policies and infrastructural needs. This capability positions Algotronix's offering as an optimal choice for organizations prioritizing stringent security postures.
The NI Class RISC-V CPU IP caters to communication, video processing, and AI applications, providing a balanced architecture for intensive data handling and processing capabilities. With a focus on high efficiency and flexibility, this processor supports advanced data crunching and networking applications, ensuring that systems run smoothly and efficiently even when managing complex algorithms. The NI Class upholds Nuclei's commitment to providing versatile solutions in the evolving tech landscape.
The Individual IP Core Modules by ResQuant are comprehensive components engineered to support diverse post-quantum cryptographic standards, including Dilithium, Kyber, XMSS, SPHINCS+, AES, and the SHA-2 family. These modules offer organizations the flexibility to select specific cryptographic functionalities tailored to their security needs, without the necessity of entire systems or hardware changes. Each module is designed to integrate easily into existing infrastructure, ensuring minimal disruption while enhancing security measures against potential future quantum threats. This approach allows industries to gradually implement PQC standards, ensuring a seamless transition to quantum-resistant cryptographic measures. Tailored for flexibility, the ResQuant Individual IP Core Modules can be used across a wide array of applications, from IoT devices to complex military and IT systems. By offering component-level integration, these modules empower companies to future-proof their offerings incrementally while maintaining robust security practices in their operations.
Suite-Q SW is a versatile cryptographic software library provided by PQSecure, crafted to enhance the security capabilities of devices through efficient cryptographic processing. Available in portable C code and optimized assembly variations, Suite-Q SW caters to a wide array of processors, including both general-purpose and embedded CPUs. This software library is engineered to optimize code size, stack usage, and overall performance, allowing it to operate effectively even on memory-limited devices. It provides a comprehensive set of cryptographic functions including secure hashing, encryption, and digital signatures, designed to meet the demands of diverse security scenarios. The software solution is an ideal choice for developers seeking ease of integration, support for hardware offload, and customization for specific needs. Its plug-and-play architecture makes it straightforward to deploy across different platforms, providing a robust defense against modern security threats for IoT devices, mobile applications, and more.
Suite-Q HW is an integrated system-on-chip (SoC) solution by PQSecure designed to encapsulate complete cryptographic functionalities within a compact and efficient package. It targets both high-end servers and low-end embedded systems, offering a unified architecture that employs the same hardware accelerators across its different implementations. The hardware system integrates multiple cryptographic operations, including symmetric and asymmetric algorithms, within a streamlined chip design. This allows for a comprehensive offloading of cryptographic tasks, freeing up the main processor for other critical operations, and ensures rapid execution and enhanced performance. Additionally, Suite-Q HW's flexibility in configurations aids in balancing performance with silicon footprint, making it suitable for a diverse range of applications. Further, the solution is equipped with anti-tamper technologies and design features to resist side-channel attacks, a critical consideration in environments where secure operations are non-negotiable. Whether used in data-sensitive financial systems or IoT devices with limited computational resources, Suite-Q HW promises dependable security with optimal efficiency.
The Cyclone V FPGA with Integrated PQC Processor by ResQuant is a specialized product that comes pre-equipped with a comprehensive NIST PQC cryptography suite. This FPGA is tailored for applications requiring a robust proof-of-concept for quantum-safe implementations. It ensures seamless integration into existing systems, providing a practical platform for testing and deployment in quantum-secure environments. This product is available at a competitive price and represents an ideal starting point for entities looking to explore and adopt quantum-resilient technologies. Its configuration allows for straightforward implementation in diverse hardware infrastructures while offering a reliable option for organizations aiming to stay ahead in the evolving cyber security landscape. By incorporating the latest in cryptographic standards and ensuring vendor independence, the Cyclone V FPGA with Integrated PQC Processor by ResQuant effectively bridges current hardware technologies and future-proof security needs. It supports industry-wide applications, from IoT and ICT to automotive and military sectors, underscoring ResQuant's versatility in hardware security solutions.
Featuring G15, this IP is optimized for 2KB correction blocks, suitable for NAND devices with larger page sizes, such as 8KB. The design is aligned with methods seen in the G14X, but it extends its reach with longer codewords for comprehensive coverage of high-density NAND. The design supports a wide array of block sizes and configurational setups, making it highly adaptable to varying design needs. Additional error correction capabilities can be integrated based on client requirements, reinforcing its bespoke delivery.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
The DSHA2-512 core specializes in the SHA2-512 hashing algorithm, providing a highly efficient means to process hashing functions in data-intensive environments. It is designed to comply with FIPS PUB 180-4 standards, ensuring that it meets established guidelines for secure hashing operations necessary in a variety of industry settings. With interfaces that include APB, AHB, and AXI, the DSHA2-512 exhibits broad compatibility with existing digital infrastructures, enabling it to be deployed across a wide array of technology solutions. This core is ideal for sectors where ensuring data integrity and authenticity is critical, such as finance, governmental, and secure communications sectors. Its enhanced technical capabilities mean that the DSHA2-512 core supports extensive data processing requirements while maintaining the security integrity of hashes, making it an essential component for applications that demand reliable hash computation and data security.
AndeSoft SW Stack encompasses a comprehensive set of software building blocks and middleware optimized for AndesCore processors. This rich collection includes operating systems, libraries, drivers, and middleware components, all meticulously designed to enhance software development speed and quality. By providing ready-to-use components, AndeSoft enables developers to focus on crafting their application-specific solutions, significantly reducing time-to-market. Its seamless integration with AndeSight IDE further enhances development efficiency, supporting diverse operating systems and being adaptable to various processor configurations for optimal performance.
NeoPUF sets a high standard in semiconductor security by offering exceptionally fast random number generation capabilities that reach speeds up to 100 times faster than conventional methods. It is a versatile hardware security IP that forms the backbone of secure chips designed to combat evolving digital threats. NeoPUF's unique design offers an intrinsic level of security that harnesses the physical characteristics of silicon to create a naturally unclonable identifier for each chip. Used extensively in fields where security is paramount, NeoPUF helps ensure the integrity and confidentiality of data throughout the lifecycle of semiconductor devices. It's critically important in sectors such as IoT, automotive, and enterprise computing, where the cost of a security breach is high. The integration of NeoPUF provides a secure basis for implementing complex encryption keys and enhances the trustworthiness of digital transactions. By employing cutting-edge cryptographic measures, NeoPUF is considered a suitable foundation for future-proofing semiconductor systems against the anticipated quantum computing threats. It forms part of a comprehensive security solution, offering hardware-based security features that significantly enhance the reliability and safety of modern electronic devices.
The patented QDID PUF by Crypto Quantique utilizes quantum tunneling current variations to produce a unique identity in standard CMOS processes. This solution leverages oxide thickness variations and trap distributions in the gate oxide to create an unpredictable and unclonable physically unclonable function (PUF). As a hardware root-of-trust, it simplifies secure provisioning and emits high-entropy seeds resistant to side-channel attacks, supporting up to 256-bit security strength. The QDID PUF's robustness is confirmed through extensive testing, including adherence to NIST standards, making it an ideal choice for secure device identity and post-quantum cryptographic applications.
Fully autonomous, FIPS 140-3 CAVP compliant PQC subsystem PQPlatform-SubSys is a cryptographic subsystem, designed to provide offloaded cryptographic services with minimal integration effort and full autonomy from an existing security subsystem, as well as configurable side-channel protection. These services include post-quantum signature generation, verification, and secure key establishment. It’s built with optimal performance in mind, as well as crypto agility with its provision of traditional, PQ/T hybrid and fully post-quantum algorithms. PQPlatform-SubSys uses its built-in RISC-V CPU independently from the surrounding system, allowing cryptographic services to be offloaded efficiently from the system processor.
The G13/G13X series is tailored for 512B correction blocks, particularly used in NAND setups with 2KB to 4KB page sizes. While both variants are crafted to manage the demands of SLC NAND transitions to finer geometries, the G13X allows for correction of a higher number of errors. Designed to fit seamlessly into existing controller architectures, it enables extensions of current hardware and software capabilities without extensive new investments. It offers area optimization through parameter adjustments and supports a range of channel configurations for broad applicability.
The SHA-3 Crypto Engine from KiviCore offers an efficient and secure solution for cryptographic hashing, specifically designed to perform high-speed data integrity verification and authentication. Compliant with NIST's FIPS 202 standard, this IP core facilitates extensions such as SHAKE-128 and SHAKE-256 for customizable output lengths. Aimed at securing transactions and communications in today's networks, the core provides high throughput and resilient operations against timing-based side channel attacks. Its compact design fits both ASIC and FPGA environments while maintaining robust security assurance. Extensively verified and characterized for multiple high-performance scenarios, the SHA-3 core finds application in SSL and IPsec protocols, secure boot systems, blockchain processing, and other domains requiring trustable encryption. Its AMBA AXI4 interface allows for straightforward hardware integration alongside a comprehensive suite of software resources and support documentation.
The Alcora V-by-One HS Daughter Card by Parretto B.V. is designed to facilitate high-speed video data transmission with minimal wire insulation. Featuring V-by-One HS technology, it provides seamless connectivity for large video content transfer over fewer cables, supporting high-definition resolutions efficiently. Alcora's focus on V-by-One HS technology makes it suitable for applications where reduced cable clutter and high data transfer rates are necessary. It becomes an excellent choice for display applications that demand clean setups while transmitting vast amounts of data. By integrating this daughter card, system designers can achieve a streamlined architecture that supports robust video transmission without the associated clutter, keeping systems neat and efficient. Its compatible interface ensures it integrates well with existing video systems, offering scalable and future-proof solutions.
VeriSyno's Digital Systems and Security Solutions encompass a comprehensive set of offerings tailored to address the needs of secure data processing environments. These solutions feature a range of digital IP cores that can enhance the operational capabilities of processors, memory controllers, and communication interfaces. By leveraging these digital assets, VeriSyno aims to provide robust and efficient systems that prioritize security and performance. Designed to integrate seamlessly with existing hardware, these solutions are particularly critical in applications prone to demand high security, such as financial transactions and sensitive data processing. The security IPs ensure that data integrity and confidentiality are upheld, leveraging sophisticated encryption and protection mechanisms. Moreover, VeriSyno is agile in customizing its IP solutions to fit different process nodes and technological requirements, aiding in both rapid deployment and scalability of digital systems. This makes their offerings especially attractive to clients requiring high-end security implementations without compromising on performance or reliability.
SEMIFIVE’s AIoT Platform targets smart environmental ecosystems, offering convergence of AI capabilities with IoT frameworks. This platform enhances connectivity and intelligence in next-generation smart devices and facilities, integrating edge computing and AI capabilities to enable intelligent data processing and real-time action. The AIoT platform is equipped with multi-core processing capabilities, providing energy-efficient solutions suited for edge environments. This facilitates distributed AI computations right where data is generated, significantly improving response times and reducing backhaul costs compared to traditional centralized models. Designed to support a wide range of devices and systems, the platform allows developers to build solutions that are scalable and adaptable to various IoT applications. It provides comprehensive hardware-software co-design solutions, simplifying the development process for applications like smart homes, industrial IoT systems, and intelligent transportation networks.
The AES Encrypt/Decrypt IP provided by Secantec offers a highly secure solution for data encryption and decryption, supporting 128, 192, and 256-bit key lengths. Adhering to the Advanced Encryption Standard (AES), this IP ensures that data confidentiality is maintained across various platforms and applications. With its comprehensive encryption capability, this IP is pivotal in protecting sensitive data against unauthorized access, making it indispensable in secure communication systems, data storage solutions, and more. It provides a robust security framework that can be implemented efficiently within existing infrastructures. By leveraging the versatility of AES algorithms, the IP can be seamlessly integrated into a wide range of environments, from high-performance computing systems to portable devices requiring secure data channels. Its design ensures minimal latency and resource overhead, delivering a swift and reliable encryption mechanism.
Secure-IC's Post-Quantum Cryptography IP offers robust, future-ready security for digital communications, addressing the challenges of quantum computing on traditional encryption methods. This IP is crucial for systems that require long-term confidentiality and authenticity of data, ensuring they remain secure against threats posed by advancements in quantum computing. Designed to integrate seamlessly into existing hardware and software infrastructures, the Post-Quantum Cryptography IP is adaptable and scalable, providing flexibility in implementation. It supports a variety of cryptographic algorithms specifically chosen for their resistance to quantum attacks, ensuring they meet the highest security standards. By adopting this technology, systems can safeguard against potential future vulnerabilities that quantum processors might exploit. This IP is an essential component for industries looking to fortify their security measures, particularly in sensitive sectors such as defense, finance, and critical infrastructure. It provides a forward-thinking approach to cybersecurity, aligning with global trends and regulatory requirements for enhanced cryptographic solutions. By securing today’s systems against tomorrow’s threats, this IP is a strategic investment in sustained security resilience.
The CANsec Controller Core is an advanced security solution specifically tailored for the Controller Area Network (CAN) bus protocols commonly used in automotive applications. This core enhances the integrity and confidentiality of CAN network communications through robust encryption mechanisms, safeguarding against potential cyber threats. Designed for high compatibility, the CANsec Controller integrates smoothly into existing CAN infrastructures without the need for extensive reconfiguration. This adaptability allows automotive manufacturers to retrofit older models with contemporary security standards, thereby extending the lifecycle and safety of vehicles across all market segments. With its high-speed encryption and decryption processes, the CANsec Controller ensures real-time communications are not compromised. This efficiency is crucial in maintaining the latency constraints necessary for vehicle operations, especially as industries move towards more autonomous functionalities. The core's ability to secure internal communications helps manufacturers address growing cybersecurity concerns in today's connected vehicle landscape, ensuring secure data exchange within vehicular networks.
Tailored for applications requiring secure non-volatile memory, CrossBar's ReRAM as FTP/OTP Memory offers a refined solution for few-time programmable (FTP) and one-time programmable (OTP) needs. Leveraging the intrinsic properties of ReRAM technology, these applications benefit from reduced write requirements and minimized area without compromising security or performance. This ReRAM variant integrates effectively within standard CMOS processes, providing adaptability whether used independently or embedded within more complex systems. Its non-volatility and high density make it a preferred choice for secure applications where cost-efficient data integrity is essential. The technology supports diverse applications across numerous sectors including automotive, medical, and industrial systems, where quick response times and reliability are critical. The FTP/OTP ReRAM enables provisioning for physical unclonable functions (PUF), further enhancing its security capabilities. Such an implementation provides resistance to invasive attacks and maintains data integrity even under adverse conditions. These features position ReRAM as a powerful tool for managing sensitive data operations and broad pursuits in modern digital infrastructures.
The Customizable Cryptography Accelerator offered by ResQuant is designed to meet varied client needs with an extensive array of configurable options. It integrates seamlessly with all NIST PQC standards like Dilithium, Kyber, XMSS, and SPHINCS+, and is extendible with additional algorithms, including customer-specific implementations. The accelerator is built to be DPA, timing, and SCA resistant, and is AXI 4 ready, ensuring robust protection in a variety of applications. This innovation allows for customizable tuning in performance and size, addressing the specific security requirements of customers from various industries. The accelerator demonstrates ResQuant's commitment to flexibility and adaptability, enabling clients to implement cutting-edge encryption with ease. With ongoing enhancements to extend its capabilities, the accelerator stands as a critical component in defenses against future computational threats posed by quantum technologies. In addition to its technical capabilities, the ResQuant Customizable Cryptography Accelerator is engineered for efficient power use and minimized physical footprint, making it suitable for integration into a wide range of hardware setups. This solution underscores ResQuant's dedication to delivering high-security standards and unmatched versatility in cryptographic processing solutions.
The IPSEC Core by Algotronix is designed to secure IP communications by providing robust encryption and authentication mechanisms. Essential for ensuring data confidentiality and integrity over IP networks, this core is suitable for embedding into network devices and systems aimed at safeguarding data against potential interception or tampering. Catering to a broad range of IP-based communication systems, the IPSEC Core offers flexibility and reliability, making it a preferred choice for developers focusing on secure data exchange methods. The ease of integration allows for its deployment in both new and existing network architectures, underpinning secure transmissions across increasingly complex digital environments. Its wide acceptance and deployment in secure communications underscore the IPSEC Core's effectiveness in delivering critical security features, thus supporting enterprises in protecting sensitive data across diverse network topologies.
Ocean Logic's AES Encryption Core represents a robust and reliable solution for securing data across numerous platforms. Renowned for its certification and extensive validation in silicon on both FPGA and ASIC, this IP core has established credibility and trust among a diversified customer base. The AES core has seen nearly 60 successful implementations, underlining its reliability in providing robust data security. This encryption core complies with stringent security standards, ensuring data integrity and confidentiality. It is subject to Australia's Export Control regulations, qualifying it for international deployment across numerous key markets worldwide. Such widespread recognition indicates its versatility and adaptability to meet various encryption needs. For businesses and organizations prioritizing data security, Ocean Logic's AES Encryption Core offers a proven, high-performance solution. Its design facilitates seamless integration into existing systems, providing a comprehensive encryption capability while maintaining operational efficiency. The IP core stands as an ideal choice for companies looking to fortify their security measures with a trusted, efficient, and scalable encryption architecture.
The Security Protocol Accelerator by PQSecure is engineered to enhance the execution of various cryptographic protocols by offloading complex computation tasks from the main CPU, thereby accelerating the overall process. This specialized hardware component streamlines cryptographic operations such as encryption, decryption, and key exchanges, delivering faster and more reliable security processes. Designed to support a wide array of cryptographic protocols, including both symmetric and asymmetric types, the Security Protocol Accelerator is pivotal for organizations aiming to integrate high-speed security measures without compromising performance. It can be seamlessly integrated into existing network infrastructures, providing a scalable solution for enhancing secure communications in real-time applications. By implementing this accelerator, enterprises can expect significant improvements in handling secure transactions, reducing latency, and achieving lower power consumption compared to software-only implementations. This is particularly beneficial for environments with demanding processing requirements, such as data centers and cloud computing platforms, where efficient performance is crucial.
PQSecure offers cryptographic cores that serve as the backbone for secure data transmission and encryption processes. These cores are designed to perform a range of cryptographic functions, including symmetric and asymmetric encryption, which are critical for secure communications in a quantum-safe world. The design of these cores focuses on flexibility and efficiency, allowing them to be tailored to meet the specific needs of varied applications and environments. These cores are built to support multiple standards and cryptographic algorithms, accommodating both classical and post-quantum encryption methods. This adaptability ensures they can maintain security in the face of evolving computational threats. The Cryptographic Core is also optimized for integration into existing systems, providing seamless compatibility across a range of platforms from lightweight embedded devices to robust server environments. Additionally, the Cryptographic Core is crafted with hardware security measures to mitigate risks such as unauthorized access and data tampering. With its robust design and comprehensive feature set, the core is a vital component for any system requiring high assurance in security, especially in sectors where data integrity is paramount, including finance, government, and healthcare.
SINR is designed to effectively minimize background noise, ensuring that the main audio content is both clear and intelligible. It operates efficiently by focusing on reducing unwanted noise, thus improving the user's overall listening experience. This feature is especially vital in settings where clear communication is essential, and noise pollution needs to be significantly reduced.
PhantomBlu by Blu Wireless represents a cutting-edge advancement in tactical defense communications. This mmWave technology solution is expertly constructed to deliver stealthy, gigabit-level connectivity on the move, supporting high-speed tactical operations. PhantomBlu's low SWAP (Size, Weight, and Power) tactical solutions, configurable as PCP (hub) or STA (client), align with dynamic defense needs by providing dependable communications at range. The system capitalizes on spectrum availability and equipment flexibility, offering interoperability for both legacy systems and future assets without dependence on traditional networks. This capability makes PhantomBlu an invaluable tool for military forces requiring swift, secure, and adaptable communications to maintain operational efficacy in complex environments. The PhantomBlu system plays a pivotal role in transforming how modern military operations are conducted by seamlessly integrating with existing communications bases and enhancing mission-based applications. The flexibility of the configurable options supports high-performance execution, ensuring that military communication networks are responsive and robust in the face of evolving tactical demands.
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