The DP80C51 is an ultra-high performance, speed-optimized soft core of a single-chip 8-bit embedded controller, intended to operate with fast (typically on-chip) and slow (off-chip) memories. The core was designed with a special concern for the performance to power-consumption ratio. This ratio is extended by an advanced power management unit (PMU). The DP80C51 softcore is 100% binary and pins compatible with the industry standard 8051 8- bit microcontrollers. There are two configurations of the DP80C51: Harvard, where external data and program buses are separated, and von Neumann, with common program and external data bus. The DP80C51 has a Pipelined RISC architecture (up to 10 times faster compared to the standard architecture) and executes 85-200 million instructions per second. This performance can be also exploited to great advantage in low-power applications, where the core can be clocked over ten times slower than the original implementation, without performance depletion. The DP80C51 is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of SoC design flow. Each of DCD’s 8051 Cores has built-in support for the proprietary Hardware Debug System, called DoCD™. It is a real-time hardware debugger, which provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of running applications.
