All IPs > Security IP > Cryptography Cores
In today's interconnected world, the importance of secure communication and data protection cannot be overstated. Cryptography cores are a crucial subset of semiconductor IPs designed to provide foundational security solutions across a variety of electronic systems. At their core, these IPs implement complex algorithms that ensure the confidentiality, integrity, and authenticity of data being processed and exchanged.
The cryptography cores available in this category offer a diverse range of features tailored to different security needs. From symmetric-key algorithms like AES to asymmetric-key systems such as RSA and ECC, these cores ensure that systems can securely encrypt and decrypt information, protecting it from unauthorized access and tampering. By embedding these cryptographic functions directly into hardware, it becomes possible to achieve faster processing speeds and higher levels of security compared to software implementations.
These semiconductor IPs are widely used in applications where data security is paramount. This includes, but is not limited to, industries such as finance, telecommunications, and healthcare. Devices utilizing cryptography cores can range from secure payment systems, ensuring safe financial transactions, to mobile devices for secure communications, to medical devices that safeguard sensitive health information. Additionally, with the rise of the Internet of Things (IoT), cryptography cores are increasingly crucial in providing secure connections for a myriad of smart devices.
By integrating cryptography cores into your designs, you not only improve security but also future-proof your products against many potential vulnerabilities. As security threats continue to evolve, having robust cryptography solutions is essential for maintaining trust and reliability in your products and services. Whether you're developing a new application or enhancing an existing one, our category of cryptography cores offers the semiconductor IP solutions you need to meet today's stringent security demands.
Overview: Cybersecurity IPs offer a range of essential security features to protect your digital assets and sensitive information. From True Random Number Generators (TRNG) to advanced encryption algorithms like AES, DES, 3DES, and cryptographic hash functions like SHA, as well as RSA for secure key exchange and digital signatures, the IPs provide a comprehensive suite of tools to safeguard your data. Key Features: True Random Number Generator (TRNG): Generates unpredictable and unbiased random numbers for cryptographic applications. Advanced Encryption Standard (AES): Provides robust encryption with symmetric key algorithms for securing data. Data Encryption Standard (DES) and Triple DES (3DES): Implement legacy encryption algorithms for data protection. Hash Functions: Includes secure cryptographic hash functions like SHA (Secure Hash Algorithm) for data integrity verification. RSA: Enables secure key exchange, encryption, and digital signatures for secure communication. These cybersecurity IPs are designed to meet the stringent security requirements of modern applications, ensuring the confidentiality, integrity, and authenticity of your data.
The Akida IP is a revolutionary neural processor platform that brings real-time AI processing capabilities to the edge. Inspired by the brain's cognitive functions, Akida IP employs neuromorphic principles to deliver low-power AI solutions specifically crafted for applications like vision, audio, and sensor fusion. It features a scalable architecture composed of up to 128 neural nodes, each supporting an efficient allocation of MACs (multiply-accumulate operations) and configurable SRAM for enhanced processing capacity. This IP is designed to operate independently, integrating seamlessly with any existing microcontroller or application processor. The emphasis on event-based hardware acceleration allows it to minimize computational and communicational loads, significantly reducing the need for host CPU intervention. Additionally, Akida IP supports on-chip learning, including one-shot and few-shot learning capabilities, which limits the transmission of sensitive data, hence bolstering security and privacy measures. With a silicon-proven design that prioritizes cost-effectiveness and predictability, BrainChip’s Akida IP enables fully digital neuromorphic implementations. It leverages flexible configurations that can be adjusted post-silicon, ensuring adaptability in deployment. The support for multiple layers and varied bit weights and activations facilitates the development of sophisticated neural network models, accommodating complex AI solutions with increased scalability and configurability.
Polar ID is revolutionizing biometric security by using meta-optic technology to read the unique polarization signature of human faces. This innovative approach significantly improves security, effectively differentiating between real and fake faces primarily through its precise polarization detection capabilities. The system operates efficiently in all lighting conditions thanks to its near-infrared illumination at 940nm, making it versatile enough for both indoor and outdoor settings. It's designed to be compact, suitable even for smartphones with limited space, and significantly more cost-effective compared to conventional structured light solutions. Polar ID not only enhances security by preventing unauthorized access through spoofing with masks or photos, but it also elevates user convenience through its seamless integration into mobile devices. The absence of bulky notch requirements further underscores its design excellence. Its technological makeup stems from Metalenz's proprietary meta-optics, which allows it to fuse advanced functionality into a single compact system. Additionally, Polar ID eliminates the need for additional optical modules, integrating itself as a single image-based recognition and authentication solution. By adopting a complete system approach, Polar ID is set to redefine digital security across a vast array of consumer electronics, including smartphones and IoT devices. This meta-optic advancement is also projected to enhance future applications, likely extending into secure digital transactions and possibly medical diagnostics, broadening the horizons for secure biometric technology in personal and professional spheres.
aiWare represents a high-performance neural processing solution aimed at driving efficiency in AI-powered automotive applications. At its core, aiWare is designed to deliver robust inference capabilities necessary for complex neural network operations within the automotive domain. This IP features scalable performance fitting a broad spectrum of use-cases, from sensor-edge processors to high-performance centralized models, alongside substantial variances such as L2 to L4 automated driving applications. The aiWare NPU offers unrivaled efficiency and deterministic flexibility, having achieved ISO 26262 ASIL B certification, which accentuates its safety and reliability for automotive environments. It supports a multitude of advanced neural architectures, including CNNs and RNNs, empowering developers to effectively deploy AI models within constrained automotive ecosystems. AI pollution-free data pathways ensure high throughput with minimum energy consumption, aligning with automotive standards for efficiency and operational dependability. Accompanied by aiWare Studio SDK, aiWare simplifies the development process by offering an offline performance estimator that accurately predicts system performance. This tool, celebrated by OEMs globally, allows developers to refine neural networks with minimal hardware requirements, significantly abbreviating time-to-market while preserving high-performance standards. The aiWare's architecture focuses on enhancing efficiency, ensuring robust performance for applications spanning multi-modality sensing and complex data analytics.
Up to 1M KeyEnc/sec with improved power efficiency PQPerform-Lattice is a powerful hardware-based product designed for high throughput, high-performance, and high speed. It adds post-quantum cryptography for applications that typically handle a large number of transactions, such as high-capacity network hardware applications and secure key management HSMs. Optimizable for secure boot, as well as other use-cases, PQPerform-Lattice supports FIPS 204 ML-DSA for quantum-secure digital signature verification, as well as FIPS 203 ML-KEM for quantum key exchange. PQPerform-Lattice supports AXI4, PCIe, and is deployable in multiple instances, making it a powerful solution for existing systems and infrastructure requirements.
The SiFive Intelligence X280 delivers best-in-class vector processing capabilities powered by the RISC-V architecture, specifically targeting AI and ML applications. This core is designed to cater to advanced AI workloads, equipped with extensive compute capabilities that include wide vector processing units and scalable matrix computation. With its distinctive software-centric design, the X280 facilitates easy integration and offers adaptability to complex AI and ML processes. Its architecture is built to handle modern computational demands with high efficiency, thanks to its robust bandwidth and scalable execution units that accommodate evolving machine learning algorithms. Ideal for edge applications, the X280 supports sophisticated AI operations, resulting in fast and energy-efficient processing. The design flexibility ensures that the core can be optimized for a wide range of applications, promising unmatched performance scalability and intelligence in edge computing environments.
PUFrt is a fundamental security module that operates as a Hardware Root of Trust, providing a comprehensive suite of features such as PUF-based key generation, true random number generation (TRNG), and secure OTP storage. Designed to integrate seamlessly with a variety of systems, PUFrt shields against tampering and unauthorized access, thereby strengthening the security posture of semiconductor devices. Its compatibility stretches across lightweight security keys to advanced security coprocessors, marking it essential for safeguarding the integrity and authenticity of chips. The module incorporates a robust anti-tamper shell and features a built-in APB controller with secure/non-secure separation, allowing for flexible integration and custom security configurations. With an extensive 8k-bit OTP enhanced by instant hardware encryption, PUFrt supports secure boot processes, ensuring devices operate only with authenticated software. By addressing the core security needs at the hardware level, PUFrt plays a crucial role in mitigating the risks associated with IoT deployments and other connected devices. PUFrt's technical prowess is reflected in features like multi-chip key provisioning and entropy source integration, which are vital for cost-effective security deployments and cryptographic operations. The IP's design not only enhances security but also simplifies integration, making it a preferred choice for manufacturers seeking to bolster their defense mechanisms against hardware-based threats. Coupled with certifications like NIST CAMP and Riscure, PUFrt stands out as a premier choice for robust and reliable hardware security solutions.
Trilinear Technologies' HDCP Encryption-Decryption Engine is a sophisticated solution designed to safeguard digital content as it traverses various transmission channels. This engine is compliant with the HDCP standards 1.4 and 2.3, offering robust protection mechanisms to ensure that digital media investments are secure from unauthorized access and piracy. The engine’s hardware acceleration capabilities represent a crucial advantage, significantly reducing the load on the system processor while maintaining real-time encryption and decryption functions. This not only enhances performance but also extends the operational life of the hardware involved, making it suitable for high-demand media applications across sectors such as broadcast, entertainment, and corporate environments. Trilinear’s HDCP Encryption-Decryption Engine ensures compatibility with a wide array of consumer and professional-grade video equipment, providing seamless protection without interference in media quality or transmission speed. Its flexible integration options allow it to be smoothly incorporated into existing infrastructures, whether in standalone media devices or complex SoC architectures. Supported by comprehensive software resources, the HDCP Encryption-Decryption Engine provides an all-encompassing solution that includes necessary software stacks for managing device authentication and link maintenance. Its ability to safeguard high-definition content effectively makes it an invaluable asset for entities focused on secure content delivery and rights management.
The AES-XTS core is optimized for encryption of storage devices, providing advanced data protection by implementing the AES-XTS mode. XTS-AES is specifically designed for encrypting data storage, such as hard drives and SSDs, ensuring that sensitive information remains secure and inaccessible to unauthorized users. This core delivers high-speed encryption and decryption capabilities, making it ideal for disk encryption applications where performance is a critical factor. It adheres to the IEEE P1619 standard, which outlines the AES consistency in securing data at rest. By employing the AES-XTS core, storage devices can achieve comprehensive protection against data breaches, safeguarding important data across various storage media in personal computers, corporate databases, and portable external devices, ensuring data security and regulatory compliance.
Secure OTP by PUFsecurity offers the next generation in secure storage solutions within semiconductor devices. It builds on standard OTP technology by providing enhanced protection mechanisms for key and data storage. Combining physical macro components with digital RTL, Secure OTP offers comprehensive security for data at rest, in use, and during transit. This level of protection is imperative for today’s connected environments, where devices often face sophisticated hardware attacks. One critical aspect of Secure OTP is its ability to integrate seamlessly within a range of IC applications, supporting various interface controllers (I/F) for easy deployment. This integration ensures that sensitive data such as boot codes and cryptographic keys get the robust protection they need, preventing unauthorized access and possible exploitation. With an anti-tamper shell as part of its design, Secure OTP stands as a resilient guardian against attempts to extract or modify data illegitimately. As the security landscape evolves, Secure OTP acts as a pivotal element in transitioning from outdated e-fuse solutions to more impregnable storage systems. This IP essentially forms a crucial part of the defense-in-depth strategy, underpinning secure operations in IoT developments and beyond. Designed to withstand the increasingly rigorous demands of modern security standards, Secure OTP ensures that data integrity and confidentiality are preserved throughout the life cycle of electronic products.
The eSi-Crypto package provides a robust suite of cryptographic solutions tailored for ASIC and FPGA targets. It features a comprehensive range of encryption and authentication tools optimized for high throughput with minimal resource usage. A standout feature is its high-quality True Random Number Generator (TRNG), which adheres to NIST 800-22 standards, available as a hard macro in specified technologies. This suite also incorporates a variety of cryptographic algorithms including CRYSTALS Kyber and Dilithium, ECC/ECDSA, RSA, AES, and more for enhanced data security in applications like V2X communications. The eSi-Crypto suite is known for deploying sophisticated algorithms that ensure efficient and secure data processing. These include advanced features like support for algorithms such as ChaCha20 and Poly1305, recognized for their high-security margins and efficient computational profiles. The suite's architecture suits networking applications demanding robust encryption and quick processing due to its compatibility with various chip architectures. Leveraging modern cryptographic standards, eSi-Crypto plays a crucial role in defending against quantum computer threats. Its range of supported features signifies its versatility, catering to a wide spectrum of secure communications and transactions. EnSilica’s cryptographic IP is not only secure but also seamlessly integrates with multiple systems thanks to its customizable design framework and support for AMBA APB/AHB or AXI bus interfaces.
Securyzr iSSP is designed as a comprehensive security management platform, serving as the backbone for protecting embedded devices throughout their lifecycle. The integrated Security Services Platform facilitates a seamless deployment and management experience for users seeking robust security solutions. One of its main components is the Securyzr iSE neo, which functions as the root of trust within the device, offering secure boot processes and key isolation. The platform also incorporates a host software framework that ensures protected communication between the device's secure element, the host chip, and external servers. By integrating these layers, the Securyzr iSSP delivers an end-to-end security service, addressing critical needs such as firmware updates, security monitoring, and comprehensive device identity management. This secure communication backbone is pivotal in safeguarding all transactions across the network infrastructure. Leveraging its status as a PQC (Post-Quantum Cryptography) ready solution, the iSSP anticipates future security needs by integrating advanced cryptographic techniques. This commitment to evolving security practices ensures that users of Securyzr iSSP are equipped to combat both present and future vulnerabilities, keeping their systems ahead in the cybersecurity landscape.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
The 802.11 LDPC core by Wasiela is engineered for high throughput applications in wireless communication systems. It excels in providing frame-to-frame on-the-fly configuration, allowing developers to balance throughput and error correction performance according to specific needs. This LDPC solution is compliant with relevant throughput and performance specifications, ensuring reliable bit-error-rate and packet-error-rate outcomes that meet industry standards. The core's adaptability in decoding iterations is key to maintaining high efficiency without compromising on quality.
FIPS 140-3 CAVP-compliant, compact lattice-based hardware PQC engine PQPlatform-Lattice is a compact FIPS 140-3 CAVP-compliant, PQC engine that adds post-quantum support for hardware components and embedded devices, using lattice-based cryptographic algorithms such as ML-KEM (FIPS 203) for post-quantum key exchange, and ML-DSA (FIPS 204) – post-quantum digital signature verification. It provides secure acceleration of lattice-based PQC alongside support for traditional cryptography. Its use cases include strong user authentication, protecting hardware keys, and small-footprint, configurable side-channel protection. PQPlatform-Lattice is designed for minimal area as well as maximum compatibility and can be deployed with optional firmware-backed side-channel countermeasures. It is covered by multiple PQShield implementation patents.
The AES Core offers robust cryptographic solutions for secure communication in digital systems. This core implements the Advanced Encryption Standard (AES) algorithm, ensuring high levels of security for data transmission and storage. It is designed to be easily integrated into a variety of systems, providing advanced encryption capabilities while maintaining optimal performance levels.
Fully autonomous, FIPS 140-3 CAVP compliant PQC subsystem PQPlatform-SubSys is a cryptographic subsystem, designed to provide offloaded cryptographic services with minimal integration effort and full autonomy from an existing security subsystem, as well as configurable side-channel protection. These services include post-quantum signature generation, verification, and secure key establishment. It’s built with optimal performance in mind, as well as crypto agility with its provision of traditional, PQ/T hybrid and fully post-quantum algorithms. PQPlatform-SubSys uses its built-in RISC-V CPU independently from the surrounding system, allowing cryptographic services to be offloaded efficiently from the system processor.
The Cyclone V FPGA is equipped with a pre-integrated PQC processor, featuring a comprehensive suite of NIST-approved post-quantum cryptography algorithms. Designed for easy integration, it is tailored for proof-of-concept testing in various quantum-safe applications. This FPGA board, priced at $15,000, offers a viable solution for industries looking to trial and eventually implement quantum-resistant security measures.
Post-quantum Software Development Kit Provides easy-to-use software implementations of both post-quantum and classical cryptographic primitives. It’s designed with prototyping and experimentation in mind, consisting of an integration of PQShield’s PQCryptoLib library with two popular high-level cryptography libraries: OpenSSL and mbedTLS. OpenSSL: a widely-adopted secure-communication library mbedTLS: primarily intended for use in embedded system and IoT deployments
SEMIFIVE's AIoT Platform integrates artificial intelligence with the Internet of Things (IoT), offering a comprehensive solution for smart and connected devices. Tailored for edge computing applications, the platform combines the latest RISC-V cores with energy-efficient connectivity and processing capabilities, enabling innovations in smart home technologies, cybersecurity, and robotics. The platform is structured to deliver seamless connectivity and versatile functionality, including support for advanced peripherals such as USB 3.0 and MIPI interfaces, among others. Its infrastructure promotes rapid deployment in diverse IoT sectors, ensuring the fusion of intelligence into everyday objects effectively and conveniently. Designed to uphold the requirements of modern smart environments, the AIoT Platform encourages efficiency and simplicity in development, reducing the complexity and cost associated with custom IoT solutions. Whether utilized in industrial IoT or consumer electronics, this platform is essential for organizations aiming to harness the full potential of AI-enhanced IoT.
The SHA hashing core is designed to provide reliable and efficient data verification. It employs Secure Hash Algorithms (SHA) to generate distinct hash values from input data, ensuring data integrity and authentication. With its focus on high-speed operation and low resource usage, this core is ideal for environments requiring secure data handling. Supporting various SHA standards such as SHA-1, SHA-224, SHA-256, SHA-384, and SHA-512, this core caters to a wide range of cryptographic applications. It is instrumental in digital signatures, message authentication codes, and secure boot mechanisms. The implementation is optimized for both hardware and software applications, providing robust security measures essential for financial, governmental, and consumer electronics sectors needing secure data transactions and storage.
The Securyzr Key Management System is crafted to systematically handle cryptographic keys throughout their lifecycle within secure environments. Ensuring the security of keys involves rigorous management practices, from their generation and storage to distribution and eventual destruction. This management system employs robust protocols to maintain the confidentiality, integrity, and availability of cryptographic keys, vital for securing communications and data access. By automating key lifecycle events, the system reduces the risk of human error while ensuring strict adherence to security policies and standards. Offering a mixture of flexibility and high-level security assurance, the Securyzr Key Management System is ideal for integration into various organizational infrastructures, from enterprise applications to government operations, where secure key management is paramount.
Featuring G15, this IP is optimized for 2KB correction blocks, suitable for NAND devices with larger page sizes, such as 8KB. The design is aligned with methods seen in the G14X, but it extends its reach with longer codewords for comprehensive coverage of high-density NAND. The design supports a wide array of block sizes and configurational setups, making it highly adaptable to varying design needs. Additional error correction capabilities can be integrated based on client requirements, reinforcing its bespoke delivery.
The G13/G13X series is tailored for 512B correction blocks, particularly used in NAND setups with 2KB to 4KB page sizes. While both variants are crafted to manage the demands of SLC NAND transitions to finer geometries, the G13X allows for correction of a higher number of errors. Designed to fit seamlessly into existing controller architectures, it enables extensions of current hardware and software capabilities without extensive new investments. It offers area optimization through parameter adjustments and supports a range of channel configurations for broad applicability.
AndeSoft SW Stack encompasses a comprehensive set of software building blocks and middleware optimized for AndesCore processors. This rich collection includes operating systems, libraries, drivers, and middleware components, all meticulously designed to enhance software development speed and quality. By providing ready-to-use components, AndeSoft enables developers to focus on crafting their application-specific solutions, significantly reducing time-to-market. Its seamless integration with AndeSight IDE further enhances development efficiency, supporting diverse operating systems and being adaptable to various processor configurations for optimal performance.
The FPGA Pre-Trade Risk Check by Algo-Logic is designed for traders who demand real-time risk assessments before executing trades. By leveraging FPGA technology, this solution accelerates pre-trade checks by embedding them directly into hardware, reducing the typical delays encountered with software-based checks. This ensures that trades are both high-speed and secure, mitigating financial risks and protecting capital. Ideal for trading firms and exchanges, this solution upholds the integrity of high-frequency trading environments by performing rapid analysis and validation of trading orders.
The AES Encrypt/Decrypt IP provided by Secantec offers a highly secure solution for data encryption and decryption, supporting 128, 192, and 256-bit key lengths. Adhering to the Advanced Encryption Standard (AES), this IP ensures that data confidentiality is maintained across various platforms and applications. With its comprehensive encryption capability, this IP is pivotal in protecting sensitive data against unauthorized access, making it indispensable in secure communication systems, data storage solutions, and more. It provides a robust security framework that can be implemented efficiently within existing infrastructures. By leveraging the versatility of AES algorithms, the IP can be seamlessly integrated into a wide range of environments, from high-performance computing systems to portable devices requiring secure data channels. Its design ensures minimal latency and resource overhead, delivering a swift and reliable encryption mechanism.
The Individual IP Core Modules offer a suite of cryptographic solutions that adhere to the latest NIST PQC standards. Included algorithms like Dilithium, Kyber, and XMSS/SPHINCS+ provide robust security foundations. These modules are built for diverse use cases, delivering secure data processing and transmission while featuring AES encryption modes and secure random number generation. Perfect for developers seeking comprehensive, modular cryptographic elements for integration into larger systems.
The NS Class RISC-V CPU IP by Nuclei is ingeniously designed for applications emphasizing security and financial technologies, as well as IoT security. This IP offers a balanced blend of high-performance processing and specialized features aimed at safeguarding data integrity and promoting secure transaction environments. By leveraging a 32-bit architecture, the NS Class is particularly well-suited to applications requiring reliable secure processing capabilities. Equipped with state-of-the-art security extensions, the NS Class IP features trusted execution environments that are crucial for maintaining data security and integrity during operations. Developers can also exploit user-defined instruction extensions to customize security protocols according to specific applications, ensuring the highest level of data protection possible. The NS Class also accommodates a variety of RISC-V extensions, further enhancing the IP's adaptability to modern security-centric applications. With strong support in terms of an integrated toolchain and developmental infrastructure, Nuclei positions this IP as a solution that not only meets current IoT and fintech security requirements but is also adaptable for future developments in secure processing technologies.
FIPS 140-3 CAVP-compliant, compact PQC hardware acceleration for subsystems PQPlatform-CoPro combines hash-based and lattice-based post-quantum cryptography that can be added to an existing security subsystem. It can be optimized for minimum area, maintaining high-performance, and is designed to be run by an existing CPU using PQShield-supplied firmware, meaning it involves low integration effort and flexible configurations to support a wide variety of use cases, including quantum-safe secure boot. Solutions are available for hardware acceleration of SHA-3, SHAKE, ML-KEM, ML-DSA, alongside traditional cryptography. In addition, PQPlatform-CoPro can be configured with side-channel protection. PQPlatform-CoPro is covered by multiple PQShield implementation patents.
NVM Defender is a pioneering hardware module designed to safeguard integrated circuits (ICs) from common invasive attacks such as non-volatile memory (NVM) code extraction. This innovative solution emphasizes security by design, creating a self-aware environment that detects potential breaches automatically. The inherent structure of NVM Defender makes bypassing any security measures impractical, ensuring comprehensive protection against emulation, cloning, and counterfeiting attempts. Suitable for chipmakers seeking robust security solutions, NVM Defender effectively protects embedded software, cryptographic keys, and personal data, integrating seamlessly into any chip architecture to offer a cost-effective countermeasure against unauthorized data access.
The AES-GCM core is developed for authenticated encryption, delivering enhanced data protection through a combination of encryption and integrity assurance. AES-GCM (Galois/Counter Mode) is a mode of operation for AES that offers authenticated encryption, which is crucial for secure communications requiring both confidentiality and authenticity. This core is designed for high-performance environments, ensuring minimal latency while maximizing throughput. It is suitable for a variety of applications including secure network communications, storage encryption, and high-speed data transfer systems. With its integrated authentication mechanisms, the AES-GCM core protects data against unauthorized modifications and ensures secure, tamper-proof communication channels, making it indispensable for industries like financial services, telecommunications, and cloud computing where data integrity and confidentiality are paramount.
PUFcc is a versatile Crypto Coprocessor built on PUFsecurity's Hardware Root of Trust technology. It merges key generation, storage, and a comprehensive suite of cryptographic algorithms into a single, easily deployable IP block. This integration simplifies the development of secure systems, providing features like Secure Boot, TLS, OTA, and robust key management. The IP supports a range of cryptographic functions certified under NIST CAVP and OSCCA, tailored for flexible security applications across IoT devices and beyond. It is engineered to achieve seamless integration with SoC designs, using standard interfaces such as AXI and APB for efficient memory access. The PUFcc also promotes extended security boundaries that include external flash components, enhancing the protection spectrum across entire systems. With its feature-packed architecture, PUFcc proves critical in tackling the security demands of interconnected devices. By embedding hardware-level defense mechanisms, PUFcc positions itself as a cornerstone for developing resilient devices in an era characterized by sophisticated cyber threats. Its built-in protections against cloning and other forms of unauthorized exploitation make it indispensable in fortifying the security of next-generation electronic products.
The AES standard modes core is designed for secure encryption applications, adhering to the Advanced Encryption Standard (AES). It offers reliable and efficient encryption capabilities essential for safeguarding sensitive data across various platforms. Developed with a robust architecture, this core ensures optimal performance in both resource-constrained and high-throughput environments. The core supports multiple AES modes including ECB, CBC, CFB, OFB, and CTR, making it versatile for different encryption needs. It provides high security and flexibility, essential for applications such as telecommunications, storage, and secure communication networks. By incorporating this core into their systems, users can meet stringent security standards while enjoying ease of integration and minimal resource consumption.
The MACSEC Core provides an essential building block for implementing Ethernet data security, supporting protocols crucial for protecting data at the MAC layer in network infrastructure. It ensures confidentiality and integrity of the communications, making it invaluable for environments where data transmission security is paramount. A vital tool for network security, the MACSEC Core integrates seamlessly into various network processors, offering robust security for both small-scale and extensive network architectures. It stands out for its efficiency in encrypting and authenticating Ethernet packets, ensuring data remains protected from eavesdropping and unauthorized access. Designed for versatile network applications, the MACSEC Core can easily adapt to existing network configurations, enabling quick deployment and teeming with existing systems, thereby enhancing overall network security without extensive reconfigurations.
Post-Quantum Cryptography IP represents a forward-looking approach to cryptographic security, designed to protect against the potential threats posed by quantum computing. This IP incorporates novel algorithms developed to withstand the unique challenges introduced by quantum computational capabilities. This suite of cryptographic solutions is engineered to be resilient against the theoretical potential of quantum computers breaking conventional cryptographic systems. Incorporating these technologies into existing systems ensures that sensitive data is secured even as computation power and methodologies evolve. The Post-Quantum Cryptography IP is indispensable for users seeking future-proof security architectures, providing an assurance that their cryptographic functions will remain secure against the quantum threats of tomorrow.
The QUIC Protocol Core is engineered to offer secure and efficient communication by supporting the Quick UDP Internet Connections (QUIC) protocol optimized with TLS 1.3 security. This core provides full hardware encryption and decryption along with efficient packet handling that offloads CPU tasks. It's specially designed for applications demanding high-speed, secure connections such as data centers and cloud computing.
NeoPUF technology harnesses the unpredictability and uniqueness of physical variations formed during chip manufacturing to create a highly secure root of trust. This technology is crucial in providing secure keys and authentication for applications needing strong security frameworks, such as IoT and mobile communications. NeoPUF's ability to generate cryptographic keys without storing them aims to protect data from unauthorized access and cloning, making it highly valuable for devices requiring elevated security standards.
Alma Technologies' Ultra-High Throughput 8/10/12-bit JPEG Encoder is crafted for top-tier compression performance, designed to manage high-resolution images with remarkable speed. This encoder supports both 8-bit standard-compliant and extended 10/12-bit lossless and lossy compression, making it versatile enough to handle a multitude of professional imaging needs across different sectors like broadcasting, medical imaging, and space exploration. The architecture of this encoder emphasizes parallel processing capabilities, allowing it to maintain high throughput rates even with the most demanding image resolutions. By employing a scalable engine framework, it delivers unprecedented compression speeds while preserving exceptional image quality, thereby providing visually lossless outputs that maintain the original image integrity across various compression settings. Integration into both FPGA and ASIC systems is seamless, thanks to its system-independent design, which supports flexible interfacing and low-resource utilization. The encoder is optimized to accommodate adjustable data flows and manage real-time processing requirements without sacrificing efficiency. This makes it an invaluable resource for applications needing rapid data processing and transmission without compromising quality,"category_ids":[283], "supported_process_nodes":[], "tech_specs":[],"features":[],"applications":[],"part_number":null,"power_watts":null,"supply_voltage_volts":null}],"company_country_iso_code":null,"services":["soft-ip","custom-ip"],"outsourcing_services":[]} This versatile JPEG IP core by Alma Technologies is designed to facilitate high-speed compression of images, supporting 8-bit baseline and 10/12-bit extended modes. Catering specifically to both standard and advanced image compression needs, these cores effectively handle diverse data formats including grayscale and full color with various chroma subsampling options like 4:4:4, 4:2:2, and 4:2:0. The IP cores deliver exceptional performance through lossless or configurable lossy compression, making them adaptable to different application requirements, whether they are for high-quality imaging or storage-efficient compression solutions. Despite the complex demands of high-speed image processing, these JPEG cores maintain a streamlined operation with an intuitive interface that supports user control over the compression process without requiring significant computing resources. Additionally, their robust rate control mechanisms ensure consistency across frames, providing reliable quality maintenance even at different compression levels. Moreover, the IP core's flexible architecture allows for seamless integration into existing systems, with well-balanced power and space consumption. This makes them ideally suited for implementation in both FPGA and ASIC platforms, guaranteeing impressive reliability and outstanding image fidelity, supporting a wide range of mixed-media applications across industries. Please include this elsewhere. The AES Block Cipher IP has already been modernized. Also, it seems like only the JPEG encoder has been featured. I could review the rest of the website. vulnerabilities across the H.264 suite. Perhaps the JPEG LS Encoder and its parts. Alma Technologies' AES Block Cipher IP is designed to provide high-performance encryption and decryption capabilities essential for secure data transmission. This IP core supports a wide range of cipher modes, including ECB, CBC, CFB, OFB, CTR, and GCM, accommodating various encryption standards while maintaining flexibility and efficiency. Its robust architecture ensures effective performance, enabling the integration of secure communication protocols into hardware devices without compromising speed or security. 11 These AES cores are crafted to offer top-notch encryption ability, emphasizing compact design suitable for both FPGA and ASIC implementations. The modular framework of the AES IP allows for easy updates and adaptations to meet changing security landscapes without extensive system overhauls. The integration of these cores guarantees adherence to stringent data security requirements, making them ideal for use in sensitive applications such as secure communications, financial transactions, and personal data protection. Ease of use is a significant feature of this IP, supported by a straightforward interface that simplifies its implementation into existing systems. Its design considers low power consumption while ensuring high throughput rates, offering an optimal balance of energy-efficiency and encryption performance. This makes it a suitable addition for any security-centric applications demanding superior confidentiality mechanisms in data handling processes.9 Alma Technologies' Ultra-High Throughput 8/10/12-bit JPEG Encoder is crafted for top-tier compression performance, designed to manage high-resolution images with remarkable speed. This encoder supports both 8-bit standard-compliant and extended 10/12-bit lossless and lossy compression, making it versatile enough to handle a multitude of professional imaging needs across different sectors like broadcasting, medical imaging, and space exploration. The architecture of this encoder emphasizes parallel processing capabilities, allowing it to maintain high throughput rates even with the most demanding image resolutions. By employing a scalable engine framework, it delivers unprecedented compression speeds while preserving exceptional image quality, thereby providing visually lossless outputs that maintain the original image integrity across various compression settings. Integration into both FPGA and ASIC systems is seamless, thanks to its system-independent design, which supports flexible interfacing and low-resource utilization. The encoder is optimized to accommodate adjustable data flows and manage real-time processing requirements without sacrificing efficiency. This makes it an invaluable resource for applications needing rapid data processing and transmission without compromising quality. 8 Easy setup with appropriate provisions was placed. Other relevant IP, such as the AES Block Cipher IP, for wider applicability should be added. Do ensure that the data is clean and structured. Please return the other parts. PIECE GLOSSESSphinx Publishing ":[5270] The AES Block Cipher IP is modernized in strategies. According to their desired configurations, adapting a non-portable blocking access and utilizing modern processing techniques. Alma Technologies' AES Block Cipher IP offers high-performance encryption and decryption capabilities essential for secure data transmission. This IP core supports multiple cipher modes including ECB, CBC, CFB, OFB, CTR, and GCM, enabling compatibility with various secure applications while maintaining flexibility and efficiency. Its comprehensive architecture ensures strong performance, facilitating the integration of secure communication protocols into devices without compromising speed or security. The AES cores emphasize a compact design suitable for both FPGA and ASIC implementations, offering superior encryption capabilities with customizable settings. The IP accommodates various updates and security adaptations without requiring significant system overhauls, adhering to strict data encryption standards. Designed with ease of use in mind, these cores feature straightforward interfaces for seamless integration. High throughput rates are maintained alongside low power consumption, making them an optimal choice for applications requiring robust data protection like secure communications and financial transactions.8clusion.9ging. Easy_trans!setup with appropriate provisions was pla...
The AES Core by Algotronix is a sophisticated solution tailored for securing data using advanced encryption methods. This core supports various encryption modes such as ECB, CBC, CTR, CFB, OFB, CCM, GCM, and XTS, which cater to a wide array of applications requiring different levels and methods of data protection. The flexibility in supported modes allows for tailored implementations in different security-critical environments. This encryption core is known for its deployment among prominent defense electronics organizations, and it has been operational within several NATO member states, testifying to its high-level security assurance and operational readiness in sensitive global contexts. Offered typically in source code form, the AES Core ensures that users can perform thorough security audits and tailor enhancements specific to their security policies and infrastructural needs. This capability positions Algotronix's offering as an optimal choice for organizations prioritizing stringent security postures.
FIPS 140-3 CAVP compliant ultra-fast, compact, and power efficient secure hash acceleration PQPlatform-Hash is a power side-channel accelerator, supporting a wide range of Hash-Based Signature Schemes (HBSS). PQPlatform-Hash deploys tried-and-tested HBSS including quantum-safe LMS and XMSS (not hybrid). It provides acceleration of HBSS in embedded devices, especially where high throughput is required, or resource constraints necessitate minimal additional area. For example, PQPlatform-Hash is a solution for secure first-stage boot loading with hash-based signature schemes. HBSS offer different trade-offs of memory/area to lattice-based schemes, and as a result, PQPlatform-Hash is ideally suited for smaller key sizes, larger signature sizes, and processing times for key generation, signature generation and verification.
The IPSEC Core by Algotronix is designed to secure IP communications by providing robust encryption and authentication mechanisms. Essential for ensuring data confidentiality and integrity over IP networks, this core is suitable for embedding into network devices and systems aimed at safeguarding data against potential interception or tampering. Catering to a broad range of IP-based communication systems, the IPSEC Core offers flexibility and reliability, making it a preferred choice for developers focusing on secure data exchange methods. The ease of integration allows for its deployment in both new and existing network architectures, underpinning secure transmissions across increasingly complex digital environments. Its wide acceptance and deployment in secure communications underscore the IPSEC Core's effectiveness in delivering critical security features, thus supporting enterprises in protecting sensitive data across diverse network topologies.
The Customizable Cryptography Accelerator is designed to adapt to specific client needs, offering a broad spectrum of configurability. It integrates seamlessly with all NIST PQC standards, including Dilithium and Kyber, while allowing the extension of additional algorithms, even custom ones. This accelerator ensures robust processing with adjustable performance and size, delivering resilience against differential power analysis (DPA), timing, and side-channel attacks. Compatible with AXI4, the solution emphasizes versatility and security, making it an ideal choice for organizations seeking tailored cryptographic solutions.
Ocean Logic's AES Encryption Core represents a robust and reliable solution for securing data across numerous platforms. Renowned for its certification and extensive validation in silicon on both FPGA and ASIC, this IP core has established credibility and trust among a diversified customer base. The AES core has seen nearly 60 successful implementations, underlining its reliability in providing robust data security. This encryption core complies with stringent security standards, ensuring data integrity and confidentiality. It is subject to Australia's Export Control regulations, qualifying it for international deployment across numerous key markets worldwide. Such widespread recognition indicates its versatility and adaptability to meet various encryption needs. For businesses and organizations prioritizing data security, Ocean Logic's AES Encryption Core offers a proven, high-performance solution. Its design facilitates seamless integration into existing systems, providing a comprehensive encryption capability while maintaining operational efficiency. The IP core stands as an ideal choice for companies looking to fortify their security measures with a trusted, efficient, and scalable encryption architecture.
FortiPKA-RISC-V is a robust Public Key Algorithm coprocessor crafted to enhance security through its modular multiplication capabilities. Protected against side-channel and fault injection attacks, this coprocessor eliminates the common bottlenecks seen in modular arithmetic computations, such as Montgomery domain transformations. The design is highly efficient, streamlining key cryptographic operations to bolster performance while minimizing the silicon area. This results in a finely tuned balance of speed and security, making it an excellent choice for applications where both efficiency and protection are crucial. FortiPKA-RISC-V's reliability has been proven through rigorous testing, offering a formidable solution for secure environments. It is particularly beneficial for devices that need to manage complex cryptographic tasks securely, from financial systems to secure communications protocols, highlighting its role in maintaining data integrity on a global scale.
The FPGA Lock Core is an innovative FPGA solution designed to secure FPGAs and hardware against unauthorized access and counterfeiting, leveraging a Microchip ATSHA204A crypto authentication IC. It reads a unique ID, generates a 256-bit challenge, and uses secure hashing to verify the hardware's authenticity, ensuring hardware integrity in sensitive applications like military and medical fields. This solution allows hardware protection against IP theft by enforcing authentication and disables FPGA functionality if unauthorized access is detected. The core utilizes minimal logic resources and one FPGA pin, communicating through a bidirectional open drain link. The clarity of this system is enhanced by providing the core in VHDL, allowing users to thoroughly understand its functionality, supported by example designs on Cyclone10 and Artix 7 boards, catering to both Intel and Xilinx FPGA platforms. Complementing this security measure is the Key Writer Core, which allows programming of custom secret keys into the ATSHA204A in situ on assembled boards, ensuring a seamless integration with the FPGA Lock system. Available for various FPGA platforms, the Efinix version, distributed with TRS Star, expands its applicability, with webinars and user guides offering in-depth implementation insights.
The NI Class RISC-V CPU IP from Nuclei serves high-intensity applications across AI, ADAS, communication, and video processing domains. This sophisticated IP harnesses a powerful architecture to support complex computational demands, ensuring efficient processing and data management in demanding environments. Its robust design facilitates the integration of advanced AI technologies and high-definition video processing, catering to both automotive and communication industries. Operating within a 64-bit framework, the NI Class IP provides extensive support for custom instruction sets, allowing developers to expand functionality to meet application-specific requirements. This adaptability is bolstered by the inclusion of a variety of RISC-V extensions, ensuring that the IP remains at the forefront of advancing technology needs. Security considerations are paramount in the design of the NI Class IP, with integrated trusted execution environments and comprehensive physical security packages to safeguard data integrity across various platforms. By offering an extensive toolkit and a supportive ecosystem, Nuclei empowers developers to maximize the potential of their communication and video processing solutions, ensuring readiness for future technological advancements.
This product enhances the standard AES Core by incorporating fault-resistant features, making it resilient to potential threats and system errors. It ensures the continuous secure operation of the encryption process even in the presence of hardware faults or soft errors. This core is ideal for applications where data integrity and security cannot be compromised, such as defense and financial systems.
The QDID PUF provides a unique identity based directly on quantum effects observed in standard CMOS processes. These identities are inherently secure due to the randomness that originates from variations in device oxide thickness and defect distribution. By leveraging such inherent unpredictability, QDID PUFs form a robust basis for hardware root-of-trust. This IP simplifies secure provisioning by avoiding traditional factory-based key injections, thereby reducing reliance on external secure manufacturing processes. QDID PUFs also ensure that identities are not stored in memory, instead being generated dynamically. This characteristic defends against side-channel attacks exploiting memory vulnerabilities. Additionally, the high entropy of the quantum effects they harness offers robust resistance to machine learning-based entropy source attacks, generating customizable security seeds up to 256 bits. Boosting its security, the QDID PUF integrates strategic countermeasures against side-channel attacks and has been certified to comply with stringent standards like PSA Level 2 and CC EAL4+. It supports wide-ranging environmental conditions and boasts extensive process node compatibility with major fabrication technologies. Typically used for key generation and device authentication, it represents the vanguard of cryptographic consistency for post-quantum applications.
The AES Crypto core by Dillon Engineering offers robust encryption and decryption capabilities consistent with the Federal Information Processing Standard (FIPS) 197. Developed using the ParaCore Architect™ utility, this IP core can be precisely tailored to meet diverse throughput, size, and performance needs, making it an ideal solution for modern cybersecurity applications. With data throughput capabilities up to 12.8 Gb/s, this core supports several encryption modes, including ECB, CBC, CFB, OFB, and CTR. Its high adaptability allows dynamic key changes without incursions in throughput, making it flexible for various encryption tasks. The core is fully compliant with NIST standards and can function in both standalone and integrated encryption/decryption modes. This AES Crypto core, available in generic HDL or targeted EDIF formats, is easily integrable into different design architectures, whether for FPGA or ASIC environments. It is suited for applications demanding robust security measures, providing dependable encryption performance across a plethora of processing needs.
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