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All IPs > Interface Controller & PHY > Other > eDP 1.5a RX PHY Samsung 14nm

eDP 1.5a RX PHY Samsung 14nm

From Qualitas Semiconductor

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Description

The Qualitas eDP RX PHY IP supports the eDP RX v1.5a standard.
This core IP commonly used for connecting a timing controller (TCON) to a host processor.

Deliverables
Hard IP
  • Verilog
  • GDS
  • LEF/DEF
  • Extracted netlist
  • Datasheet
  • Integration guide
  • Test bench
  • FE-Common: MODEL, TWRAP, TB, LEF. LIBERTY, IPXACT, ATPG, SIPI BE-Common: CIR, GDS, DRC, LVS, DFM DOC-Common: DataSheet, UserGuide, TestGuide, Register_setting, SupplementGuide
Verification IP
Features
  • Compliant to DisplayPort v1.4, eDP v1.4, and eDP v1.5a
  • Supports data rates from Reduced Bit Rate (RBR:1.62 Gbps) to High Bit Rate 3 (HBR3: 8.1Gbps), and user configurable custom B/Ws
  • Supports for eDP v1.4b features, such as PSR1 and PSR2
  • Supports eDP v1.5a features, including AUX-less link training (Low Frequency Peridoc Signaling)
  • Adaptive Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
  • Automatic calibration of analog circuits and parametric offset cancellation
  • Supports Built in Eye Open Monitor feature
  • Built In Self Test (BIST), including DP Standard Training Pattern Sets (TPS1~TPS4), pseudo random bit stram generation and checkers
  • Includes PCS layer for easier link interfaces (symbol aligning, 8b10b decoder, de-scrambler, and support for fail-safe auto recovery feature)
  • AUX RX controller includes sync detection and fully synthesizable digital CDR
  • Operating parameters can be fully configured by APB v3.0 and SPI interfaces
Foundries & Process Nodes
Foundry Process Nodes
Samsung 14nm
Tech Specs
Class Value
Categories Interface Controller & PHY > Other
Availability All Countries & Regions
Image Gallery
eDP 1.5a RX PHY Samsung 14nm
Applications
  • TCON
  • DDI
  • Mobile
  • IoT
  • Automotive
  • Chip-to-chip interconnect
  • etc.
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