All IPs > Wireline Communication > Ethernet
The wireline communication category of Ethernet semiconductor IPs is pivotal in the development of modern high-speed data transfer technologies. Ethernet technology, a mainstay in networking, facilitates the connection of computers to local networks (LANs) and wide-area networks (WANs). This category focuses on semiconductor IPs that implement Ethernet protocols, enabling manufacturers to integrate high-performance networking capabilities into their electronic devices efficiently and cost-effectively.
Ethernet semiconductor IPs are crucial for designing networking chips used in a variety of enterprise, consumer, and industrial applications. These IPs provide the foundational building blocks for implementing Ethernet standards from legacy 10/100 Mbps to the latest Multi-Gigabit Ethernet, including 1G, 10G, 25G, and beyond. Enhanced with features like Energy Efficient Ethernet (EEE) and advanced security mechanisms, these semiconductor IPs ensure optimized performance and reliability essential for today’s data-intensive applications.
The products in this category include a diverse range of Ethernet MAC(medium access control) cores, PHY(physical layer) cores, and network interface controllers, among others. These components work together to manage data packet transmission over Ethernet networks, ensuring seamless communication between connected devices. Designers leverage these Ethernet IPs to create routers, switches, servers, and Internet of Things (IoT) devices that require sophisticated data handling capabilities.
By integrating Ethernet semiconductor IPs, developers and OEMs can achieve faster time-to-market while reducing design risk and cost. These IPs are pre-verified, ensuring compliance with the current Ethernet standards, which accelerates the development cycle for networking equipment. Consequently, Ethernet semiconductor IPs are indispensable for any entity aiming to innovate within the competitive landscape of wireline communication technologies.
Axelera AI's Metis AIPU PCIe AI Accelerator Card is designed to tackle demanding vision applications with its powerful processing capabilities. The card embeds a single Metis AIPU which can deliver up to 214 TOPS, providing the necessary throughput for concurrent processing of high-definition video streams and complex AI inference tasks. This PCIe card is supported by the Voyager SDK, which enhances the user experience by allowing easy integration into existing systems for efficient deployment of AI inference networks. It suits developers and integrators looking for an upgrade to existing infrastructure without extensive modifications, optimizing performance and accelerating AI model deployment. The card’s design prioritizes performance and efficiency, making it suitable for diverse applications across industries like security, transportation, and smart city environments. Its capacity to deliver high frames per second on popular AI models ensures it meets modern digital processing demands with reliability and precision.
Panmnesia's CXL 3.1 Switch is an integral component designed to facilitate high-speed, low-latency data transfers across multiple connected devices. It is architected to manage resource allocation seamlessly in AI and high-performance computing environments, supporting broad bandwidth, robust data throughput, and efficient power consumption, creating a cohesive foundation for scalable AI infrastructures. Its integration with advanced protocols ensures high system compatibility.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
Intilop's 10G TCP Offload Engine (TOE) offers an advanced solution integrating MAC, PCIe, and Host Interface to deliver ultra-low latency network performance. This solution is crafted for environments requiring high-speed data transmission and minimal delays, ensuring a robust system for demanding networking tasks. With its capability for full TCP stack implementation, the TOE handles up to 16,000 concurrent sessions, operating with remarkably low latency and without the need for additional CPU processing.\n\nThe engine's design incorporates key features like zero jitter, dual 10G ports, and extensive offloading capabilities including checksum offload and large send offload. It supports multiple DMA engines, ensuring high throughput across varied network conditions. The architecture is highly adaptable, offering both hardware and software customization options to suit specific customer requirements, leveraging Intilop's expertise in FPGA and SoC design.\n\nThis IP is deployed globally, supporting configurations in cloud computing, data centers, and high-performance computing environments. Its ability to offload significant networking tasks from the CPU allows enterprises to maximize application performance while minimizing power consumption and system costs, delivering a comprehensive network acceleration solution. The product is part of Intilop's extensive portfolio, designed to enhance network throughput and efficiency while significantly reducing processing overhead.
Time-Triggered Ethernet is a cutting-edge networking technology designed to bring real-time capabilities to Ethernet networks. It enhances standard Ethernet by incorporating time-triggered mechanisms, which support synchronized data transmission across network nodes. This is important in industries such as aerospace and automotive, where precise timing and reliable data transmission are essential for safe operations.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The CT25205 digital core serves as a comprehensive solution for implementing the IEEE 802.3cg® 10BASE-T1S Ethernet Physical Layer. Crafted in Verilog 2005 HDL, this synthesizable core adapts elegantly to standard cells and FPGA environments. It incorporates critical components like the PMA, PCS, and PLCA Reconciliation Sublayer, working seamlessly with any Ethernet MAC conforming to the IEEE CSMA/CD standards using the MII interface. A unique feature of CT25205 is its integrated PLCA RS, which enables existing MAC devices to access PLCA functionalities without further hardware modifications. This digital core also features connectivity with a standard OPEN Alliance 10BASE-T1S PMD interface, making it pivotal in enhancing communication for Zonal Gateway SoCs and MCUs that demand advanced 10BASE-T1S capabilities.
KPIT's Integrated Diagnostics and Aftersales Transformation (iDART) program is designed to enhance vehicle diagnostics and streamline aftersales services. By employing advanced diagnostic tools and solutions, iDART aids in early detection and resolution of vehicle issues, reducing downtime and improving overall vehicle reliability. The program leverages cutting-edge software and data analytics to monitor vehicle health in real-time, allowing service providers to anticipate and address potential problems proactively. This comprehensive approach ensures that vehicles maintain peak performance and extends their operational lifespan. iDART also focuses on transforming aftersales processes by integrating digital platforms, which facilitate better communication between manufacturers, service providers, and customers. This integration leads to more efficient service delivery, improved customer satisfaction, and optimized resource utilization. By harnessing the power of data and diagnostics, KPIT's iDART program provides invaluable insights into each vehicle's condition, facilitating timely maintenance and reducing service-related costs. This innovative solution supports KPIT's commitment to delivering end-to-end digital transformation within the automotive sector.
The pPLL03F-GF22FDX is part of the DeepSub family of all digital PLLs specifically designed for performance computing applications. Known for its low jitter and compact area, it is optimal for clocking applications with stringent timing requirements at frequencies reaching 4GHz. This makes it particularly suitable for use in performance computing blocks and ADCs/DACs that require moderate SNR levels, offering stable and reliable clocking solutions across multiple domains. With benefits like fractional multiplication and small die size, the pPLL03F excels in systems that need integration of multiple PLLs per SoC. Its design caters to complex SoCs with multiple clock domains and low-jitter applications, enhancing the overall system performance without compromising on power efficiency. Currently available in multiple process technologies such as GlobalFoundries 22FDX, Samsung 8LPP and 14LPP, and TSMC N6/N7, the pPLL03F is highly adaptable and can be ported to other technologies as needed. Its strategic design attributes ensure that it addresses the dual challenges of high performance and energy efficiency in today's fast-paced semiconductor industry.
KPIT's Connected Vehicle Solutions redefine vehicular connectivity by focusing on robust software platforms and tools that enable seamless communication between vehicles and their environments. These solutions are designed to enhance the driving experience by providing real-time data exchange, ensuring vehicles stay informed and adaptive to changing conditions. The solutions encompass production-ready platforms that integrate advanced telematics, infotainment systems, and onboard diagnostics, making vehicles increasingly intelligent and user-friendly. By enabling real-time traffic updates, navigation assistance, and remote vehicle monitoring, these solutions offer a more connected, efficient, and safer driving experience. This technology empowers both drivers and manufacturers by providing critical insights through data analytics, ultimately leading to smarter vehicle operations. Furthermore, KPIT's solutions facilitate vehicle-to-everything (V2X) communication, which plays a crucial role in developing smart city infrastructure. This connectivity allows vehicles to interact with their surroundings, enhancing safety, reducing congestion, and promoting the efficient use of resources. The implementation of these systems is a testament to KPIT's commitment to advancing automotive technologies. KPIT continues to lead the evolution of connected vehicles by supporting automakers with the tools and expertise necessary to transform traditional vehicles into modern, interconnected entities. This positions KPIT as a trailblazer in crafting the future of automotive communication and integration.
The ePHY-5616 delivers data rates from 1 to 56Gbps across technology nodes of 16nm and 12nm. Designed for a diverse range of applications, this product offers superior BER and low latency, making it ideal for enterprise equipment like routers, switches, and network interface cards. The ePHY-5616 employs a highly configurable DSP-based receiver architecture designed to manage various insertion loss scenarios, from 10dB up to over 35dB. This ensures robust and reliable data transfer across multiple setups.
The 10G TCP Offload Engine (TOE) by Intilop is engineered to offer efficient TCP processing with minimized CPU involvement, thereby enhancing overall system performance. This solution is a perfect fit for networks requiring low-latency interfaces with high data throughput, supplemented by a complete implementation of TCP protocols. Its architecture supports multiple concurrent TCP sessions, ensuring consistent latency across extensive network loads.\n\nThis TOE leverages advanced offload features such as large send and checksum offload, facilitating rapid data throughput while reducing processor workload. Ideal for integration into systems where speed and efficiency are paramount, the TOE effectively alleviates data transfer burdens from host CPUs, thereby optimizing resource allocation and system functionality.\n\nThe TOE is tailored for diverse applications including broadband networking, enterprise data centers, and high-performance computing setups. Offering reliable performance with broad compatibility, the TOE provides a practical solution for modern network environments requiring scalable, robust network acceleration technologies.
The HOTLink II Product Suite from Great River Technology exemplifies a high-performance video and data communication solution, tailored to meet the demanding requirements of aerospace applications. This suite is designed to facilitate the seamless transfer of high-speed data using the HOTLink II protocol, supporting the implementation of systems that require synchronization and reliability. With its focus on bridging video interfaces efficiently, Great River Technology provides a formidable toolset for avionics engineers looking to streamline their data communication systems. Leveraging the HOTLink II suite, users can expect a credible solution that offers both adaptability and robust performance, capable of integrating into a multitude of platforms. Great River Technology's commitment to technical excellence delivers a product suite that not only caters to current industry needs but is also adaptable for future advancements within the domain of video data exchange systems. By combining the tools and expertise offered in this suite, clients can develop, test, and implement HOTLink II systems that enhance communication capabilities within their network infrastructure. The suite is backed by comprehensive support to ensure optimal performance in all stages of product deployment, making it a vital component in achieving strategic communication objectives in aerospace technology.
The High PHY Accelerators from AccelerComm are a collection of signal processing cores designed for ASIC, FPGA, and SoC applications, primarily focused on boosting 5G NR communications. These accelerators incorporate proprietary algorithms that allow users to attain the highest levels of throughput, efficiency, and power savings. These accelerator cores are engineered to facilitate seamless integration into existing systems, significantly improving spectral efficiency through advanced processing techniques. The use of patented algorithms allows for overcoming system noise and interference, delivering superior performance for complex wireless communication networks. Moreover, these accelerators excel at minimizing latency and resource consumption, providing an optimal balance between high performance and low power requirements. Recognized for their flexibility, these accelerators support scalable architectures, customizable for various deployment scenarios. This versatility ensures operators and developers can adapt solutions to fit small, cost-sensitive applications or larger enterprise demands, enhancing the ability to handle high data volumes with integrity and reliability.
The Ultra-Low Latency 10G Ethernet MAC from Chevin Technology is engineered to provide exceptional performance in demanding environments. This IP core achieves ultra-low latency without compromising on data throughput, making it ideal for real-time applications where timing is critical. It simplifies integration, offering an all-logic architecture that eliminates the need for additional computing power, thereby enhancing efficiency and lowering operational costs.
The CT25203 represents a key building block designed for creating PMD transceivers compliant with the OA TC14 specification. It partners seamlessly with the CT25205 to communicate over the OA 3-pin interface with host MCUs, Zonal Gateway Controllers, or Ethernet switches integrated with a 10BASE-T1S digital PHY. This IP core supports high-performance transceivers encased in compact 8-pin packages. Manufactured with high-voltage process technology, it ensures top-tier electromagnetic compatibility. This capability makes the CT25203 an ideal choice for industrial and automotive applications where reliable communication and exceptional EMC performance are crucial.
KPIT's Powertrain Solutions are at the forefront of modern automotive innovation, focusing on both electric and conventional systems. Designed to enhance vehicle performance and efficiency, these solutions encompass a wide range of technologies that integrate seamlessly with existing vehicle frameworks. The blend of electronic control units and powertrain management systems ensures that vehicles not only perform optimally but also comply with ongoing environmental regulations. In the realm of electric vehicles, KPIT's solutions address the entire powertrain spectrum from energy storage systems to electric control units. This comprehensive approach guarantees that electric vehicles are not only more environmentally friendly but also commercially viable in competitive markets. These technologies enable automakers to push the boundaries of vehicle efficiency, making electric vehicles a practical and appealing option for consumers. For conventional powertrains, KPIT advances the integration of traditional gasoline and diesel systems with cutting-edge software solutions. These enhancements lead to improved fuel efficiency, reduced emissions, and enhanced drivability without compromising on performance. The solutions integrate seamlessly with hybrid systems, further bridging the gap between conventional and electric vehicles. Through years of expertise and innovation, KPIT is paving the way for future automotive technologies that prioritize sustainability and efficiency. Its diversified approach in developing powertrain solutions is pivotal in accelerating the transition towards a cleaner automotive future, making it a valuable partner for automakers worldwide.
The Ethernet Real-Time Publish-Subscribe IP Core provides an advanced hardware solution designed to facilitate real-time data exchange over Ethernet networks. This core supports the RTPS protocol, which is essential for applications requiring timely and deterministic data distribution. Engineered for seamless integration, the RTPS IP Core is an ideal choice for systems needing reliable and efficient data communication, such as in aerospace and defense environments. It enables fast, high-quality data transactions while reducing latency, ensuring that information is transmitted as intended under critical conditions. Coupling a robust framework with flexible configuration options, the Ethernet RTPS core excels in synchronizing data exchanges and maintaining communication integrity. Its architecture supports the demands of mission-critical applications, enhancing the performance and reliability of system operations.
The Network Protocol Accelerator Platform (NPAP) by Missing Link Electronics is engineered to significantly enhance network protocol processing. This platform leverages MLE's innovative patented and patent-pending technologies to boost the speed of data transmission within FPGAs, achieving impressive rates of up to 100 Gbps. The NPAP provides a robust, efficient solution for offloading processing tasks, leading to superior networking efficiency. MLE's NPAP facilitates multiple high-speed connections and can manage large volumes of data effectively, incorporating support for a variety of network protocols. The design ensures that users benefit from reduced latency and improved data throughput, making it an ideal choice for network-intensive applications. MLE’s expertise in integrating high-performance networking capabilities into FPGA environments comes to the forefront with this product, providing users with a dependable tool for optimizing their network infrastructures.
Digital Connected Solutions from KPIT encompass a suite of services that integrate digital capabilities across the automotive ecosystem, ensuring vehicles are equipped for the demands of a digitally connected world. These solutions support seamless communication and data exchange, paving the way for enhanced vehicle intelligence and user interaction. At the core of these solutions lies advanced digital platforms that connect in-vehicle systems with external networks and data resources. KPIT focuses on leveraging data analytics and connectivity to create smart systems capable of adapting to dynamic driving conditions. These digital solutions are crucial in supporting autonomous driving technologies, providing a foundation for vehicles to respond intelligently and efficiently. These solutions are integrated with state-of-the-art cybersecurity measures, ensuring that the data and communications within vehicles remain secure. This emphasis on security is critical as vehicles become more interconnected, necessitating robust defenses against potential cyber threats. The solutions also feature over-the-air updates and remote diagnostics, which maintain vehicle performance and reliability. Overall, KPIT's Digital Connected Solutions are key to revolutionizing how vehicles operate and interact within a connected infrastructure. They enable automakers to offer advanced functionalities that contribute to an enriched driving experience, reaffirming KPIT's role as a leader in automotive digital transformation.
An innovative solution in Intilop's IP product lineup, the UDP Offload Engine (UOE) enhances network performance by transferring UDP packet handling from the CPU to dedicated hardware. This process significantly reduces latency and power usage, making it an invaluable addition to high-demand network environments. The UOE is designed to handle 1G to 10G network speeds efficiently, supporting vast numbers of UDP sessions concurrently with minimal delay.\n\nThis engine stands out due to its flexible integration capabilities, allowing it to be used across a variety of platforms including cloud computing environments and high-performance enterprise networks. With support for comprehensive checksum offloads and direct interface to packet buffers, the UOE efficiently manages data flow, ensuring that application workloads can be streamlined without sacrificing performance.\n\nCustomers deploying the UOE can expect enhancements in bandwidth utilization and system resource allocation, as it offloads network processing tasks that traditionally would consume significant CPU bandwidth. The UOE comes with extensive features that enable it to adapt to varied networking demands while maintaining a very low impact on system resources, thereby delivering enhanced network infrastructure efficiency.
The Dual-Drive™ Power Amplifier FCM1401 is engineered to deliver superior efficiency and performance, specifically designed for demanding RF and mmWave applications. This amplifier distinguishes itself with its ability to produce more RF power while minimizing heat production, making it ideal for applications that require high thermal management. Key to its performance is the patented Dual-Drive™ architecture, which enhances output power and bandwidth significantly. This results in reduced need for large cooling systems and oversized batteries, making it a lighter and more energy-efficient solution. The design is process-agnostic, silicon-proven, and features a small silicon footprint, ensuring high adaptability in various applications. The FCM1401 is built to offer a seamless integration with plug-and-play functionality, allowing for straightforward implementation in existing systems. This makes it a versatile choice for sectors like satellite communications, telecom, and defense, where robust and efficient RF power solutions are critical. The advanced design flow aligns precisely with real-world measurements to within a 2% margin, ensuring reliability and performance consistency.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
The Time-Triggered Protocol (TTP) is an innovative real-time communications protocol used primarily in space and aviation networks. TTP ensures synchronized communication across various nodes in a network, providing deterministic message delivery, which is crucial in systems where timing and reliability are critical. By supporting highly dependable system architectures, it aids in achieving high safety levels required in critical aerospace applications.
The ASPER short-range radar sensor by NOVELIC is a groundbreaking solution that provides superior environmental awareness around vehicles through its 79 GHz frequency band. Designed for automotive applications, ASPER replaces conventional ultrasonic park assist systems, offering a superior 180-degree field of view with a single module. This allows for comprehensive 360-degree coverage with the use of multiple sensors, enhancing detection reliability and reducing blind spots. ASPER's high frequency aids in achieving outstanding accuracy and resolution, crucial for parking assistance and collision warning systems. The radar can detect obstacles as close as 5 cm and as far as 100 meters, making it an ideal choice for urban environments where precision is paramount. With its robust design, ASPER functions effectively even in adverse conditions like fog or dirt, maintaining high performance without interference from environmental factors. The versatility of ASPER extends to various applications, such as blind spot detection, rear cross-traffic alerts, and automated door opening. Its edge processing capabilities allow for domain-specific processing, integrating easily into existing vehicle systems via CAN interfaces. This innovative radar solution is not only cost-effective but also simplifies system complexity, offering a modern alternative to traditional sensors.
The DisplayPort 1.4 is an advanced IP core solution, ideal for fulfilling modern DisplayPort requirements. Available as both a source (DPTX) and a sink (DPRX), it caters to a variety of link rates including 1.62, 2.7, 5.4, and 8.1 Gbps—covering eDP rates as well. Offering support for 1, 2, and 4 DP lanes, this IP core features Native video and AXI stream video interfaces. This IP core supports Single Stream Transport (SST) and Multiple Stream Transport (MST), along with dual and quad pixel clocks for 8 and 10-bit video in RGB, YCbCr 4:4:4, YCbCr 4:2:2, and YCbCr 4:2:0 colorspaces. It also incorporates a secondary data packet interface conducive for audio and metadata transport. To facilitate video processing, the IP comes with a Video Toolbox (VTB), equipped with a timing generator, test pattern generator, and video clock recovery. Its design ensures broad FPGA adaptability, working seamlessly with a variety of devices including AMD UltraScale+, AMD Artix-7, Intel Cyclone 10 GX, Intel Arria 10 GX, and Lattice CertusPro-NX.
The FC Anonymous Subscriber Messaging (ASM) IP Core offers a streamlined hardware-based full-network stack solution specialized for FC-AE-ASM protocols. This core is instrumental in providing hardware-centric approaches to data distribution tasks, offering key features like label lookup, DMA controllers, and sophisticated message chain engines. F-35 aircraft compatibility and the integration of AS5643 protocols allow this core to ensure optimal performance in the exacting realms of aerospace communication systems. By minimizing software overhead, the ASM Core offers enhanced speeds and operational efficiency. This IP is advantageous where high-speed communication integrity is paramount, and where precise, real-time data exchanges are needed. Through performance-focused design, it upholds efficient data management, ensuring that communication networks maintain a dependable and responsive nature vital in mission-critical applications.
Chevin Technology's 10G Ethernet MAC and PCS solution is designed for high-performance FPGAs, enabling robust data transfer with reduced latency and minimal resource usage. This IP core is ideal for applications requiring secure and high-speed data communications, optimizing throughput and reliability. It integrates seamlessly with existing systems, delivering continuous high-speed data rates while ensuring maximum flexibility for further design enhancements.
The Flexibilis Ethernet Switch (FES) is a robust Layer 2 Ethernet switch IP, distinguished by its gigabit capabilities across multiple ports. Apart from basic switching tasks, FES excels with its IEEEv2 end-to-end transparent clock support that greatly enhances network timing accuracy. Ideal for expansive and complex network setups, FES incorporates an array of interface options, QoS features, and supports diverse protocols, making it a flexible choice for industrial applications needing scalability and precision time management.
Ethernet MAC 10M/100M/1G/2.5G IP is a solution that enables the host to communicate data using the IEEE 802.3 standard for 10M, 100M, 1G, 2.5G speeds and is suited for use in networking equipment such as switches and routers. The Client-side interface for the IP is AXI-S and the Ethernet MAC IP comes with GMII, RGMII or MII interfaces on the PHY side. The Ethernet MAC 10M/100M/1G/2.5G IP features a compact and low latency solution, it is highly configurable and can optionally include IEEE 1588 Timestamping Unit (TSU). The Silicon agnostic Ethernet MAC IP, suitable for ASICs and FPGAs, is prepared for easy integration with Ethernet PCS 10M/ 100M/1G/2.5G IP from Comcores.
Credo's SerDes PHY is a pivotal offering in their semiconductor IP portfolio, geared toward custom ASIC solutions and integration into advanced systems. This PHY facilitates seamless integration into next-generation ASICs by employing a sophisticated mixed signal DSP architecture that optimizes performance, power efficiency, and manufacturing cost. The unique design ensures that the SerDes lanes can be deployed across a range of mature and state-of-the-art fabrication processes, delivering leading-edge data transfer speeds and reliability. The SerDes PHY from Credo supports a wide range of applications, particularly in environments that demand high data throughput and minimal latency, such as data centers, AI applications, and telecommunications infrastructure. Its robust architecture accommodates multiple signaling standards, including PAM4 and NRZ, and offers flexibility in terms of reach and bandwidth, ensuring optimal performance across various use cases. Furthermore, Credo's SerDes architecture is designed to facilitate integration flexibility, allowing it to function effectively even when core digital logic and analog components are not deployed simultaneously or within the same process technology. This makes it an ideal component for multi-chip module (MCM) solutions, enhancing system-level performance and reducing design complexity.
The Digital PreDistortion (DPD) Solution by Systems4Silicon is crafted to enhance the power efficiency of RF power amplifiers significantly. Known as FlexDPD, this innovative technology is adaptable and independent of target device vendors, making it suitable for both FPGA/SoC or ASIC platforms. FlexDPD is uniquely designed to maximize efficiency by enabling operations in the non-linear region of amplifiers, and with the integration of GaN devices, over 50% efficiency can be achieved. Additionally, this technology allows for vast compatibility, supporting both multi-carrier and multi-standard transmissions. FlexDPD boasts a scalable architecture that allows optimization based on bandwidth, performance, and the number of antennas or MIMO configurations. Its adaptability enables it to accommodate a range of target resource requirements. FlexDPD's advanced linearization capabilities include compensations for transmitter and observation path impairments and PA memory effects, ensuring minimal distortion enhancements greater than 45 dB. Notably, FlexDPD is vendor-agnostic concerning transistor technologies and amplifier topologies, aligning effortlessly with various communication standards such as FDD, TDD, and 5G. Its broad scope of compatibility extends to technologies like Crest Factor Reduction and envelope tracking and is designed to support O-RAN deployments. This versatile solution is backed by comprehensive documentation and expert support from seasoned radio systems engineers.
The High-Speed SerDes from EXTOLL is an essential component in facilitating chiplet-based designs, offering an advanced solution for data transmission. This SerDes is engineered to provide high-speed data communication necessary for modern computing systems, making it an integral part of system on chip (SoC) architectures. In addition to supporting rapid data transfer between chiplets, it also ensures compatibility with various tech nodes. Designed for ultra-low power consumption, EXTOLL’s High-Speed SerDes utilizes a unique digital-centric architecture. This ensures the component not only supports swift data rates but also optimizes energy efficiency and cost-effectiveness. By delivering high-performance results while minimizing power usage, it meets the critical demands of modern electronic designs. The SerDes is suitable for a variety of applications, especially those requiring rapid signal transfers in compact designs. Its integration capabilities are further enhanced by its architectural compatibility with a range of standard process nodes, including 12nm through 28nm. These features make EXTOLL’s SerDes a leading choice for companies looking to enhance their chiplet technology.
CLOP Technologies' 60GHz Wireless Solution offers businesses an impressive alternative to traditional networking systems. Leveraging the IEEE 802.11ad WiFi standard and Wireless Gigabit Alliance MAC/PHY specifications, this solution achieves a peak data rate of up to 4.6Gbps. This makes it particularly suited for applications that require significant bandwidth, such as real-time, uncompressed HD video streaming and high-speed data transfers — operations that are notably quicker compared to current WiFi systems. The solution is engineered to support 802.11ad IP networking, providing a platform for IP-based applications like peer-to-peer data transfer and serving as a router or access point. Its architecture includes a USB 3.0 host interface and mechanisms for RF impairment compensation, ensuring both ease of access for host compatibility and robust performance even under high data rate operations. Operating on a frequency band ranging from 57GHz to 66GHz, the wireless solution utilizes modulation modes such as BPSK, QPSK, and 16QAM. It incorporates forward error correction (FEC) with LDPC codes, providing various coding rates for enhanced data integrity. Furthermore, the system boasts AES-128 hardware security, with quality of service maintained through IEEE 802.11e standards.
The SMPTE ST 2110 suite from Nextera Video offers a robust IP solution for transporting media over networks. Originally designed for broadcast and professional AV applications, this series of cores empowers equipment to transmit and receive high-quality audio, video, and ancillary data over IP networks rapidly and efficiently. It supports a myriad of sub-standards, ensuring seamless integration with the established infrastructure and promoting future-proofing. Using modular architecture, the ST 2110 cores facilitate the implementation that is both resource-efficient and flexible in configuration. This permits adapting to varied application needs, from uncompressed video handling to audio embedding. The system timing protocols and traffic shaping capabilities minimize latency while optimizing the stream quality, making it ideal for live broadcasts and production environments. Leveraging this technology enables seamless media-over-IP operations in a diverse ecosystem, where precision and reliability are paramount. Nextera Video’s comprehensive reference designs, along with demo projects, ensure clients start with a functional setup that aligns with their specific development pressures and provides an advance industrial solution for media networking.
eSi-Comms provides a comprehensive suite of Communications IP tailored for modern ASIC designs, excelling in parameterization to suit various air interface standards. It includes a wide range of OFDM based MODEM and DFE IPs pivotal for crafting both custom and standards-based communication solutions. The platform supports several contemporary communication standards such as 4G, 5G, and Wi-Fi, and is highly optimized for power, performance, and area. Its sophisticated architecture facilitates simple streaming interfaces, thorough error correction through Viterbi and Reed-Solomon codecs, as well as advanced DSP for synchronization and signal processing. This IP solution is particularly advantageous for designing software-defined radio systems, leveraging EnSilica’s expertise in signal processing and hardware acceleration. The eSi-Comms IP is silicon-proven, with components ready for seamless integration into a range of wireless applications such as remote metering and cellular networks, offering a blend of flexibility and dedicated processing power for efficient communication system development.
The FC Upper Layer Protocol (ULP) IP Core is engineered for a complete network stack implementation tailored to the Fibre Channel - Aerospace Environment (FC-AE) Remote Direct Memory Access (RDMA) or FC-AV standards. Designed for demanding aerospace contexts, this core enables efficient data handling through advanced buffer mapping and direct memory access capabilities. The ULP Core provides comprehensive hardware solutions for label lookup functions, DMA controllers, and message chain engines, enhancing network communication performance. Notably, this core is compatible with F-18 and F-15 aircraft interface modes, ensuring seamless integration across military communication systems. With its robust architecture, the FC ULP Core meets the high-performance demands of fibre channel systems, enabling reliable data path optimization for mission-critical environments. The core supports complex data networking needs, facilitating high-speed data transactions with remarkable efficiency.
The Digital Radio (GDR) from GIRD Systems is an advanced software-defined radio (SDR) platform that offers extensive flexibility and adaptability. It is characterized by its multi-channel capabilities and high-speed signal processing resources, allowing it to meet a diverse range of system requirements. Built on a core single board module, this radio can be configured for both embedded and standalone operations, supporting a wide frequency range. The GDR can operate with either one or two independent transceivers, with options for full or half duplex configurations. It supports single channel setups as well as multiple-input multiple-output (MIMO) configurations, providing significant adaptability in communication scenarios. This flexibility makes it an ideal choice for systems that require rapid reconfiguration or scalability. Known for its robust construction, the GDR is designed to address challenging signal processing needs in congested environments, making it suitable for a variety of applications. Whether used in defense, communications, or electronic warfare, the GDR's ability to seamlessly switch configurations ensures it meets the evolving demands of modern communications technology.
The IPM-NVMe Device from IP Maker serves as a comprehensive PCIe-based storage controller, streamlining data transfers and mitigating the processing load typically managed by an external host CPU. This IP core aligns with UNH-IOL NVM Express specifications, making it a reliable choice for commercial NVMe SSD designs. Equipped to handle multiple channels and DMA processes, the IPM-NVMe Device can orchestrate up to 65,536 I/O queues with weighted round-robin arbitration support. These capabilities, along with full NVMe register support and asynchronous event management, make it a powerful addition to any storage architecture. Its low-power architecture is optimized for PCIe Gen1/2/3/4/5/6, ensuring compatibility across various standards while reducing operating costs. Ideal for FPGA and SoC designs, the IPM-NVMe Device facilitates the construction of both consumer and enterprise-grade SS storage solutions. Integrating seamlessly with the IP Maker's flash controllers and ECC controllers, it provides a cohesive infrastructure for innovative storage solutions, including NVMe NVRAM drives and persistent memory SSDs. This IP core is an excellent foundation for advancing NVMe storage technologies within data centers and high-performance storage applications.
Dyumnin's RISCV SoC is a versatile platform centered around a 64-bit quad-core server-class RISCV CPU, offering extensive subsystems, including AI/ML, automotive, multimedia, memory, cryptographic, and communication systems. This test chip can be reviewed in an FPGA format, ensuring adaptability and extensive testing possibilities. The AI/ML subsystem is particularly noteworthy due to its custom CPU configuration paired with a tensor flow unit, accelerating AI operations significantly. This adaptability lends itself to innovations in artificial intelligence, setting it apart in the competitive landscape of processors. Additionally, the automotive subsystem caters robustly to the needs of the automotive sector with CAN, CAN-FD, and SafeSPI IPs, all designed to enhance systems connectivity within vehicles. Moreover, the multimedia subsystem boasts a complete range of IPs to support HDMI, Display Port, MIPI, and more, facilitating rich audio and visual experiences across devices.
Ubi.cloud is an innovative geolocation solution by Ubiscale designed for device and chipset makers. It fundamentally shifts power-draining GPS and Wi-Fi processes from devices to the cloud. This transition helps in significantly reducing the size and cost of the devices, while dramatically improving their power efficiency. The utilization of cloud-based processing allows for reduced hardware requirements, thereby enabling smaller device footprints and lower energy consumption rates. By focusing on minimizing the physical and energy demands on IoT devices, Ubi.cloud addresses major engineering challenges associated with Global Navigation Satellite System (GNSS). These challenges include managing the life-time of devices, miniaturization constraints due to limited battery capacity, and the integration of various hardware features. Additionally, the cost efficiencies gained from this cloud-centric processing alleviate budgetary pressures, making IoT deployment more economically viable. Ubi.cloud's innovative approach not only supports the creation of more sustainable and efficient IoT devices but also enhances the user's experience by enabling more reliable and robust tracking features. It sets a new benchmark in making IoT solutions more accessible and effective for a wide range of applications.
The ntLDPC_8023CA (17664,14592) IP Core is defined in IEEE 802.3ca-2020 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCE_8023CA encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer when multiplied by the 14592 payload block pro-duces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1 to 6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_8023CA decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_8023CA decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The High Speed Data Bus IP Core offers a complete hardware solution for implementing the PHY and MAC layers of the HSDB standard. It is engineered to seamlessly integrate into systems, providing an easy-to-manage frame interface suitable for aerospace and defense environments. The core delivers robust data transfer capabilities essential for high-speed communication systems onto an HSDB framework to accommodate various operational requirements. This IP core stands out for its adaptability, ensuring compliance with stringent performance criteria. It plays a crucial role in enhancing data throughput and supporting full-rate operations. Designed to work compatibly with F-22 aircraft systems, this core offers a comprehensive package covering label lookup, DMA controllers, and message chain engines. Compatibility with existing systems is a design priority, which allows smooth integration and deployment across diverse platforms. Its advanced architecture supports communication under rigorous environmental conditions, making it an ideal choice for mission-critical applications demanding exceptional reliability.
The RWM6050 Baseband Modem is a cutting-edge component designed for high-efficiency wireless communications, ideally suited for dense data transmission environments. This modem acts as a fundamental building block within Blu Wireless's product portfolio, enabling seamless integration into various network architectures. Focusing on addressing the needs of complex wireless systems, the RWM6050 optimizes data flow and enhances connectivity capabilities within mmWave deployments. Technical proficiency is at the core of RWM6050's design, targeting high-speed data processing and signal integrity. It supports multiple communication standards, ensuring compatibility and flexibility in diverse operational settings. The modem's architecture is crafted to manage substantial data payloads effectively, fostering reliable, high-bandwidth communication across different sectors, including telecommunications and IoT applications. The RWM6050 is engineered to simplify the setup of communication networks and improve performance in crowded signal environments. Its robust design not only accommodates the challenges posed by demanding applications but also anticipates future advancements within wireless communication technologies. The modem provides a scalable yet efficient solution that meets the industry's evolving requirements.
The ARINC 818 Product Suite by Great River Technology is an industry-leading collection of tools and solutions designed to address every aspect of ARINC 818 protocol implementation. This suite provides comprehensive resources for developing, qualifying, testing, and simulating ARINC 818 products, ensuring seamless integration and operation in mission-critical environments. With a focus on the unique requirements of avionics systems, this product suite supports a wide range of high-fidelity video and data communications applications. Great River Technology's suite is renowned for its role in helping organizations bring ARINC 818 products to fruition, offering unparalleled support throughout the product lifecycle. Their guidance in the protocol's implementation is enhanced by an expansive set of development tools and resources, making them a preferred partner for companies looking to enhance their avionics capabilities. This integration capability is essential for creating robust systems that meet the rigorous demands of modern aerospace engineering. The ARINC 818 Product Suite is complemented by expert service and support from Great River Technology, ensuring that customers not only receive top-tier products but also benefit from the company’s extensive experience in the field. As a cornerstone of the company’s offerings, the ARINC 818 suite empowers clients to deliver exceptional performance in their aviation technology projects.
LightningBlu is a sophisticated mmWave connectivity solution explicitly designed for high-speed rail environments. This advanced system offers continuous, on-the-move multi-gigabit connectivity between trackside infrastructure and trains, ensuring seamless internet access, entertainment services, and real-time updates for passengers. Operating within the 60 GHz spectrum and compliant with IEEE 802.11 ad and ay standards, LightningBlu provides robust and efficient wireless communication for the rail industry. The LightningBlu system's standout feature is its ability to maintain reliable service even at speeds of over 300 km/h, enhancing the passengers' travel experience with fast and dependable connectivity. Its architecture allows for dynamic interaction between train-mounted and trackside units, facilitating uninterrupted data transfer essential for modern transport needs. This product not only addresses current connectivity requirements but also positions itself as a future-proof solution adaptable to evolving technological landscapes. Adopting a highly functional design, LightningBlu effectively eliminates the dependency on cabled infrastructure, making it an ideal choice for upgrading existing rail systems or deploying in new corridors. By supporting innovative services and enhancing passenger contentment, LightningBlu contributes significantly to modernizing the rail sector, aligning with the increasing push towards digital transformation in mass transit.
The HOTLink II IP Core provides a comprehensive, layer 2 hardware solution for implementing the HSI communication protocol. Integrated with an intuitive frame interface, it simplifies deployment and supports a range of operational modes, including full-rate, half-rate, and quarter-rate settings, in line with industry standards. This IP core is purpose-built to facilitate high-speed data links while ensuring adherence to communication standards used in military applications, such as the F-18 aircraft. Its robust and scalable architecture guarantees that it can handle high-bitrate environments, ensuring reliable and synchronized data exchange. Its design facilitates quick integration into existing processor and FPGA-based systems. The core's adaptability makes it suitable for complex systems requiring real-time data transactions, reinforcing its utility in high-demand environments like avionics and secure communications.
The FC Link Layer (LL) IP Core serves as a full-fledged hardware solution for implementing the Fibre Channel FC-1 and FC-2 layers. Designed for high-speed data environments, it directly addresses the challenges of handling complex data streams across networks in mission-critical aerospace applications. This IP core ensures precise and reliable communication through its robust architecture, excelling in data throughput and latency management. Its functionality enriches network layers, allowing seamless integration into systems requiring stable, high-speed data services. By supporting advanced interface modes and providing a complete hardware configuration, the LL Core enhances operational capabilities and reliability for military and aerospace industries. This vital component in the communication infrastructure underscores high levels of interconnectivity needed in complex network frameworks.
The Advanced Flexibilis Ethernet Controller (AFEC) delivers a high-performance triple-speed Ethernet interface designed for programmable hardware and ASICs. Beyond standard Ethernet functionalities, AFEC aims to minimize CPU workload through features like DMA transfers and scatter-gather operations. Supporting IEEE 1588 for precise timing, this controller is well-suited for applications where accurate synchronization and high data throughput are critical. It offers a seamless connection to various Ethernet physical layer devices via standard interfaces.
APIX3 represents the third-generation transmission technology developed by INOVA, targeted at enhancing infotainment and cockpit architectures in vehicles. This series features transmitters and receivers that can handle multiple ultra-high-definition (UHD) video streams and Ethernet communication over shielded twisted pairs or quad twisted pairs. APIX3 is uniquely positioned to meet the demands of high bandwidth automotive applications, supporting data rates of up to 6 Gbps on a single shielded cable and reaching up to 12 Gbps on quad twisted pair connections. This improved bandwidth allows for seamless transmission of multiple video and data channels, crucial for the sophisticated display systems used in modern vehicles. The technology also emphasizes diagnostic capabilities, including cable monitoring for preemptive maintenance, enhancing the reliability and longevity of the overall system. Its backward compatibility with APIX2 ensures a smooth transition and integration into existing setups, making it a flexible and future-proof solution for automotive manufacturers.
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