All IPs > Memory & Logic Library > I/O Library
The I/O Library within the Memory & Logic Library category encompasses a wide range of semiconductor IPs focused on input and output interfacing. These IPs are critical for ensuring efficient data communication and integration between different parts of an electronic system. They play a pivotal role in defining how devices connect and interact with each other, which is crucial for the design of versatile and robust electronic products.
I/O Libraries are meticulously designed to support various communication protocols and standards, enabling seamless connectivity. They can include a variety of interfaces such as GPIOs (General Purpose Input/Outputs), UARTs (Universal Asynchronous Receiver-Transmitter), SPI (Serial Peripheral Interface), and I2C (Inter-Integrated Circuit) among others. Each type of interface IP ensures high compatibility and interaction efficiency, tailored to meet the specific needs of different applications ranging from simple consumer electronics to complex industrial solutions.
These semiconductor IPs are integral in reducing design time by providing pre-verified components, which developers can modularly integrate into their chip designs. By utilizing these I/O IP components, designers can significantly streamline the development process, meeting tight deadlines while achieving high-performance standards. The versatility of these IPs allows for easy customization and adaptation to various technological requirements, thus providing a flexible foundation for innovative electronic product development.
In addition to supporting various communication protocols, I/O Libraries also adhere to stringent electrical and timing specifications, ensuring reliable and consistent performance across devices. These libraries are critical in environments where precision and reliability are paramount, making them indispensable for designers focused on creating cutting-edge technology solutions. Overall, I/O Library semiconductor IPs are a cornerstone of contemporary electronics design, enabling a seamless blend of performance, compatibility, and scalability.
xcore.ai is a versatile and powerful processing platform designed for AIoT applications, delivering a balance of high performance and low power consumption. Crafted to bring AI processing capabilities to the edge, it integrates embedded AI, DSP, and advanced I/O functionalities, enabling quick and effective solutions for a variety of use cases. What sets xcore.ai apart is its cycle-accurate programmability and low-latency control, which improve the responsiveness and precision of the applications in which it is deployed. Tailored for smart environments, xcore.ai ensures robust and flexible computing power, suitable for consumer, industrial, and automotive markets. xcore.ai supports a wide range of functionalities, including voice and audio processing, making it ideal for developing smart interfaces such as voice-controlled devices. It also provides a framework for implementing complex algorithms and third-party applications, positioning it as a scalable solution for the growing demands of the connected world.
Certus Semiconductor's Digital I/O solutions are engineered to meet various GPIO/ODIO standards. These versatile libraries offer support for standards such as I2C, I3C, SPI, JEDEC CMOS, and more. Designed to withstand extreme conditions, these I/Os incorporate features like ultra-low power consumption, multiple drive strengths, and high levels of ESD protection. These attributes make them suitable for applications requiring resilient performance under harsh conditions. Certus Semiconductor’s offerings also include a variety of advanced features like RGMII-compliant IO cells, offering flexibility for different project needs.
Silvaco's Standard Cell Libraries offer robust solutions with thousands of optimized cells designed to meet the power, speed, and area requirements of high-performance applications. These libraries provide engineers with ECO Kits for late-stage design modifications and Power Management Kits to enhance power efficiency. They cater to multiple processes, including those at the forefront like TSMC's 3nm technology, enabling designers to manage power efficiency uniquely with features like low voltage operation at 0.45 V.
RegSpec is a cutting-edge tool that streamlines the generation of control and status register code, catering to the needs of IP designers by overcoming the limitations of traditional CSR generators. It supports complex synchronization and hardware interactions, allowing designers to automate intricate processes like pulse generation and serialization. Furthermore, it enhances verification by producing UVM-compatible code. This tool's flexibility shines as it can import and export in industry-standard formats such as SystemRDL and IP-XACT, interacting seamlessly with other CSR tools. RegSpec not only generates verilog RTL and SystemC header files but also provides comprehensive documentation across multiple formats including HTML, PDF, and Word. By transforming complex designs into streamlined processes, RegSpec plays a vital role in elevating design efficiency and precision. For system design, it creates standard C/C++ headers that facilitate firmware access, accompanied by SystemC models for advanced system modeling. Such comprehensive functionality ensures that RegSpec is invaluable for organizations seeking to optimize register specification, documentation, and CSR generation in a streamlined manner.
APB4 GPIO by Roa Logic is a comprehensive and adaptable core that introduces a user-defined number of general-purpose, bidirectional input and output channels to designs. It provides a flexible interface for developers who require customizable GPIO settings in their embedded systems, making it suitable for a wide range of applications in different industry verticals.
The Universal DSP Library is a versatile and comprehensive solution designed to simplify digital signal processing tasks in FPGA applications. It provides a robust framework for handling complex signal processing requirements, enabling developers to integrate advanced DSP functionalities efficiently into their systems. This library is crafted to offer flexibility and adaptability, supporting a wide range of applications in various industries. This DSP library stands out for its ability to handle diverse signal processing operations with ease. By offering pre-built functions and modules, it reduces the complexity traditionally associated with DSP implementation in FPGA designs. Developers can leverage this library to accelerate their development cycles, ensuring quicker time-to-market for their products. Incorporating the Universal DSP Library into an FPGA design allows for enhanced performance and efficiency, as it optimizes the processing power of FPGAs to manage demanding signal processing tasks. Its design enables seamless integration with existing systems, providing scalable solutions that can adapt to future needs. Overall, this library is an invaluable asset for any project involving digital signal processing on FPGA platforms.
The Configurable I/O from SkyeChip offers high-speed interfaces capable of signaling speeds up to 3.2 GT/s. This versatile I/O solution supports a range of standards, including LVDS, HCSL, POD, SSTL, HSTL, HSUL, LVSTL, and LVCMOS, covering voltages from 1.1V to 1.5V. This flexibility makes it apt for a variety of applications requiring custom I/O configurations. Its ability to accommodate multiple protocols and signal standards makes this I/O solution particularly suited for complex system designs that demand robust signaling capabilities across different voltage levels. Featuring support for both high-speed and low-power operational modes, the configurable I/O balances performance with energy efficiency. Ideal for deployment in systems requiring adaptable interface options, this Configurable I/O IP offers high reliability and compatibility with diverse hardware interfaces, enabling seamless integration in a variety of technological environments.
The I/O semiconductor solutions from Analog Bits are designed to interface with multiple systems, ensuring seamless signal transmission across a variety of applications. These solutions offer a comprehensive range of features, including differential signaling and CMOS compatibility, enabling optimal communication within integrated circuits. By providing robust I/O management, these solutions help maintain signal integrity and efficiency. Analog Bits' I/O IP is distinguished by its adaptability to various process nodes, making it highly versatile in applications ranging from consumer electronics to industrial automation systems. The technology supports robust data transfer and is tailored to meet the demands of modern high-performance computing environments where quick, reliable communication interfaces are crucial. The solutions align with the complex requirements of contemporary digital systems, facilitating superior performance and power management. With features designed to minimize electromagnetic interference and ensure high fidelity in signal transmission, the I/O IP from Analog Bits is a pivotal component in the deployment of advanced semiconductor technologies.
Spectral CustomIP caters to bespoke memory architecture needs, offering a wide array of specially designed memory structures like Binary and Ternary CAMs, and multi-ported memories. These solutions integrate optimized circuitry for high speed and low power, ideal for complex IC applications. Spectral CustomIP is based on standard CMOS technology and is suitable for SOI or embedded Flash processes, making it versatile for various applications. Each module uses SpectralTrak technology for proactive monitoring of operational conditions, ensuring robust performance across different environments. The products support extensive configurability options like multi-bank and multi-port architectures, allowing for a tailored fit in specific applications. CustomIP addresses specialized requirements in networking, graphics applications, and mobile devices, providing unique power-down and test mode features. Offering a comprehensive set of tools for custom development, these solutions can be extensively modified and optimized by customers, delivering added value in terms of flexibility and control.
CodaCache is Arteris' solution for addressing memory latency issues in SoC designs through an optimized last-level cache configuration. This sophisticated shared cache greatly improves the data flow within the system, leading to enhanced overall SoC performance and power efficiency. By reducing reliance on main memory for frequently accessed data, it minimizes delays and energy consumption, making it ideal for modern computing workloads. Configurable to meet diverse performance and efficiency needs, CodaCache allows fine-tuning that unlocks its full potential in various scenarios. This includes seamless integration through AXI support, which facilitates efficient component communication, expediting developments and modularity in SoC architectures. With a focus on ensuring high performance through reduced latencies and lower power requirements, CodaCache is essential for applications seeking to strike a balance between speed and energy efficiency. The cache’s design emphasizes quicker access to stored data, which is pivotal for industries striving to develop faster processing capabilities without increasing power consumption and development time.
Tower Semiconductor offers Non-Volatile Memory (NVM) solutions that cater to robust data storage needs in modern electronics requiring reliable data retention. These technologies are integral in maintaining data integrity without the necessity for continuous power, proving essential in a variety of embedded systems and devices. The NVM solutions emphasize endurance and data retention, engineered to address the intricate demands of sectors such as automotive, industrial control, and consumer electronics. This technology facilitates the development of memory components capable of sustaining high write and erase cycles, contributing to the durability of electronic products. The integration of NVM solutions into numerous applications signifies Tower Semiconductor's ability to meet specific technological requirements, offering scalable solutions that are both efficient and effective in their application. Their design flexibility ensures adaptability to diverse process nodes, ensuring broad compatibility across multiple platforms.
SEMIFIVE's SoC Platform provides a comprehensive solution for rapid system-on-chip (SoC) development, tailoring these designs to various key applications. Leveraging purpose-built silicon-proven IPs and optimized design methodologies, it enables lower cost, minimized risk, and swift turnaround times. The platform employs a Domain-Specific Architecture, utilizing pre-configured and verified IP pools, making the integration and development process significantly faster and less complex. This platform is equipped with hardware/software prototypes that ensure customers can bring their ideas to fruition with less overhead and enhanced efficiency. It features technical highlights like the SiFive quad-core U74 RISC-V processor, LPDDR4x memory interfaces, and cutting-edge peripheral interfaces including PCIe Gen4, facilitating various applications ranging from AI inference to big data analytics and vision processing. Customers benefit from significantly reduced non-recurring engineering (NRE) costs and time-to-market durations that are up to 50% lower than the industry average. This framework maximizes design and verification component reusability, therefore reducing engineering risks. Its silicon-proven design ensures reliability and offers a variety of engagement models to cater to the unique needs of different projects.
Rabbit 2000 is a pioneering microprocessor suitable for a wide array of applications, featuring 19K gates in its design and occupying 100 pins. It offers a compact and efficient core, well-suited for integrating into systems where space and power are constrained. This processor is foundational in the Rabbit series and demonstrates excellent performance as a standard 8-bit microprocessor. The Rabbit 2000 architecture promotes seamless integration into larger systems with minimal design overhead. It provides a reliable base for developing sophisticated projects that require a blend of processing power and unique peripheral interfaces. The model has been thoroughly proven in silicon, ensuring robustness and reliability from prototype to mass production. This processor also supports various standard interfaces, simplifying the design process for developers needing a versatile processing unit with peripheral connectivity. Its versatile design makes it applicable in numerous applications, from embedded systems to industrial controllers.
The 1D Optical Micrometers from Riftek Europe are non-contact devices specifically fashioned to measure diameters, gaps, and displacements with exceptional accuracy. They cater to the dimensional measurement needs across a wide range extending from 5 mm to 100 mm, with an impressive measuring accuracy of +/- 0.3 um aided by a sampling rate of 10000 Hz. These micrometers are indispensable in production lines where small part measurement is vital, such as mechanical engineering and electronic component manufacturing. Their high-speed data acquisition and precision allow for dynamic measurement, ensuring that product specifications are consistently met. Their efficient design and robust capabilities provide significant advantages in applications requiring quick and accurate dimensional checks, thereby minimizing manual inspection processes. The integration of this technology supports comprehensive monitoring and control frameworks that enhance overall production quality.
Dolphin Semiconductor's Foundation IPs are crafted to enhance the efficiency and cost-effectiveness of System-on-Chip (SoC) designs through robust offerings of embedded memories and standard-cell libraries. Specially designed for energy-efficient applications, these components help optimize space and power usage while ensuring the cutting-edge performance of modern electronic devices. Incorporated within Dolphin's Foundation IP portfolio are standard cells that allow chip designers to achieve up to 30% density gains at the cell level, compared to conventional libraries. Further, these components are engineered to support always-on applications with exceptionally low leakage rates. The Foundation IP suite optimizes SoC designs by delivering dramatically reduced leakage and area consumption, avoiding the additional cost and complexity of using a regulator. The memory compilers within Foundation IPs offer ultra-low power and high-density memory solutions, including SRAM and via-programmable ROMs. These are formulated to deliver up to 50% energy savings, providing flexibility with multi-power modes and adaptable to varied instances. With optimization for TSMC processes, Dolphin's Foundation IPs provide an essential backbone for creating innovative, efficient, and sustainable SoC products.
DXCorr's SRAM solution is a high-performance, low-power Static Random-Access Memory tailored for demanding applications. Built with precision, the SRAM from DXCorr ensures exceptional speed while maintaining energy efficiency, making it an ideal choice for cutting-edge systems. The design caters to contemporary needs of bandwidth and storage, providing a robust framework that supports a wide range of digital processors. The SRAM solutions are crafted to address both high-density and high-speed requirements, ensuring adaptability across various technological challenges. What sets DXCorr's SRAM apart is its ability to perform in processes as small as 2nm, delivering industry-leading power efficiency and reliability. The meticulous structure supports standalone as well as embedded applications that require extreme data throughput and minimal latency, thus catering to a diverse spectrum of client needs. Coupled with DXCorr's extensive portfolio of cross-functional IPs, the SRAM emerges as a flagship product that exemplifies both innovation and performance. It offers flexibility in design, making it suitable for integration into a variety of platforms, from telecommunication systems to consumer electronics, proving its versatility and adaptability. Crafted under high-quality standards, it assures customers of peak performance and long-term reliability as a data storage solution.
The Absolute Linear Position Sensors developed by Riftek Europe are precision instruments designed to measure and check displacements, dimensions, and surface profiles. Utilizing absolute linear encoder technology, these sensors promise an innovative approach to absolute measurement over ranges of 3 mm to 55 mm with a resolution of 0.1 um. These sensors address the demand for accurate measurement within manufacturing environments, ensuring that the run-outs and deformations are controlled to enhance product quality. They are built for reliability, delivering robust performance in challenging industrial conditions where precision is a crucial aspect of equipment and product assembly. Engineered to provide real-time feedback, these sensors aid in automating quality checks and maintaining operational efficiencies. They offer manufacturers the ability to optimize processes and reduce errors, further promoting productivity and reducing material wastage due to inaccurate measurement during production.
xcore-200 leverages multicore microcontroller technology to deliver exceptional processing power for embedded systems. Built to handle intensive DSP and I/O tasks, it excels in environments requiring seamless integration of voice, audio, and data processing. This processor is ideally suited for applications in consumer electronics and industrial control, offering a balance of high processing capability and energy efficiency. With its deterministic performance and support for various communication interfaces, xcore-200 ensures reliable operation across diverse environments. By facilitating sophisticated signal processing and real-time control, xcore-200 enables developers to implement innovative solutions that meet demanding technical specifications. Its adaptability makes it a go-to choice for applications requiring robust computational frameworks and high-speed processing capabilities.
X-REL is EASii IC’s line of semiconductor products explicitly tailored for extreme environments, featuring extraordinary reliability at temperatures ranging from -60°C to +230°C. These high-reliability components address the rigorous demands across sectors like oil and gas, geothermal energy, aerospace, and automotive. Available in various packages, including ceramic, metal, and, for less constrained environments, plastic, X-REL products offer extended life with minimum system cost. These components are engineered to fulfill the need for continuous operation under severe conditions, delivering five years of guaranteed reliability. X-REL’s diverse lineup encompasses power management solutions, clock and timing circuits, discrete transistors and diodes, and interfaces. The robust performance of these components, coupled with certifications like ISO9001 and EN9100, underscores their suitability for mission-critical applications, where traditional designs may falter due to adverse heat and stress.
Riftek Europe’s 2D Optical Micrometers are designed for batch in-line dimensional measurement, offering a sophisticated solution for industries demanding precision in wire and rod measurements. The measurement scope of these micrometers spans from 8x10 mm to 60x80 mm, with outstanding accuracy up to +/-0.5 um, making them suitable for high-precision industries. These micrometers expedite measurement tasks in industrial environments, reducing manual work by automating the dimensional analysis of numerous components rapidly. By employing advanced optoelectronic technology, these devices simplify the acquisition of precise dimensional characteristics across multiple parameters. The real-time data collection capability of these devices supports seamless integration into assembly lines, enabling consistent measurement that reduces defects and assures high manufacturing standards. This contributes significantly to improving efficiency and operational throughput, aligning with the demands of fast-paced production environments.
Rezonent's Compute-in-Memory Technology fuses computational and memory functionalities within a single architecture to enhance processing speed and reduce power consumption. This innovative technology minimizes data movement between memory and the processor, which significantly speeds up data-intensive tasks and dramatically lowers energy usage. By utilizing sophisticated data encoding techniques, the technology optimizes storage and retrieval processes, making it ideal for AI and machine learning applications. Designed to excel in scenarios that require rapid data processing and efficient power management, Compute-in-Memory Technology addresses practical challenges faced by data centers and IoT devices. This technology effectively supports the burgeoning demand for faster processing in edge computing, where power efficiency is paramount. Its architecture is adaptable, allowing deployment across various systems, from conventional servers to cutting-edge AI models. Moreover, its integration into semiconductor designs ensures backward compatibility, offering enhanced performance without drastic changes to existing infrastructure. As data demands continue to rise, Rezonent's technology provides a scalable solution that meets the needs of modern computing applications, delivering both speed and sustainability.
MiniMiser emerges as a revolutionary multi-port register file architecture designed to combine low power and high-performance capabilities. Its unique design effectively reduces power consumption by over 50% and presents a powerful alternative to conventional register files. By providing various performance modes configured to specific operating voltages, MiniMiser allows System on Chip (SoC) developers to precisely tailor their products' power profiles to exact application requirements. As complexity in wearable devices increases, the need for efficient power management becomes crucial. MiniMiser's role expands here, providing an elegant solution that allows for the replacement of standard off-the-shelf register files, significantly cutting power without sacrificing efficacy. This adaptability is particularly critical for computational heavy applications requiring substantial interim data storage or interfacing between different clock domains. MiniMiser's innovative tuneable structure means it sidesteps traditional constraints, supporting high-read/write port counts, wide voltage ranges, and maintaining high performance with minimal power draw. Its architectural flexibility paves the way for the next generation of wearable devices, ensuring extended life through intelligent power usage.
The Embedded ReRAM module by Weebit Nano is a cutting-edge memory solution designed to integrate seamlessly into System-on-Chip (SoC) architectures. Operating predominantly on SkyWater Technology's 130nm CMOS process, this IP offers a highly reliable and scalable non-volatile memory option. Its design emphasizes low-power consumption and high data retention, making it ideal for IoT devices, automotive systems, and AI applications. The ReRAM module incorporates advanced circuitry, including optimized voltage references and smart algorithms that enhance reading, setting, and resetting processes. Additionally, control logic and input/output communication elements ensure seamless integration into various digital platforms. Weebit Nano's focus on robust error correction, through redundancy and error-correcting code (ECC), further enhances the reliability and performance of the memory module. For semiconductor design teams, the ReRAM module comes with comprehensive collateral and electronic design automation (EDA) views, facilitating smooth integration into existing systems using leading EDA tools. Offering customizable storage capacities and compatibility across a variety of process nodes from 180nm to 22nm, this module is adaptable to a wide range of applications and design requirements.
Key ASIC offers a broad range of foundational IP solutions including standard cell libraries, I/O libraries, and SRAM compilers, tailored to meet the evolving needs of chip designers. These IPs are silicon-proven and optimized for a diverse range of applications. They cater to different voltage levels including LVCMOS inputs/outputs (I/O) at 1.2V, 1.8V, and 2.5V, providing designers with tools to achieve efficient performance benchmarks. Included in their foundational offering are PLLs and DLLs operating up to 500MHz, which enhance chip timing accuracy. For system reliability, power-on reset circuits and robust voltage regulators are provided, ensuring stable operations across different power requirements. These components are integral in designing circuits that demand precision and robust operations. Key ASIC's IP solutions have been specifically crafted to cater to high-density integration needs across consumer electronics and communication devices. With a focus on power efficiency, these IPs are designed to support the rigorous demands of modern electronic applications, ensuring clients can produce cutting-edge and competitive products.
VisualSim Technology IP comprises an extensive library of Technology IP blocks crucial for system modeling and design. This collection includes over 150 IP blocks that facilitate comprehensive system-level exploration across multiple application domains. These blocks encompass both hardware and software elements such as processors, memory, interfaces, and RTOS schedulers, among others, allowing for versatile and detailed system modeling. The IP blocks in the VisualSim Technology collection are designed for functionality, timing, and power accuracy, ensuring that system models reflect realistic operational behavior. They are meticulously crafted according to the specifications from standard bodies or vendor datasheets and undergo validation against timing diagrams and throughput metrics. Each block contains adaptable parameters to suit various design needs, making them highly configurable for diverse engineering applications. Another key feature is the robustness of its interface support. The IP blocks feature polymorphic connectivity, which eliminates the need for custom protocol converters. This seamless integration capability with other system components aids in streamlining the design process and enhancing overall system performance. Additionally, the comprehensive reporting functionality, which includes metrics such as buffer usage and processor pipeline stalls, provides detailed insights into system performance, aiding in the optimization of design configurations.
IQonIC Works’ Intelligent Sensor and Power Management Platform (ISP) provides an all-encompassing solution for the development of sensor-based, intelligent, embedded applications. The platform emphasizes key areas like power management, energy harvesting, sensor interfacing, and processing, utilizing a rich variety of design building blocks and pre-assembled, validated sub-systems. By offering this suite as an integrated platform, IQonIC Works ensures that projects aimed at developing new ASICs or improving existing designs can maintain budget and time constraints more typical of derivative projects. The ISP expands the scope of possibilities in diverse applications, especially those associated with IoT, by delivering modular and scalable design tools. Additionally, the ISP supports various MCU cores and I/O IP configurations, allowing solutions to be tailored to specific application requirements. It integrates easily with other design blocks, providing the flexibility needed to accommodate additional features such as communication and security, making it an invaluable resource for advanced IoT and sensor applications.
The Quazar Quad Partition Rate (QPR) Memories are engineered to revolutionize the design and efficiency of high-speed, low-latency memory systems in FPGAs. By replacing multiple Quad Data Rate (QDR) devices with a single, robust IC, Quazar delivers exceptional memory performance that caters to the sophisticated demands of today's technology applications. Utilizing advanced QPR technology, Quazar enables system architects to leverage higher bandwidth and reduced operational costs by compressing multiple serial connections into a streamlined configuration. The product is available in two variants, QPR4 and QPR8, offering versatile memory capacities of 576Mb and 1Gb respectively. Designed with partitioned architecture, the Quazar devices offer flexible operational modes—Deep and Wide—allowing users to tailor memory functions according to their specific application needs. This architecture not only supports high-data-rate operations but also enhances signal integrity and reliability. Furthermore, the easy-to-integrate MoSys FPGA RTL Memory Controller simplifies the adoption of these memory solutions into existing systems, enabling a seamless transition without extensive redesign efforts.
This library is a production-quality, silicon-proven I/O library in TSMC 12nm technology. Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level. Also included are various open-drain I/Os and hot plug detects capable of up to 5V operation. The library also includes a wide-variety of low-capacitance RF and analog ESD. There have operating ranges from 0 to 5V protection and support a wide range of high-performance interfaces including HDMI, LVDS, USB and wireless front-ends. Also included is a range of IEC 61000-4-2 system-level ESD protection that supports digital and analog I/O cells.
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The BCH Encoder/Decoder core from IP-Maker is essential for mitigating errors in NAND Flash memory, thus extending the lifetime and reliability of storage devices. Built on the powerful BCH algorithm, this IP core is fully customizable based on application-specific needs, from consuming minimal resources to optimizing latency. By offering support for up to 84 error-bits per block and configurable block sizes, it ensures robust data protection across varied storage environments. The IPM-BCH benefits from a well-balanced performance and gate count, making it suitable for high-performance NAND Flash-based applications.
The i.MX 94 Applications Processor is an innovative preproduction MPU that stands out due to its integrated Time-Sensitive Networking (TSN) switch that provides extensive protocol support. This cutting-edge feature makes the processor ideal for applications requiring robust, real-time data transmission, ensuring data packets are delivered with precision and low latency across networked systems. Built to meet the demands of modern industrial applications, the i.MX 94 offers a suite of capabilities for smarter and more connected devices. It excels in high-performance environments where accurate and synchronized communication is paramount, such as in advanced manufacturing setups and automated industrial processes. Moreover, the i.MX 94 Applications Processor supports dynamic edge computing capabilities. This enhances the processor's potential in sprawling industrial ecosystems, where distributed intelligence and multi-protocol communication are increasingly essential.
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The LittleBee family of FPGAs is known for its flash-based non-volatile design, offering low power consumption and minimal package sizes, as small as 2.4x2.3mm. These FPGAs are particularly suited for I/O intensive applications, providing solutions for source synchronous interfacing and bridging in systems using protocols such as MIPI CSI-2, MIPI DSI, USB 2.0, Ethernet, and HDMI. These devices are tailored for hardware management applications due to their instant-on capability and built-in security functions. LittleBee FPGAs are further enhanced by features such as extended memory, hardened ARM Cortex-M processor cores, and Bluetooth Low Energy (LE), enriching their functionality and broadening their application scope compared to traditional FPGA offerings. Notably, the LittleBee series enhances its capabilities with an emphasis on quick boot sequences and robust security, making it suitable for applications spanning from consumer electronics to industrial applications requiring compact and efficient FPGA solutions.
This library is a production-ready I/O library built on the TSMC 12nm process. The library features 1.8V to 3.3V GPIOs with programmable drive strength, hysteresis, and control logic. It includes support cells for all power domains: 0.8V, 1.8V, and I/O and incorporates latch-up immune, JEDEC-compliant ESD structures. The library is designed for flip-chip packaging and includes vertical and horizontal variants to support all die edge orientations. All power domains include integrated power-on control (POC) cells for safe and reliable sequencing.
This is an ultra-low leakage library. The GPIO has a typical leakage of only 150pA from VDDIO and 1nA from VDD. The library has a GPIO and an ODIO. The GPIO cell set can be configured as input or output and has an internal 50K ohm pull-up or pull-down resistor. Cells for I/O and core power and ground with built-in ESD circuitry are included. A power-on-control circuit is integrated into an available VDDIO cell. The library includes pads for analog signals and a 6.5V one-time-programming voltage. The GPIO can do TX and RX up to 100MHz. The ODIO is I2C compliant. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.
This is an ultra-low leakage library. The GPIO has a worst-case leakage of only 425nA. It works with a wide VDDIO supply range from 1.8V to 3.3V during system operation without the need for the customer to manually switch between high and low-voltage modes. The GPIO cell set can be configured as input or output and has an internal 50K ohm pull-up or pull-down resistor. It has a sleep function which - when enabled - puts the I/O into an ultra-low power state and latches the I/O in the previous state. Cells for I/O, core power, and ground with built-in ESD circuitry are included. A power-on-control circuit is integrated into an available VDDIO cell. The GPIO can do TX and RX up to 150MHz. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.
This silicon-proven TSMC 28nm Digital I/O Library delivers a low-capacitance, high-reliability interface solution optimized for advanced semiconductor applications. Featuring low-capacitance LVDS differential pairs (<250fF per pin) at 0.8V, this library ensures superior signal integrity for high-speed applications. The I/O macro seamlessly integrates with the TSMC 1.0V I/O Library, sharing a compatible VDDA and VSSA bus structure for streamlined power management. Designed with a 14-bondpad ESD macro, including two differential pairs and dedicated power/ground cells, it provides a robust 0.8V VDDA power domain with a 0V ground reference. Engineered for reliability, the library avoids minimum-width metal traces and adheres to enhanced via/contact recommendations for long-term durability. With Cadence OA database compatibility, the library supports Spectre and auCdl views, enabling seamless simulation, LVS verification, and integration into standard design flows.
This library is a mixed Digital and Analog library built for the TSMC 65nm process. It is based around a Fail-Safe General Purpose Input/Output (FSGPIO) cell that is compatible with both I2C and I3C protocols. The FSGPIO operates with a power supply of 1.0 to 1.2V and can tolerate external signals up to 3.3V. The library contains all the power, ground, and ESD cells to support the FSGPIO as well as an Analog I/O cell. The cells are laid out in an inline wirebond format.
This silicon-proven, flip chip library in TSMC 22nm boasts three variants of GPIOs and one ODIO. All GPIO and ODIO cells have NS and EW orientation. All GPIO types are classified based on speed: 25MHz, 75MHz and 150MHz. All GPIO speed variants can operate at different post-driver voltage, which can be set at the system level and dynamically changed in the system if needed. The I/O includes a weak pull-up or pull-down resistor (approx. 60 Ohms). The ODIO is designed for lower speed interfaces but can be used as a high-voltage, high-speed input at up to 100MHz. The library is designed to allow for independent power sequences of any I/O cell, which is accomplished with an intrinsic power-on-control architecture. In the case of GPIO and ODIO, only when all powers are up and detected as ON, will the I/Os begin to function, otherwise they will remain in a high impedance state. Beyond standard ESD protection, the library is tolerant to 61000-4-2 IEC standard to 2kV.
This radiation-hardened, by design, library features both a 1.8 and 3.3V GPIO with multiple drive strengths of 2mA, 4mA, 8mA, and 16mA, along with a full-speed output enable function. The library includes an LDO to generate a 1.8V reference which has been optimized for use with the 3.3V GPIO. The library incorporates radiation-hardened ESD cells, which are silicon-proven. A fail-safe GPI allows user to interface with bus-type protocols like I2C. All cells support independent power sequencing and integrate power-on-control circuitry for a clean low-leakage power-up. A selectable Schmitt trigger receiver adds input flexibility, while a 50K ohm pull-up or pull-down resistor is available for termination configurations. The library is enriched with feed-through, filler, transition, and domain-break cells to allow for flexible pad ring construction while maintaining ESD robustness. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.
This silicon-proven, I/O Library features a 5V General Purpose I/O, 5V Open-Drain I/O, 5V Analog I/O, 5V Power Supply and an area efficient 5V ESD protection scheme. The functional cells in the library (GPIO & ODIO) feature an Output Enable pin which, when de-asserted, place the I/O in a HiZ state, and can control multiple modes of output operation with the Output Mode Control pins. The input RX path for this library all have selectable operations between a Schmitt trigger input with hysteresis, a standard buffer with no hysteresis, and a low input voltage mode that can receive a voltage level much lower than the I/O supply without causing metastability or large leakage current. The library has no poly orientation limitations and can be used in any orientation. The library cells are only built up to metal three, but include an metal 4 pad anchor that can be overlaid with either a wirebond or connected to a BUMP. ESD design level are 2kV HBM, 500V CDM and +/-125mA Latch-up.
This library is a production-quality, silicon-proven I/O library in GlobalFoundries 65/55nm technology. The library offers a 3.3V GPIO with two selectable inputs, slew rate control, and an optional active tri-state, as well as a GPIO with an ultra-wide supply range and an optional glitch filter. The library also includes a 1.2V ODIO with two slew rate options as well as a 3.3V ODIO with a 5V tolerance. All I/Os have highly programmable POC options and active pull up/down. The library is compliant with ANSI/JEDEC/ESDA JS-001-2014 ESD standards.
A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation. The GPIO cell can be configured as input, output, open source, or open drain with an optional internal 50K ohm pull up or pull down resistor. Four selectable drive strengths are offered (25 235MHz @ 1.8V, 10pF) to optimize across SS) currents & power. The output driver exhibits 50 ((20%) termination across PVT to reduce reflections at higher operating frequencies. Supply cells for VDDIO, VREF, and core VDD include necessary built in ESD circuitry. A 5VI2C / SMBUS open drain (fail safe) cell, 5V OTP, programming gate cell and 1.8V & 3.3V analog cells with ESD protection are included. The library features protection break cells to allow for separate grounds while maintaining ESD robustness. ESD design targets 2kV HBM, & 50 0V CDM, yet this library has constantly demonstrated 4kV HBM. This library can also support 2kV IEC 6100-4-2 system ESD with appropriate integration.
Specialized for audio rate applications, the STAR1011 is an ultra-low power ADC with a dynamic range of 92dBA, consuming under 110 microamps. This silicon-proven IP, fabricated in a 65nm process, offers exceptional configurability and stable performance. It is particularly useful for audio applications requiring low power usage without compromising on signal quality, ensuring effective operation in both mobile and embedded systems.
This flip-chip compatible library in Dongbu HiTek 130nm features a fail-safe GPIO, two standard GPIOs, a 5V GPI, and 5V I2C-compliant ODIO. The GFGPIO is a highly configurable 5V tolerant, multi-voltage, multi=-protocol I/O. The standard GPIO, both regular and reduced footprint, in this library is a highly configurable 5V tolerant, multi-voltage, multi-protocol I/O. The library’s GPI is a highly configurable general-purpose input cell which features three selectable input modes, three selectable resistive termination options, and a wide supply range. The library’s ODIO is a 5V I2C-compliant ODIO which features standard mode, fast-mode, and fast-mode plus, as well as selectable input modes, drive strength control and robust 2kV HBM protection. The library also supports I3C, SPI and QSPI standards. The library includes all layout and support cells. ESD targets are 2kV HBM and 500V CDM.
This silicon-proven Wirebond compatible library in Dongbu HiTek 110nm features a multi-voltage, multi-standard General Purpose Input Output with an Open-Drain Input Output capability, that targets the I2C standard. The library is built as a Fail- Safe I/O design. There is no poly-orientation for this library. The library features an Analog Mux, which allows for core direct access to the bondpad, either to drive externally a signal or receive a signal from the PAD. The I/O Library is compliant with standards regarding all 1.2V, 1.8V, and 3.3V operation. The library can support various standards, including I3C, I2C, SPI and QSPI. ESD targets are 2kV HMB and 500V CDM.
The STAR1010 is an ultra-low power audio ADC that achieves superior audio rate performance characterized by a 96dBA dynamic range while maintaining a power consumption below 200 microamps. This highly configurable ADC can operate in both over-sampled and Nyquist rate incremental modes, adapting flexibly to varying application requirements. Tested and silicon-proven in a 40-nanometer process, the STAR1010 stands out for its reliability and performance in demanding audio applications.
This I/O Library, developed on GlobalFoundries 55nm CMOS, delivers a complete suite of digital and analog I/O solutions with robust 2 kV HBM / 500 V CDM ESD protection and latch-up immunity. The library includes 1.83.3 V GPIOs supporting GMII and LVCMOS standards, I2C-compliant ODIOs, and flexible analog I/Os (ANA/DANA) with integrated ESD. Complemented by a full set of power, filler, corner, and transition cells, the VZ55 library enables reliable padring construction across mixed-signal designs. With wide voltage support, industrial temperature range (-40C to 125C), and cross-domain ESD protection, VZ55 provides a scalable, production-ready I/O platform for advanced SoC integration.
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