All IPs > Processor > DSP Core
In the realm of semiconductor IP, DSP Cores play a pivotal role in enabling efficient digital signal processing capabilities across a wide range of applications. Short for Digital Signal Processor Cores, these semiconductor IPs are engineered to handle complex mathematical calculations swiftly and accurately, making them ideal for integration into devices requiring intensive signal processing tasks.
DSP Core semiconductor IPs are widely implemented in industries like telecommunications, where they are crucial for modulating and encoding signals in mobile phones and other communication devices. They empower these devices to perform multiple operations simultaneously, including compressing audio, optimizing bandwidth usage, and enhancing data packets for better transmission quality. Additionally, in consumer electronics, DSP Cores are fundamental in audio and video equipment, improving the clarity and quality of sound and visuals users experience.
Moreover, DSP Cores are a linchpin in the design of advanced automotive systems and industrial equipment. In automotive applications, they assist in radar and lidar systems, crucial for autonomous driving features by processing the data needed for real-time environmental assessment. In industrial settings, DSP Cores amplify the performance of control systems by providing precise feedback loops and enhancing overall process automation and efficiency.
Silicon Hub's category for DSP Core semiconductor IPs includes a comprehensive collection of advanced designs tailored to various processing needs. These IPs are designed to integrate seamlessly into a multitude of hardware architectures, offering designers and engineers the flexibility and performance necessary to push the boundaries of technology in their respective fields. Whether for enhancing consumer experiences or driving innovation in industrial and automotive sectors, our DSP Core IPs bring unparalleled processing power to the forefront of digital innovations.
The xcore.ai platform is designed to power the intelligent Internet of Things (IoT) by combining flexibility and performance efficiency. With its distinctive multi-threaded micro-architecture, it allows for low-latency and predictable performance, crucial for IoT applications. Each xcore.ai device is equipped with 16 logical cores distributed over two tiles, each with integrated 512kB SRAM and a vector unit capable of handling both integer and floating-point operations. Communication between processors is facilitated by a robust interprocessor communication infrastructure, enabling scalability for systems requiring multiple xcore.ai SoCs. This platform supports a multitude of applications by integrating DSP, AI, and I/O processing within a cohesive development environment. For audio and voice processing needs, it offers adaptable, software-defined I/O that aligns with specific application requirements, ensuring efficient and targeted performance. The xcore.ai is also equipped for ai and machine learning tasks with a 256-bit VPU that supports various operations including 32-bit, 16-bit, and 8-bit vector operations, offering peak AI performance. The inclusion of a comprehensive development kit allows developers to explore its capabilities through ready-made solutions or custom-built applications.
Jotunn8 represents VSORA's pioneering leap into the world of AI Inference technology, aimed at data centers that require high-speed, cost-efficient, and scalable systems. The Jotunn8 chip is engineered to deliver trained models with unparalleled speed, minimizing latency and optimizing power usage, thereby guaranteeing that high-demand applications such as recommendation systems or large language model APIs operate at optimal efficiency. The Jotunn8 is celebrated for its near-theoretical performance, specifically designed to meet the demands of real-time services like chatbots and fraud detection. With a focus on reducing costs per inference – a critical factor for operating at massive scale – the chip ensures business viability through its power-efficient architecture, which significantly trims operational expenses and reduces carbon footprints. Innovative in its approach, the Jotunn8 supports complex AI computing needs by integrating various AI models seamlessly. It provides the foundation for scalable AI, ensuring that infrastructure can keep pace with growing consumer and business demands, and represents a robust solution that prepares businesses for the future of AI-driven applications.
Leveraging a high-performance RISC architecture, the eSi-3250 32-bit core efficiently integrates instruction and data caches. This makes it compatible with designs utilizing slower on-chip memories such as eFlash. The core not only supports MMU for address translation but also allows for user-defined custom instructions, greatly enhancing its flexibility for specialized and high-performance applications.
The Chimera GPNPU from Quadric stands as a versatile processing unit designed to accelerate machine learning models across a wide range of applications. Uniquely integrating the strengths of neural processing units and digital signal processors, the Chimera GPNPU simplifies heterogeneous workloads by running traditional C++ code and complex AI networks such as large language models and vision transformers in a unified processor architecture. This scalability, tailored from 1 to 864 TOPs, allows it to meet the diverse requirements of markets, including automotive and network edge computing.\n\nA key feature of the Chimera GPNPU is its ability to handle matrix and vector operations alongside scalar control code within a single pipeline. Its fully software-driven nature enables developers to fine-tune model performance over the processor's lifecycle, adapting to evolving AI techniques without needing hardware updates. The system's design minimizes off-chip memory access, thereby enhancing efficiency through its L2 memory management and compiler-driven optimizations.\n\nMoreover, the Chimera GPNPU provides an extensive instruction set, finely tuned for AI inference tasks with intelligent memory management, reducing power consumption and maximizing processing efficiency. Its ability to maintain high performance with deterministic execution across various processes underlines its standing as a leading choice for AI-focused chip design.
The eSi-3200, a 32-bit cacheless core, is tailored for embedded control with its expansive and configurable instruction set. Its capabilities, such as 64-bit multiply-accumulate operations and fixed-point complex multiplications, cater effectively to signal processing tasks like FFTs and FIRs. Additionally, it supports SIMD and single-precision floating point operations, coupled with efficient power management features, enhancing its utility for diverse embedded applications.
The eSi-3264 stands out with its support for both 32/64-bit operations, including 64-bit fixed and floating-point SIMD (Single Instruction Multiple Data) DSP extensions. Engineered for applications mandating DSP functionality, it does so with minimal silicon footprint. Its comprehensive instruction set includes specialized commands for various tasks, bolstering its practicality across multiple sectors.
The SCR3 Microcontroller Core offers a medium-performance solution for embedded applications, featuring a 5-stage in-order pipeline. It supports both 32-bit and 64-bit configurations, providing a versatile platform for various use cases in industrial and automotive systems. Equipped with privilege modes and a memory protection unit (MPU), the SCR3 core emphasizes security and stability, ensuring robust performance in safety-critical environments. Additionally, its L1 and L2 cache support enhances processing speed and data efficiency. Tailored for real-time tasks, this core integrates capabilities that support complex control systems and network devices. Its architecture and toolchain are specifically designed to enable developers to quickly innovate and meet stringent application demands.
The Codasip RISC-V BK Core Series represents a family of processor cores that bring advanced customization to the forefront of embedded designs. These cores are optimized for power and performance, striking a fine balance that suits an array of applications, from sensor controllers in IoT devices to sophisticated automotive systems. Their modular design allows developers to tailor instructions and performance levels directly to their needs, providing a flexible platform that enhances both existing and new applications. Featuring high degrees of configurability, the BK Core Series facilitates designers in achieving superior performance and efficiency. By supporting a broad spectrum of operating requirements, including low-power and high-performance scenarios, these cores stand out in the processor IP marketplace. The series is verified through industry-leading practices, ensuring robust and reliable operation in various application environments. Codasip has made it straightforward to use and adapt the BK Core Series, with an emphasis on simplicity and productivity in customizing processor architecture. This ease of use allows for swift validation and deployment, enabling quicker time to market and reducing costs associated with custom hardware design.
The Digital Radio (GDR) from GIRD Systems is an advanced software-defined radio (SDR) platform that offers extensive flexibility and adaptability. It is characterized by its multi-channel capabilities and high-speed signal processing resources, allowing it to meet a diverse range of system requirements. Built on a core single board module, this radio can be configured for both embedded and standalone operations, supporting a wide frequency range. The GDR can operate with either one or two independent transceivers, with options for full or half duplex configurations. It supports single channel setups as well as multiple-input multiple-output (MIMO) configurations, providing significant adaptability in communication scenarios. This flexibility makes it an ideal choice for systems that require rapid reconfiguration or scalability. Known for its robust construction, the GDR is designed to address challenging signal processing needs in congested environments, making it suitable for a variety of applications. Whether used in defense, communications, or electronic warfare, the GDR's ability to seamlessly switch configurations ensures it meets the evolving demands of modern communications technology.
ISPido represents a fully configurable RTL Image Signal Processing Pipeline, adhering to the AMBA AXI4 standards and tailored through the AXI4-LITE protocol for seamless integration with systems such as RISC-V. This advanced pipeline supports a variety of image processing functions like defective pixel correction, color filter interpolation using the Malvar-Cutler algorithm, and auto-white balance, among others. Designed to handle resolutions up to 7680x7680, ISPido provides compatibility for both 4K and 8K video systems, with support for 8, 10, or 12-bit depth inputs. Each module within this pipeline can be fine-tuned to fit specific requirements, making it a versatile choice for adapting to various imaging needs. The architecture's compatibility with flexible standards ensures robust performance and adaptability in diverse applications, from consumer electronics to professional-grade imaging solutions. Through its compact design, ISPido optimizes area and energy efficiency, providing high-quality image processing while keeping hardware demands low. This makes it suitable for battery-operated devices where power efficiency is crucial, without sacrificing the processing power needed for high-resolution outputs.
The Spiking Neural Processor T1 from Innatera is a groundbreaking microcontroller optimized for ultra-low power always-on sensing applications. Integrating a RISC-V core with an SNN-based processing engine, the T1 operates at sub-milliwatt power levels, enabling advanced signal processing and AI capabilities close to the sensor. This microcontroller effectively offloads sensor data processing, allowing for rapid pattern recognition and efficient power usage in latency-sensitive and power-constrained devices. Key among its features is a nimble 32-bit RISC-V core, supported by 384 KB of embedded SRAM. The innovative spiking neural network engine allows for the real-time inference of complex patterns, mirroring brain-like behavior in processing tasks while keeping power dissipation minimal. Its capabilities facilitate applications such as activity recognition in wearables and high-accuracy signal processing in acoustic sensors. The T1 is packaged in a compact WLCSP form factor and supports diverse interfaces including QSPI, I2C, UART, JTAG, and GPIO, making it adaptable to various sensor configurations. Additionally, developers can leverage the T1 Evaluation Kit and Talamo SDK, which provide a robust platform for developing and optimizing applications harnessing the T1’s unique processing strengths.
The **Ceva-SensPro DSP family** unites scalar processing units and vector processing units under an 8-way VLIW architecture. The family incorporates advanced control features such as a branch target buffer and a loop buffer to speed up execution and reduce power. There are six family members, each with a different array of MACs, targeted at different application areas and performance points. These range from the Ceva-SP100, providing 128 8-bit integer or 32 16-bit integer MACs at 0.2 TOPS performance for compact applications such as vision processing in wearables and mobile devices; to the Ceva-SP1000, with 1024 8-bit or 256 16-bit MACs reaching 2 TOPS for demanding applications such as automotive, robotics, and surveillance. Two of the family members, the Ceva-SPF2 and Ceva-SPF4, employ 32 or 64 32-bit floating-point MACs, respectively, for applications in electric-vehicle power-train control and battery management. These two members are supported by libraries for Eigen Linear Algebra, MATLAB vector operations, and the TVM graph compiler. Highly configurable, the vector processing units in all family members can add domain-specific instructions for such areas as vision processing, Radar, or simultaneous localization and mapping (SLAM) for robotics. Integer family members can also add optional floating-point capabilities. All family members have independent instruction and data memory subsystems and a Ceva-Connect queue manager for AXI-attached accelerators or coprocessors. The Ceva-SensPro2 family is programmable in C/C++ as well as in Halide and Open MP, and supported by an Eclipse-based development environment, extensive libraries spanning a wide range of applications, and the Ceva-NeuPro Studio AI development environment. [**Learn more about Ceva-SensPro2 solution>**](https://www.ceva-ip.com/product/ceva-senspro2/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_senspro2_page)
The Tyr AI Processor series by VSORA is revolutionizing Edge AI by bringing real-time intelligence and decision-making power directly to edge devices. This family of processors delivers the compute power equivalent to data centers but in a compact, energy-efficient form factor ideal for edge environments. Tyr processors are specifically designed to process data on the device itself, reducing latency, preserving bandwidth, and maintaining data privacy without the need for cloud reliance. This localized processing translates to split-second analytics and decision capabilities critical for technologies like autonomous vehicles and industrial automation. With Tyr, industries can achieve superior performance while minimizing operational costs and energy consumption, fostering greener AI deployments. The processors’ design accommodates the demanding requirements of modern edge applications, ensuring they can support the evolving needs of future edge intelligence systems.
The iCan PicoPop® System on Module offers a compact solution for high-performance computing in constrained environments, particularly in the realm of aerospace technology. This system on module is designed to deliver robust computing power while maintaining minimal space usage, offering an excellent ratio of performance to size. The PicoPop® excels in integrating a variety of functions onto a single module, including processing, memory, and interface capabilities, which collectively handle the demanding requirements of aerospace applications. Its efficient power consumption and powerful processing capability make it ideally suited to a range of in-flight applications and systems. This solution is tailored to support the development of sophisticated aviation systems, ensuring scalability and flexibility in deployment. With its advanced features and compact form, the iCan PicoPop® System on Module stands out as a potent component for modern aerospace challenges.
ISPido on VIP Board is a customized runtime solution tailored for Lattice Semiconductors’ Video Interface Platform (VIP) board. This setup enables real-time image processing and provides flexibility for both automated configuration and manual control through a menu interface. Users can adjust settings via histogram readings, select gamma tables, and apply convolutional filters to achieve optimal image quality. Equipped with key components like the CrossLink VIP input bridge board and ECP5 VIP Processor with ECP5-85 FPGA, this solution supports dual image sensors to produce a 1920x1080p HDMI output. The platform enables dynamic runtime calibration, providing users with interface options for active parameter adjustments, ensuring that image settings are fine-tuned for various applications. This system is particularly advantageous for developers and engineers looking to integrate sophisticated image processing capabilities into their devices. Its runtime flexibility and comprehensive set of features make it a valuable tool for prototyping and deploying scalable imaging solutions.
The SCR4 Microcontroller Core provides enhanced computational capability in a 32/64-bit architecture, equipped with a 5-stage in-order pipeline. Designed for embedded systems, it features integrated floating-point unit (FPU) and memory protection unit (MPU) for increased precision and reliability. Supporting multicore configurations, this core is adept at handling sophisticated industrial and IoT applications. Its cache hierarchy, comprising L1 and L2 caches, enhances data handling efficiency, crucial for time-sensitive processing tasks. The SCR4 core's SystemVerilog-configured design, coupled with a complete development toolkit and FPGA SDK, ensures that developers have the resources necessary for expedited development and deployment. This core balances advanced functionality with efficient power use, making it a prime choice for demanding embedded applications.
The Secure Protocol Engines offer high-performance IP modules focused on efficient network and security processing. These engines are critical for applications requiring strict adherence to security protocols while managing data flow in a secure manner. By offloading the processing burden from host processors, these engines optimize throughput and maintain secure data transmission across various digital communication infrastructures. These engines support a wide array of protocols and are designed to integrate seamlessly into System-on-Chip environments, whether using FPGA or ASIC implementations. Their architecture prioritizes speed, security, and reliability—key components needed to meet the demanding standards of modern communications networks. By employing advanced cryptographic routines and stringent protocol compliance measures, Secure Protocol Engines facilitate secure interactions between network components. This enables businesses to enhance their security posture without compromising on performance, providing a resilient solution that scales with evolving network demands.
The Universal Drive Controller by Enclustra is an IP core designed for comprehensive motion control, managing up to eight drives per controller. Suitable for DC, BLDC, and stepper motors, it integrates position control, field-oriented control, and trajectory planning within a single FPGA, eliminating the need for separate drive control chips. This reduces both PCB space and overall system costs. Optimized for integration in FPGA systems, the controller offers robust error handling and customizability, making it ideal for applications requiring precise motor control.
Enclustra's Universal DSP Library, integrated with the AMD Vivado ML Design Suite, offers efficient FPGA implementations of key digital signal processing components. This library minimizes development time by providing components in raw VHDL and as Vivado IPI blocks, allowing easy DSP chain construction through a graphical interface or direct VHDL coding. The library includes components like FIR filters, mixers, and CORDIC function approximations, with a focus on ease of integration and comprehensive documentation. It supports operations on multiple data channels and real/complex signals using standardized AXI4-Stream protocol interfaces.
The Calibrator for AI-on-Chips utilizes sophisticated post-training quantization techniques to ensure high accuracy and precision in AI models deployed on heterogeneous multicore SoCs. By employing architecture-aware quantization, it maintains accuracy even when switching to fixed-point architectures such as INT8, crucial for reducing computational load and energy consumption on embedded systems. The calibrator leverages comprehensive entropy calculating methods, including KLD, L1, and L2, to optimize precision drops, commonly keeping them under 1% for well-defined microarchitectures. This tool provides seamless interoperability with popular AI frameworks, such as ONNX and TensorFlow, enhancing compatibility and ensuring a wide range of applications can benefit from precision enhancements. Designed to be flexible, the calibrator supports mixed precision across multiple engines and chip architectures, delivering effective solutions in both standalone applications and as part of a broader compiler optimization pass. This versatility ensures it can effectively address the unique constraints of various hardware platforms, including CIM and analog computing architectures.
The Codasip L-Series DSP Core offers specialized features tailored for digital signal processing applications. It is designed to efficiently handle high data throughput and complex algorithms, making it ideal for applications in telecommunications, multimedia processing, and advanced consumer electronics. With its high configurability, the L-Series can be customized to optimize processing power, ensuring that specific application needs are met with precision. One of the key advantages of this core is its ability to be finely tuned to deliver optimal performance for signal processing tasks. This includes configurable instruction sets that align precisely with the unique requirements of DSP applications. The core’s design ensures it can deliver top-tier performance while maintaining energy efficiency, which is critical for devices that operate in power-sensitive environments. The L-Series DSP Core is built on Codasip's proven processor design methodologies, integrating seamlessly into existing systems while providing a platform for developers to expand and innovate. By offering tools for easy customization within defined parameters, Codasip ensures that users can achieve the best possible outcomes for their DSP needs efficiently and swiftly.
The Satellite Navigation SoC Integration solution offers a seamless method to embed satellite navigation capabilities within a System on Chip (SoC). This solution effectively integrates GPS, GLONASS, SBAS, and Galileo channels, along with independent fast search engines for each navigation system, enabling a robust and comprehensive navigation system. Because of its silicon-verified nature and VHDL library-based design, it ensures ease of integration and compatibility with various platforms. Notably, this IP was among the first to be integrated with open hardware architecture such as RISC-V, bolstering its adaptability and performance. The navigation IP features advanced signal processing capabilities that are platform independent, supporting a high update rate that can reach up to 1000 Hz. This high performance is complemented by a user-friendly API, making it accessible for developers to implement in various applications. Its versatility is further demonstrated through the support of a wide range of communication protocols and its ability to work seamlessly with other software services like OpenStreetMaps. This solution is optimal for developers looking to enhance their SoC with precise and reliable satellite navigation functionalities. It is particularly beneficial in modern applications requiring high accuracy and reliability, offering comprehensive features that facilitate a range of applications beyond traditional GPS functions. The integration of this technology enables devices to perform at unprecedented levels of efficiency and accuracy in location-based applications.
Designed to cater to the needs of edge computing, the Neural Network Accelerator by Gyrus AI is a powerhouse of performance and efficiency. With a focus on graph processing capabilities, this product excels in implementing neural networks by providing native graph processing. The accelerator attains impressive speeds, achieving 30 TOPS/W, while offering efficient computational power with significantly reduced clock cycles, ranging between 10 to 30 times less compared to traditional models. The design ensures that power consumption is kept at a minimum, being 10-20 times lower due to its low memory usage configuration. Beyond its power efficiency, this accelerator is designed to maximize space with a smaller die area, ensuring an 8-10 times reduction in size while maintaining high utilization rates of over 80% for various model structures. Such design optimizations make it an ideal choice for applications requiring a compact, high-performance solution capable of delivering fast computations without compromising on energy efficiency. The Neural Network Accelerator is a testament to Gyrus AI's commitment to enabling smarter edge computing solutions. Additionally, Gyrus AI has paired this technology with software tools that facilitate the execution of neural networks on the IP, simplifying integration and use in various applications. This seamless integration is part of their broader strategy to augment human intelligence, providing solutions that enhance and expand the capabilities of AI-driven technologies across industries.
The AON1100 is a leading AI chip built for efficient voice and sensor processing tasks, offering exceptional performance with under 260μW power usage. It achieves a 90% accuracy level even in sub-zero decibel noise environments. Ideal for devices that require continuous sensory input without significant power drain, it is designed to function seamlessly in demanding acoustic environments, optimizing both performance and power.
TUNGA is an advanced System on Chip (SoC) leveraging the strengths of Posit arithmetic for accelerated High-Performance Computing (HPC) and Artificial Intelligence (AI) tasks. The TUNGA SoC integrates multiple CRISP-cores, employing Posit as a core technology for real-number calculations. This multi-core RISC-V SoC is uniquely equipped with a fixed-point accumulator known as QUIRE, which allows for extremely precise computations across vectors as long as 2 billion entries. The TUNGA SoC includes programmable FPGA gates for enhancing field-critical functions. These gates are instrumental in speeding up data center services, offloading tasks from the CPU, and advancing AI training and inference efficiency using non-standard data types. TUNGA's architecture is tailored for applications demanding high precision, including cryptography and variable precision computing tasks, facilitating the transition towards next-generation arithmetic. In the computational ecology, TUNGA stands out by offering customizable features and rapid processing capabilities, making it suitable not only for typical data center functions but also for complex, precision-demanding workloads. By capitalizing on Posit arithmetic, TUNGA aims to deliver more efficient and powerful computational performance, reflecting a strategic advancement in handling complex data-oriented processes.
The Cottonpicken DSP Engine offered by section5 is a powerful digital signal processing solution designed for versatile applications. This engine performs advanced functions like Bayer pattern decoding into multiple formats, supporting conversions such as YUV 4:2:2, YUV 4:2:0, and RGB. It is proficient in executing matrix operations and supports customizable filter kernels, making it ideal for complex imaging tasks. Engineered to run at high pixel clock speeds of up to 150 MHz, its performance is adaptable to platform-specific requirements. This DSP engine is built as a closed-source netlist object, emphasizing its specialized nature in the marketplace. It features programmable delays and supports various conversion schemes, offering flexibility to meet diverse processing needs. Its robust architecture ensures that it can handle operations at the full data clock rate, further enhancing its suitability for high-throughput environments. Section5's Cottonpicken DSP Engine is specifically tailored to integrate seamlessly into existing systems, catering primarily to developers seeking specialized DSP capabilities. Its closed-source nature implies a focus on secure and optimized deployment, aligning well with commercial entities that value proprietary technologies that are shielded from open-source exposure.
The NoISA Processor by Hotwright Inc. stands out because it eliminates the rigidity of conventional Instruction Set Architectures (ISA) by leveraging the Hotstate machine's microcoded state machine. This architecture alleviates the drawbacks of fixed hardware controllers by allowing unprecedented flexibility in modifying how processor tasks are executed. As an alternative to softcore CPUs, the NoISA Processor delivers superior energy efficiency, making it an ideal choice for applications where power is a critical constraint. This makes it particularly well-suited for edge computing and Internet of Things (IoT) devices, where low power usage is paramount. By discarding traditional ISA constraints, the NoISA Processor can dynamically change its functions just by reloading microcode, as opposed to relying on smaller, immutable instructions typical in ISA-bound processors. This flexibility enables it to act as a highly effective controller, adaptable to various tasks without necessitating changes to the dedicated hardware such as FPGAs. Through this adaptability, the NoISA Processor offers performance benefits not typically available with fixed-instruction processors, allowing developers to achieve optimal efficiency and capability in their computing solutions. Furthermore, the NoISA Processor supports the creation of efficient, small controllers and C programmable state machines, capitalizing on faster systolic arrays and ensuring rapid development cycles. It allows for modifications and improvements in device functionality without altering the underlying hardware, ensuring future-proof solutions by catering to evolving technology demands with ease.
The TSP1 Neural Network Accelerator is a state-of-the-art AI chip designed for versatile applications across various industries, including voice interfaces, biomedical monitoring, and industrial IoT. Engineered for efficiency, the TSP1 handles complex workloads with minimal power usage, making it ideal for battery-powered devices. This AI chip is capable of advanced bio-signal classification and natural voice interface integration, providing self-contained processing for numerous sensor signal applications. A notable feature is its high-efficiency neural network processing element fabric, which empowers signal pattern recognition and other neural network tasks, thereby reducing power, cost, and latency. The TSP1 supports powerful AI inference processes with low latency, enabling real-time applications like full vocabulary speech recognition and keyword spotting with minimal energy consumption. It's equipped with multiple interfaces for seamless integration and offers robust on-chip storage for secure network and firmware management. The chip is available in various packaging options to suit different application requirements.
Designed for both voice recognition and sensor applications, the AON1020 integrates the AONSens Neural Network cores. It features capabilities such as multi-wake-word detection, context awareness, and sensor applications including human activity detection. Delivered in Verilog RTL, it is well-suited for ASIC and FPGA implementations, providing exceptionally low-power operation ideal for always-on listening scenarios. It delivers highly accurate performance amid noisy conditions, making it a comprehensive solution for various sensor-driven applications.
The Domain-Specific RISC-V Cores from Bluespec are engineered to facilitate hardware acceleration in a streamlined and efficient manner. By packaging accelerators as software threads, these cores deliver high concurrency and efficient system performance. The scalability embedded in this technology caters to a range of application needs, enabling systematic hardware acceleration for developers and organizations aiming to optimize RISC-V implementations.
The "Origin E8" stands out in handling intense computational tasks, addressing the needs of automotive, ADAS systems, and data centers with its robust processing capabilities. It offers exceptional performance, scaling to an impressive 128 TOPS per core, perfectly meeting the demands of modern complex AI tasks, including real-time analytics and intricate neural network applications. Expedera's packet-based architecture optimizes the E8 to bypass typical architectural constraints, maximizing throughput and reducing latencies. This NPU is built to execute multiple networks concurrently with efficiency, making it a crucial component in systems requiring rapid data processing and high operational agility.
The RFicient chip is an innovative solution developed by Fraunhofer IIS, aimed at advancing the Internet of Things (IoT) connectivity. Designed with efficiency in mind, this chip enables significant power savings, reducing consumption by 99% compared to traditional systems. This allows for prolonged operation of IoT devices without frequent recharging or battery replacement, making it ideal for remote and hard-to-reach locations where power sources are scarce. The chip excels in facilitating robust communication within the IoT ecosystem, handling extensive data transfer from numerous devices seamlessly. It supports various IoT applications by enabling reliable data transmission over long distances, ensuring devices remain interconnected without interruption. Additionally, the chip's design allows it to operate effectively even in energy-scarce environments, aligning with rising demands for sustainable technology that supports the global shift towards greener practices. Technical advancements in the RFicient chip underline its competitive edge in IoT applications. Not only does it contribute to the reduction of carbon footprints by prolonging device operational times, but it also opens new fronts for IoT deployment in areas previously constrained by energy limitations. By integrating this chip, businesses and service providers can boost their IoT infrastructure's resilience and adaptability, ensuring continuous service delivery and operational efficiency.
The Prodigy Universal Processor by Tachyum is a groundbreaking chip regarded as the smallest, fastest, and most eco-friendly general-purpose chip available. Notably, it is capable of significantly lowering data center power consumption, thereby reducing carbon emissions and helping to combat climate change. This processor excels in applications such as hyperscale data centers, private cloud environments, and AI/high-performance computing. It offers seamless operation for existing applications without requiring modifications, further enhancing its appeal by offering substantial energy savings and cost efficiency. The architecture of the Prodigy Universal Processor integrates various computational resources, including CPUs, GPGPUs, and TPUs. This enables a comprehensive solution that addresses performance, energy consumption, and spatial efficiency in an ever-demanding computational landscape. Its design allows for a straightforward programming model that can effectively manage extensive AI workloads, bioinformatics processing, and a multitude of AI disciplines on a single chip. Beyond technical prowess, this processor brings a new level of performance with a focus on reducing operational costs for data centers. By drastically lowering power requirements while ensuring top-tier computational performance, it supports broader environmental sustainability goals, positioning itself as a leader in the fight against increasing global energy demands. Prodigy's unique capabilities also allow it to replace multiple traditional processors with one, offering a universal solution for varied computing needs.
The AON1000 is a cutting-edge AI processing engine that excels in wake word detection, voice commands, acoustic event detection, and speaker identification, specifically designed for low-power, high-accuracy operations. It boasts superior performance in noisy surroundings by using proprietary neural network architectures and inference algorithms. This IP can be deployed within standalone chips or integrated into sensors like microphones. Its ultra-low power design allows other processors to remain in idle mode during always-on listening states, optimizing power consumption without compromising accuracy.
The Blazar Bandwidth Accelerator Engine serves as a pivotal component for boosting FPGA applications. This engine is specifically engineered to enhance in-memory compute capabilities, thus enabling high-bandwidth activities with reduced latency. Each Blazar device integrates in-memory computation, facilitating operations at unprecedented speeds required for modern high-demand applications.\n\nWith features such as 640 Gbps bandwidth and support for dual-port memory, the Blazar Engine is apt for applications that require mass data processing at a rapid pace. Moreover, the optional inclusion of 32 RISC cores amplifies its computational capacity, making it exceptionally versatile for tasks such as SmartNIC and SmartSwitch metering. These engines are indispensable for environments where efficient data aggregation and processing are crucial, such as in network infrastructure and communication systems.\n\nThe Blazar Engine's architecture not only supports vast read/write operations but also enhances system efficiency by minimizing the external commands required for memory operations. This reduces the overall load on FPGA resources, thereby streamlining processes and accelerating time-to-market for new technologies. Its design speaks to the needs of cutting-edge 5G and Next-Gen communication systems that strive for high throughput at lower capital investment.
The ARC Processor from Synopsys represents a powerhouse of processing capabilities, optimized for embedded system designs requiring high performance and energy efficiency. Tailored for applications across consumer electronics and IoT devices, ARC processors offer custom extensibility making them adaptable to specific computational workloads. These processors boast configurable architectures, allowing designers to fine-tune performance to achieve optimal balance between speed and power consumption. They are supported by a wide ecosystem of development tools and third-party partnerships, which provide scalability and versatility for innovative applications. The ARC Processor stands out for its power-to-performance ratio, enabling complex processing tasks without significant energy penalties. Comprehensive support and resources from Synopsys ensure that developers can maximize processor capabilities, achieve faster launches, and maintain product quality in competitive markets.
The hypr_risc, offered by NOVELIC, stands as an advanced radar DSP accelerator specifically designed to augment radar signal processing capabilities. This device integrates a custom RISC-V processor core with a high-speed dedicated radar accelerator, providing an optimal balance of performance, power consumption, and size. This ensures its effectiveness across a range of uses, from compact low-power chips to expansive, high-performance applications. hypr_risc excels in computational tasks like 2D Fast Fourier Transforms (FFTs), indispensable in automotive systems requiring rapid data processing and response, such as advanced driver-assistance systems (ADAS). The device is also highly configurable, allowing for fine-tuning to meet specific project requirements. Utilizing a satellite architecture, the hypr_risc adapts to various RF frontends, allowing seamless integration irrespective of the manufacturer. The versatility of hypr_risc makes it a valuable asset in developing cutting-edge radar solutions, enhancing the speed and accuracy of radar data interpretation and thereby supporting the ongoing development of automotive and industrial innovation.
Our Specialty Microcontrollers are built upon modern RISC-V architecture, integrating advanced coprocessors to enable high-level computational tasks. These microcontrollers are specifically designed for executing complex image processing algorithms efficiently, while maintaining performance and reducing power consumption. These microcontrollers have embedded machine learning algorithms suited for touch applications. They are versatile enough to process various levels of user input, from simple commands to detailed user interfaces. This capacity allows for the creation of inventive and interactive interfaces that enhance the overall user experience. Our microcontrollers, available in SoC or multi-chip configurations, serve different touchscreen sizes and are equipped with features like integrated capacitive AFE interfaces and power management units. This makes them an optimal choice for touch-based interfaces, ensuring smooth operation over both large and small interactive displays.
The Prodigy FPGA-Based Emulator offers an advanced platform for evaluating and developing Tachyum's universal processor capabilities. This emulation system is not only essential for rigorous performance testing but also for software development, debugging, and compatibility verification. The emulator consists of multiple FPGA and IO boards connected systematically, enabling it to replicate functionalities of the Prodigy chip effectively. The primary advantage of using the Prodigy FPGA-Based Emulator lies in its ability to offer a high-fidelity representation of the Prodigy processor, making it ideal for developers aiming to transition and optimize their software for this new architecture. It supports real-time testing, allowing developers to evaluate their applications within a controlled environment that mirrors final deployment scenarios. Moreover, this emulator provides a critical advantage by enabling seamless transition of existing applications through testing and verification phases without the need for immediate hardware deployment. As such, it becomes a vital tool for those seeking to leverage Tachyum's processing power while minimizing transition risks and maximizing performance outcomes.
The Trifecta-GPU series presents an extensive range of COTS PXIe/CPCIe GPU modules designed to bring extreme compute acceleration and simplified programming to T&M and Electronic Warfare applications. Based on NVIDIA's RTX A2000 Embedded GPUs, the Trifecta-GPU delivers up to 8.3 FP32 TFLOPS of peak compute performance. It is equipped with 8GB of GDDR6 DRAM and supports PCIe Express 4.0. This makes the Trifecta-GPU a perfect match for the demanding Signal Processing, Machine Learning, and Deep Learning inference applications in PXIe/CPCIe systems, offering new levels of performance and capability. By supporting various programming frameworks such as MATLAB, Python, and C/C++, and providing broad compatibility with popular computing frameworks, Trifecta-GPUs integrate seamlessly into both Windows and Linux environments. The GPUs cater to graphics-intensive applications, boost signal analysis, and enhance ML and DL for AI-based operations like signal classification and geolocation. Much more than just a hardware solution, the Trifecta-GPU sets a new benchmark in the price-performance ratio by offering unmatched FP32 GFLOPS per dollar. With flexible power configurations, including single and dual-slot variants, it adapts to a range of PXIe and CPCIe chassis configurations, ensuring optimal deployment and future-proofing against evolving computational demands.
The "Origin E2" NPU core is designed for edge devices, providing a balanced approach to AI inference by combining efficiency and performance. Targeted at smartphones, smart devices, and edge nodes, the E2 specializes in power-optimized processing with a focus on handling complex AI tasks efficiently. Supporting a range from 1 to 20 TOPS, it is versatile enough to suit various applications, from video analytics to signal processing. Expedera's packet-based design allows parallel layer execution, maximizing resource use while minimizing power drains and latency. The E2 integrates various neural network technologies including CNNs, RNNs, and LSTMs, all while maintaining exceptional performance in terms of processor utilization, making it ideal for many consumer and industrial applications.
"Origin E6" NPU is tailored for applications requiring both cutting-edge performance and power efficiency. With a capability ranging from 16 to 32 TOPS, it serves high-demand sectors like smartphone applications, augmented and virtual reality systems, and beyond. The E6 utilizes a packet-based architecture, significantly outpacing typical layer-focused designs by facilitating unmatched execution parallelism and resource use. Engineered for low latency and energy consumption, the E6 supports extensive AI workloads, from video processing to text and audio applications, providing scalable solutions for modern and future technologies. This makes the E6 ideal for industries striving for superior AI performance while prioritizing efficiency and space.
The TimeServo System Timer is an FPGA-based timer IP core that offers sub-nanosecond resolution and sub-microsecond accuracy. It is chiefly designed for high-resolution packet timestamping within FPGAs but finds numerous applications where precise timebases are required. Utilizing a PI-DPLL, it achieves syntonicity with a local TCXO disciplined by an external pulse-per-second input.
The Catalyst-GPU range offers NVIDIA-based, cost-effective PXIe/CPCIe modules that deliver advanced graphics and compute acceleration for signal processing and ML/DL applications. Catalyst-GPUs support the Quadro T600 and T1000 GPUs, providing high-performance capabilities onto the PXIe/CPCIe platforms widely utilized in growing areas such as Modular Test & Measurement and Electronic Warfare. These GPUs offer unmatched computational performance, especially where data is acquired, by performing fast and accurate data analysis directly within the system. Supporting extensive programming frameworks such as MATLAB, Python, and C/C++, Catalyst-GPUs facilitate the straightforward integration of GPU acceleration into existing workflows, benefiting users across Windows and Linux environments. With multi-teraflop performance, the Catalyst-GPU units excel in tasks requiring substantial computational power, such as Machine and Deep Learning inferencing. Equipped with features enabling enhanced accuracy and resolution bandwidths, it ensures a higher level of performance previously unattainable in non-GPU systems, allowing for more detailed signal processing and analysis.
The AON1010 is part of the AONVoice Neural Network family, tailored for processing audio data for voice and sound recognition. This IP is delivered as Verilog RTL and is suitable for synthesis in ASIC and FPGA products. It features capabilities such as multi-wake-word detection, on-device voice command recognition, and speaker identification all while operating on minimal power. This product provides robust performance in variable environments and high background noise, ensuring high accuracy and scalability for recognizing multiple commands.
The Low Power ARM AV Player by Atria Logic is tailored for efficient multimedia processing in industrial and consumer electronics applications. With a focus on low power consumption, it is implemented using the Xilinx Zynq 7010 architecture, fully utilizing ARM Cortex-A9 cores to provide robust AV decoding capabilities. The AV Player integrates an H.264 HD decoder, AAC-LC stereo decoder, and features a GUI for comprehensive playback control. Its versatility allows it to support digital signage, remote monitoring, and infotainment systems, excelling in environments where cost and power are critical considerations.
The v-MP6000UDX Visual Processing Unit embodies a cutting-edge architecture primarily developed to efficiently support deep learning, computer vision, and multimedia processing tasks. This versatile unit is capable of running complex neural networks and advanced video coding concurrently, all within a reduced power envelope. Engineered to enhance system capabilities, it seamlessly integrates various processing tasks on a unified framework that minimizes data movement and power usage. The v-MP6000UDX is engineered to support state-of-the-art AI tasks, providing users with a comprehensive suite of tools to develop, deploy, and optimize applications effectively. Its scalable design ensures it can meet diverse application requirements while controlling costs. The platform’s support of rich multimedia capabilities makes it particularly effective for applications in automotive, mobile, and edge-computing environments. By providing high throughput and flexible configurations, the v-MP6000UDX supports sophisticated vision processing and deep learning functionalities, setting a new bar for performance in visual computing applications.
An enhancement of the AON1100, the AON1120 expands the capabilities with improved I/O and RISC-V support, optimizing it for smart homes and automotive uses. Retaining low power consumption and high accuracy, this chip enhances functionality for sophisticated edge processing in various environments.
The xcore-200 series is engineered for IoT environments, offering a versatile and cost-effective platform for high-performance computation and control. This series caters to various needs with its flexible integration of USB interfaces, gigabit Ethernet, and flash memory options, supporting a wide range of applications. Working as a programmable platform, xcore-200 allows for unique product differentiation with customizable interfaces and features. It guarantees high-speed processing, low-latency response, and the versatility sought by modern IoT applications. Unlike traditional microcontrollers, xcore-200 provides complete timing accuracy and adds enhancing hardware elements aligned with an accessible solution. Among its product classifications, the XU series focuses on USB interfaces, while the XE series provides Ethernet capabilities and the XL series emphasizes flash memory options. Each class maintains performance scalability, with logical cores ranging from 8 to 32, backed by dual-issue processors to maximize peak computational performance and a dedicated high-speed network for core communications.
Focused on enhancing image clarity and processing efficiency, this core supports a wide range of real-time image processing applications. Ideal for environments demanding high-resolution and rapid image handling capabilities, its performance is boosted by FPGA acceleration technology. This enables faster and more accurate image computation and analysis processes, essential in sectors like photography, medical imaging, and surveillance.
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