All IPs > Multimedia > JPEG
JPEG semiconductor IPs form the backbone of a variety of multimedia applications, making them essential for efficient image compression and processing across different platforms. These IPs offer high-performance solutions for encoding and decoding JPEG images, which is crucial for maintaining image quality while reducing file sizes.
In today's digital age, where multimedia content is pervasive, the need for effective image compression technologies is greater than ever. JPEG semiconductor IPs serve this need by providing robust algorithms that can handle complex image data with precision and speed. These IPs are integral to the functionality of digital cameras, smartphones, and other devices that manage and display high volumes of images. By incorporating JPEG IPs, manufacturers can ensure that their devices deliver superior image quality without compromising on storage or transmission efficiency.
In the category of JPEG semiconductor IPs, you'll find a variety of solutions tailored to different application needs. Whether it's for high-end consumer electronics or industrial imaging solutions, these IPs are designed to cater to diverse requirements, offering a balance of performance, power consumption, and area efficiency. Additionally, the flexibility of these IPs allows them to be integrated into a range of systems, offering scalability and adaptability for developers.
These semiconductor IPs play a crucial role in the multimedia ecosystem, supporting the seamless exchange of visual data across multiple devices and networks. As the demand for high-resolution images continues to rise, JPEG IPs will remain a vital component, evolving alongside new technological advancements to meet the challenges of modern multimedia applications.
The KL730 is a third-generation AI chip that integrates advanced reconfigurable NPU architecture, delivering up to 8 TOPS of computing power. This cutting-edge technology enhances computational efficiency across a range of applications, including CNN and transformer networks, while minimizing DDR bandwidth requirements. The KL730 also boasts enhanced video processing capabilities, supporting 4K 60FPS outputs. With expertise spanning over a decade in ISP technology, the KL730 stands out with its noise reduction, wide dynamic range, fisheye correction, and low-light imaging performance. It caters to markets like intelligent security, autonomous vehicles, video conferencing, and industrial camera systems, among others.
Overview: The Camera ISP IP is an Image Signal Processing (ISP) IP developed for low-light environments in surveillance and automotive applications, supporting a maximum processing resolution of 13 Mega or 8Mega Pixels (MP) at 60 frames per second (FPS). It offers a configurable ISP pipeline with features such as 18x18 2D/8x6 2D Color Shading Correction, 19-Point Bayer Gamma Correction, Region Color Saturation, Hue, and Delta L Control functions. The ISP IP enhances image quality with optimal low-light Noise/Sharp filters and offers benefits such as low gate size and memory usage through algorithm optimization. The IP is also ARM® AMBA 3 AXI protocol compliant for easy control via an AMBA 3 APB bus interface. Specifications: Maximum Resolution: o Image: 13MP/8MP o Video: 13MP @ 60fps / 8MP @ 60fps Input Formats: Bayer-8, 10, 12, 14 bits Output Formats: o DVP: YUV422, YUV444, RGB888 - 8, 10, 12 bits o AXI: YUV422, YUV444, YUV420, RGB888 - 8, 10, 12 bits Interface: o ARM® AMBA APB BUS interface for ISP system control o ARM® AMBA AXI interface for data o Direct connection to sensor stream data (DVP) o Features: Defective Pixel Correction: On-The-Fly Defective Pixel Correction 14-Bit Bayer Channel Gain Support: Up to x4 / x7.99 with Linear Algebra for Input Pixel Level Adjustment Gb/Gr Unbalance Correction: Maximum Correction Tolerance Gb/Gr Rate of 12.5% 2D Lens-Shading Correction: Supports 18x18 / 8x6 with Normal R/Gb/Gr/B Channel Shading Correction and Color Stain Correction High-Resolution RGB Interpolation: Utilizes ES/Hue-Med/Average/Non-Directional Based Hybrid Type Algorithm Color Correction Matrix: 3x3 Matrix Bayer Gamma Correction: 19 points RGB Gamma Correction: 19 points Color Enhancement: Hue/Sat/∆-L Control for R/G/B/C/M/Y Channels High-Performance Noise Reduction: For Bayer/RGB/YC Domain Noise Reduction High-Resolution Sharpness Control: Multi-Sharp Filter with Individual Sharp Gain Control Auto Exposure: Utilizes 16x16 Luminance Weight Window & Pixel Weighting Auto White Balance: Based on R/G/B Feed-Forward Method Auto Focus: 2-Type 6-Region AF Value Return
Altek's AI Camera Module integrates sophisticated imaging technology with artificial intelligence, providing a powerful solution for high-definition visual capture and AI-based image processing. This module is tailored for applications where high precision and advanced analytic capabilities are required, such as in security systems and automotive technology. The module is equipped with a broad range of functionalities, including facial recognition, motion detection, and edge computing. It harnesses AI to process images in real-time, delivering insights and analytics that support decision-making processes in various environments. By combining AI with its imaging sensors, Altek enables next-generation visual applications that require minimal human intervention. Altek's AI Camera Module stands out for its high-degree of integration with IoT networks, allowing for seamless connectivity across devices. Its adaptability to different environments and conditions makes it a highly versatile tool. The module's design ensures durability and reliability, maintaining performance even under challenging conditions, thereby ensuring consistent and accurate image capture and processing.
xcore.ai is a versatile and powerful processing platform designed for AIoT applications, delivering a balance of high performance and low power consumption. Crafted to bring AI processing capabilities to the edge, it integrates embedded AI, DSP, and advanced I/O functionalities, enabling quick and effective solutions for a variety of use cases. What sets xcore.ai apart is its cycle-accurate programmability and low-latency control, which improve the responsiveness and precision of the applications in which it is deployed. Tailored for smart environments, xcore.ai ensures robust and flexible computing power, suitable for consumer, industrial, and automotive markets. xcore.ai supports a wide range of functionalities, including voice and audio processing, making it ideal for developing smart interfaces such as voice-controlled devices. It also provides a framework for implementing complex algorithms and third-party applications, positioning it as a scalable solution for the growing demands of the connected world.
The Hyperspectral Imaging System developed by Imec is a revolutionary tool for capturing and analyzing light across a wide range of wavelengths. This system is particularly valuable for applications requiring detailed spectral analysis, such as agricultural inspection, environmental monitoring, and medical diagnostics. By capturing hundreds of narrow spectral bands, the system provides a comprehensive spectral profile of the subject, enabling precise identification of materials and substances. What sets Imec's Hyperspectral Imaging System apart is its ability to integrate seamlessly into existing devices, allowing for versatile use across various industries. The compact and efficient design ensures that it can be deployed in field conditions, offering real-time analysis capabilities that are crucial for immediate decision-making processes. The Hyperspectral Imaging System is designed with cutting-edge CMOS technology, ensuring high sensitivity and accuracy. This integration with CMOS technology not only enhances the performance but also ensures that the system is cost-effective and accessible to a broader range of applications and markets. As hyperspectral imaging continues to evolve, Imec's system stands as a leader in the field, providing unmatched resolution and reliability.
The DSC Decoder by Trilinear Technologies delivers high-performance video compression capabilities for applications demanding real-time display stream processing. Encapsulated in robust silicon-proven IP, the decoder supports Display Stream Compression (DSC) standards, allowing for efficient compression and decompression of high-definition video streams. This ensures seamless video quality while optimizing the use of data transmission channels and saving bandwidth. A vital component of modern multimedia systems, the DSC Decoder is particularly valuable in industries where image quality and transmission efficiency are critical, such as in broadcasting, telecommunications, and advanced surveillance systems. By implementing industry-standard interfaces for configuration and operation, the decoder achieves smooth interoperability with a wide range of host systems and devices, simplifying its integration into existing digital infrastructures. Trilinear Technologies' DSC Decoder is optimized for low power consumption without sacrificing performance. This focus on energy efficiency makes it ideal for portable and battery-powered devices that demand prolonged operational times without frequent recharging. Its real-time decoding capability ensures that even high-definition streams up to 16K can be managed effectively, providing high-detail video output in a variety of formats and resolutions. The integration of the DSC Decoder is facilitated by detailed support documentation and software stacks that make it easier for developers to incorporate the IP into systems with varied architectural foundations. Whether deployed in consumer electronics or professional AV installations, this decoder ensures high-quality video output with reduced latency, meeting the demands of modern digital workflows and multimedia needs.
The CTAccel Image Processor on Intel Agilex FPGA is designed to handle high-performance image processing by capitalizing on the robust capabilities of Intel's Agilex FPGAs. These FPGAs, leveraging the 10 nm SuperFin process technology, are ideal for applications demanding high performance, power efficiency, and compact sizes. Featuring advanced DSP blocks and high-speed transceivers, this IP thrives in accelerating image processing tasks that are typically computational-intensive when executed on CPUs. One of the main advantages is its ability to significantly enhance image processing throughput, achieving up to 20 times the speed while maintaining reduced latency. This performance prowess is coupled with low power consumption, leading to decreased operational and maintenance costs due to fewer required server instances. Additionally, the solution is fully compatible with mainstream image processing software, facilitating seamless integration and leveraging existing software investments. The adaptability of the FPGA allows for remote reconfiguration, ensuring that the IP can be tailored to specific image processing scenarios without necessitating a server reboot. This ease of maintenance, combined with a substantial boost in compute density, underscores the IP's suitability for high-demand image processing environments, such as those encountered in data centers and cloud computing platforms.
The DSC Encoder from Trilinear Technologies sets the standard for real-time video compression within digital display and broadcast technologies. Supporting VESA’s Display Stream Compression criteria, this encoder facilitates the efficient compression of high-definition video streams, which is critical for reducing bandwidth usage while maintaining video quality across transmission channels in advanced video systems. Trilinear’s encoder is ideal for numerous applications, ranging from consumer electronics to professional AV systems, where ensuring high-quality video output is paramount. Its robust functionality enables it to handle streams with precision and maintain visual integrity, making it essential for systems that require high-efficiency video compression such as gaming consoles, digital TV, and mobile devices. The DSC Encoder offers a high degree of configurability, providing developers with the flexibility to adapt it to various system requirements. It is equipped with industry-standard interfaces, allowing straightforward integration into existing infrastructure, ensuring compatibility and operational efficiency across different platforms. This versatility makes it well-suited for use in SoC designs and FPGA implementations, broadening its applicability across various technological landscapes. Featuring comprehensive software support and detailed user documentation, Trilinear’s DSC Encoder simplifies the integration process into complex systems, ensuring that developers can tap into its full range of capabilities with ease. Its real-time processing power and optimized energy consumption profile make it a reliable choice for cutting-edge digital video applications, reflecting Trilinear’s commitment to advancing multimedia technology.
The Camera ISP Core is designed to optimize image signal processing by integrating sophisticated algorithms that produce sharp, high-resolution images while requiring minimal logic. Compatible with RGB Bayer and monochrome image sensors, this core handles inputs from 8 to 14 bits and supports resolutions from 256x256 up to 8192x8192 pixels. Its multi-pixel processing capabilities per clock cycle allow it to achieve performance metrics like 4Kp60 and 4Kp120 on FPGA devices. It uses AXI4-Lite and AXI4-Stream interfaces to streamline defect correction, lens shading correction, and high-quality demosaicing processes. Advanced noise reduction features, both 2D and 3D, are incorporated to handle different lighting conditions effectively. The core also includes sophisticated color and gamma corrections, with HDR processing for combining multiple exposure images to improve dynamic range. Capabilities such as auto focus and saturation, contrast, and brightness control are further enhanced by automatic white balance and exposure adjustments based on RGB histograms and window analyses. Beyond its core features, the Camera ISP Core is available with several configurations including the HDR, Pro, and AI variations, supporting different performance requirements and FPGA platforms. The versatility of the core makes it suitable for a range of applications where high-quality real-time image processing is essential.
The QOI Lossless Image Compression Encoder and Decoder from Ocean Logic represents a breakthrough in image compression technology. It boasts a highly efficient implementation of the QOI algorithm, engineered for both high and low-end FPGA devices. This IP core can achieve processing speeds of up to approximately 800 megapixels per second, even in lower-powered configurations like 4K at 30 frames per second. Its design optimizes processing efficiency while maintaining minimal resource usage, making it an excellent choice for applications requiring high-speed image processing with limited power availability. At the heart of the IP is its ability to handle substantial amounts of data swiftly, without significant energy expenditure, which is crucial for embedding in power-sensitive devices. The compression enables versatile application in diverse sectors, from consumer electronics to advanced computing environments where high throughput and rapid data handling are paramount. For developers and engineers, the QOI Lossless Compression IP offers an accessible and reliable means to incorporate state-of-the-art lossless image compression into their products, enhancing their ability to handle image data efficiently while ensuring fidelity and performance remain uncompromised.
The JPEG2000 Video Compression Solution from StreamDSP offers a highly versatile compression framework capable of both lossless and lossy compression within a single codestream. Designed to support high-quality and high-compression-rate applications, this solution integrates seamlessly into a wide range of FPGA platforms. It stands out by enabling compression and decompression tasks to be performed directly within the FPGA, eliminating the need for external processors and reducing system complexity. This capability is particularly beneficial for applications such as digital cinema, surveillance, and archival digital imaging, where maintaining high fidelity while minimizing storage is critical.
The BAT Audio Platform represents a leading-edge audio IP solution developed for battery-powered System-on-Chip (SoC) applications. Intelligently designed to offer unparalleled audio fidelity, this platform significantly enhances auditory features in SoCs, accommodating uses from active noise cancellation and beamforming to voice user interfaces. With a focus on low energy consumption, BAT ensures extended battery life, optimizing devices for efficient operations. Offering an expansive array of off-the-shelf solutions combined with numerous customization options, BAT enables rapid market readiness and risk reduction by building upon top-tier, silicon-proven IPs. This platform not only accelerates project timelines but also decreases development costs, freeing clients to focus on their core competencies while leveraging Dolphin's audio expertise. Incorporating features like WhisperTrigger for ultra-low-power voice activity detection and WhisperExtractor for energy-saving analog feature extraction, BAT represents a holistic approach to advancing audio technology. The platform’s digital and mixed-signal solutions provide seamless integration and configuration, ensuring high fidelity and low power consumption across a spectrum of applications from consumer electronics to IoT devices.
The JPEG-LS Encoder core from Parretto is designed to provide superior lossless image compression, compliant with the JPEG-LS standard, known for its efficacy in reducing data without compromising image integrity. Adhering to the ISO/IEC 14495-1 and ITU-T Rec. T.87 specifications, this encoder surpasses JPEG-2000 in many cases due to its minimal resource requirements and negligible latency. It delivers remarkable compression performance for images with sample depths ranging from 8 to 16 bits, and operates with less than one line of encoding latency, eliminating the need for external memory. The core is capable of processing one pixel per clock cycle and offers configurable output data word widths to tailor to specific image processing tasks. This encoder ensures seamless data flow with its pixel and FIFO data interfaces, or alternatively, through an Avalon Streaming interface equipped with back-pressure support. It is suitable for high-resolution image processing up to ultra-high-definition levels, making it a flexible and effective solution for a wide range of imaging applications.
High-resolution Image Processing IP Performance 4K60p@400MHz (600MHz for display interface) Features Support various color format : YUV420, YUV422, YUV444, and RGB Up-/Down-scaler x1/8~x8 : selectable scaler algorithm with Bi-cubic and Lanczos Two scalers, connected to DRAM and display/direct I/F respectively, operating at different ratios at the same time (configurable to one scaler option) Color space conversion : YUV2RGB and RGB2YUV, coefficient downloadable Optional features Crop and digital zoom : scaling on cropped region Flip : horizontal and vertical 3rd Party interfaces: such as AFBC v1.2 and PVRIC v4 (support output only) Interface Display Interface : 3 channels for components with vertical/horizontal sync signal (ITU-R BT.601 compatible) Direct Interface (optional feature) : On-the-fly interface based on ready-valid protocol Support CF10 (Chips&Media’s Frame buffer compression) for Chips&Media video codec Support AFBC v1.2 and PVRIC v4 (optional feature) for output of MAPI
This JPEG Encoder is a highly efficient IP core designed for image compression in machine vision applications. It supports pixel bit depths up to 12 bits, ensuring quality retention in diverse imaging scenarios. The encoder is particularly effective for use in standard FPGAs, offering cost-efficient solutions for high-speed data processing needs. Available in two main configurations, it can handle monochrome or YUV420 multiplexed pipeline at 150 MHz pixel clock, optimizing throughput in demanding environments. The dual pipe simultaneous encoding variant enhances video quality in YUV422 formats, ideal for resolutions such as 1280×720 at 60 frames per second. Additionally, the encoder provides an option for higher pixel clock operations tailored to specific platform requirements. Deployment over Ethernet with UDP capabilities ensures seamless data transmission, backed by robust gstreamer-based applications for both Linux and Windows platforms. To meet diverse application needs, the JPEG Encoder includes both lossy and lossless compression configurations. It is validated to perform optimally through extensive co-simulations and functional verifications, ensuring compliance with industry standards. This thorough validation process guarantees reliable performance in real-world applications, making it a preferred choice for professionals requiring high-quality imaging solutions.
HEVC/H.265 Main/Main10/ Main Still Picture Profile @L5.2 AVC/H.264 BP/CBP/MP/HP/HP10 @L5.2 Capable of encoding up to 8K ((8192x4096) A 32-bit AMBA3 APB bus for host CPU system control 128-bit AMBA3 AXI for data transfer (Optionally, additional secondary AXI) Latency tolerance Low power consumption Programmability Configurable IP Multi-instances Frame buffer compression (CFrame) Rotation & Mirroring Bit-depth & chroma sub-sample conversion Background detection 3DNR Lambda table QP Map Custom mode decision, etc.
The ASRC-Lite is a versatile 16-bit audio sample rate converter designed for multi-channel environments. It excels at handling diverse synchronous input channels that are converted capably to asynchronous outputs, ensuring seamless interoperability between different digital audio equipment. Its design is robust yet simplified, providing clean audio outputs with a total harmonic distortion plus noise (THD+N) of -90 dB, making it suitable for high-fidelity audio applications. Supported by the CWda50 framework, the ASRC-Lite operates under various sample rates, adapting dynamically to the input and output clock domains. Having multiple audio channels streamlined into one cohesive flow, the ASRC-Lite can handle up to eight channels, which can be beneficial for applications requiring crisp and clear sound quality across multiple outputs. This IP supports a wide range of interfaces, including I2S, SPDIF-AES3, and various forms of TDM, which enhances its applicability in numerous digital audio scenarios. The design philosophy hinges on flexibility and adaptability, allowing users to tweak processing parameters at pre-synthesis to attain optimal performance for specific applications.
The JPEG XS Encoder/Decoder from Techno Mathematical Co., Ltd. is designed to offer visually lossless, ultra-low latency performance suitable for next-generation 5G applications. This innovative technology supports both still images and real-time video streams, making it ideal for high-quality, large-screen displays and bandwidth-efficient transmission over networks. Its mezzanine compression capabilities are particularly important for minimizing latency without sacrificing image quality, thus serving well in applications where high-speed, high-fidelity data handling is required, such as in broadcasting and professional media production.
CTAccel's Image Processor for AWS offers a powerful image processing acceleration solution as part of Amazon's cloud infrastructure. This FPGA-based processor is available as an Amazon Machine Image (AMI) and enables customers to significantly enhance their image processing capabilities within the cloud environment. The AWS-based accelerator provides a remarkable tenfold increase in image processing throughput and similar reductions in computational latency, positively impacting Total Cost of Ownership (TCO) by reducing infrastructure needs and improving operational efficiency. These enhancements are crucial for applications requiring intensive image analysis and processing. Moreover, the processor supports a variety of image enhancement functions such as JPEG thumbnail generation and color adjustments, making it suitable for diverse cloud-based processing scenarios. Its integration within the AWS ecosystem ensures that users can easily deploy and manage these advanced processing capabilities across various imaging workflows with minimal disruption.
The CTAccel Image Processor for Xilinx's Alveo U200 is a FPGA-based accelerator aimed at enhancing image processing workloads in server environments. Utilizing the powerful capabilities of the Alveo U200 FPGA, this processor dramatically boosts throughput and reduces processing latency for data centers. The accelerator can vastly increase image processing speed, up to 4 to 6 times that of traditional CPUs, and decrease latency likewise, ensuring that compute density in a server setting is significantly boosted. This performance uplift enables data centers to lower maintenance and operational costs due to reduced hardware requirements. Furthermore, this IP maintains full compatibility with popular image processing software like OpenCV and ImageMagick, ensuring smooth adaptation for existing workflows. The advanced FPGA partial reconfiguration technology allows for dynamic updates and adjustments, increasing the IP's pragmatism for a wide array of image-related applications and improving overall performance without the need for server reboots.
The JDA1 is a versatile DAC core cell, designed for high-fidelity audio processing. It integrates a delta-sigma DAC with a PLL, eliminating the need for external clock generation by deriving all necessary sampling clocks from a 27MHz input. The JDA1 processes digital PCM inputs from 16 to 24 bits wide, supporting various standard and custom audio sample rates, including 96kHz. Its efficient silicon use requires just 0.3 to 0.4 sqmm, adapting seamlessly to scaling digital IC technologies.
The MIPITM V-NLM-01 is a specialized non-local mean image noise reduction product designed to enhance image quality through sophisticated noise reduction techniques. This hardware core features a parameterized search-window size and adjustable bits per pixel, ensuring a high degree of customization and efficiency. Supporting HDMI with resolutions up to 2048×1080 at 30 to 60 fps, it is ideally suited for applications requiring image enhancement and processing.
The JPEG FPGA Cores developed by A2e Technologies provide high-resolution JPEG Baseline functionality, designed to cater to a broad range of FPGA applications. This licensable, ITAR-compliant core supports true grayscale functionality, making it an ideal solution for applications where image quality and detail are crucial. The cores are customizable, allowing engineers to adapt them to different project needs, which can include adjusting resolution and pixel depth to match specific requirements. This versatility supports a wide array of use cases, allowing for seamless integration into systems where space constraints and performance efficiency are paramount. The availability of a low-cost evaluation license further underscores A2e Technologies' commitment to making their technology accessible, enabling prospective users to test the core’s capabilities effectively before finalizing their integration decision. This flexibility, coupled with A2e's robust support services, empowers customers to succeed in their development projects, irrespective of complexity.
The J5 is a digital processor designed to perform advanced 3-D audio virtualization. Handling both TruSurround and SRS 3D algorithms, it allows users to enjoy a full surround sound feel with just two speakers by implementing complex channel downmixing and spatial audio effects. The J5 is economically designed, needing less than 0.16 sqmm of silicon, making it efficient and cost-effective for high-density audio systems.
The J1 core cell is a remarkably small and efficient audio decoder that manages Dolby Digital, AC-3, and MPEG audio decompression. With a design that occupies only 1.0 sqmm of silicon area using 0.18u CMOS technology, it delivers a robust solution for decoding 5.1 channel dolby bitstreams and supports data rates up to 640kb/s. The J1 produces high-quality stereo outputs, both normal and Pro-Logic compatible, from Dolby Digital and MPEG-encoded audio, ideal for set-top boxes and DVD applications.
HEVC/H.265 - Main/Main10 Profile @L5.1 AVC/H.264 - BP/CBP/MP/HP/HP10 Profile @ L5.2 Capable of decoding up to 4K60fps (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Secondary AXI interfaces Downscaler (on-the-fly mode)
Designed for environments demanding high precision, the ASRC-Pro stands as a 24-bit multi-channel audio sample rate converter emphasizing immaculate audio quality. It is especially tailored for high-end audio processing, boasting an impressive -130 dB THD+N. This feature makes it ideal for studio applications where maintaining the integrity of the audio signal is paramount. Operating within the CWda52 context, this IP model provides versatile compatibility with various audio channel configurations, supporting 2, 4, 6, or 8 channels. The ultra-precise conversion process accommodates different input and output sample rates independently, allowing professionals to maintain exacting standards in varied digital audio environments. The availability of standard interfaces such as SPDIF-AES3, I2S, and TDM ensures that the ASRC-Pro can be seamlessly integrated into numerous audio processing setups. Leveraging digital conversion methodologies devoid of external components like PLLs, ASRC-Pro prioritizes flexibility and precision, accommodating engineering requirements from standard to custom project needs.
Video Codec Standard AV1: Main/High profile @ L6 Main tier 50Mbps Professional profile except 12-bit @ L6 Main tier 50Mbps Mono/YUV420/YUV422/YUV444 8-/10-bit HEVC/H.265: Main/Main 10/Main 4:2:2 10 profile @ L6 High tier Main 4:4:4/Main 4:4:4 10 profile @ L6 High tier (Only support 4:2:0 coding tools, high precision weighted prediction, and chroma QP offset list) AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L6 High 10 Intra/High 4:2:2/High 4:2:2 Intra profile with frame_mbs_only_flag = 1 @ L6 High 4:4:4 Predictive/High 4:4:4 Intra/CAVLC 4:4:4 Intra profile @ L6 with: frame_mbs_only_flag = 1 bit_depth_luma ≤ 10 bit_depth_chroma ≤ 10 frame_mbs_only_flag = 1 and qpprime_y_zero_transform_bypass_flag = 0 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported), YUV420 8/10-bit Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Rotate/Mirror Down-scaler Crop Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
The CTAccel Image Processor for Intel PAC is crafted to elevate the processing capabilities of data centers by transferring intensive image processing tasks from CPU to FPGA. By exploiting the strengths of Intel's Programmable Acceleration Card (PAC), this IP offers substantial improvements in throughput, latency, and Total Cost of Ownership (TCO). This IP enhances data center efficiency with increased image processing speeds ranging from four to fivefold over traditional CPU solutions, alongside reduced latency by two to threefold. The result is fewer servers needed, translating into lower maintenance and energy costs. Its compatibility with well-known image processing tools ensures that users need not alter their existing setups substantially to benefit from the acceleration offered by the FPGA. Moreover, the CTAccel Image Processor leverages advanced FPGA partial reconfiguration, allowing users to update and adjust computational cores remotely, maximizing performance for specific applications without downtime. This flexibility is pivotal for scenarios involving varied processing loads or evolving computational demands, ensuring uninterrupted performance enhancement.
Video Codec Standard AV1: Main profile @ L5.1 HEVC: Main/Main10 profile, Main/Main 10 Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L5.2 (Interlaced coding tools are not supported) Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
The MIPI IP offering from XtremeSilica encompasses a suite of solutions designed to meet the mobile and consumer electronics industry's demand for high bandwidth and low power consumption. This IP provides the functional and physical layers needed to ensure seamless connectivity between cameras, displays, and other sensors in modern devices.\n\nKey advantages of the MIPI solutions include enhanced signal integrity and data transfer efficiency, crucial for high-resolution imaging and data streaming applications. The IP enables compact integration, critical for form factor-sensitive devices, ensuring robust performance without excessive power drain.\n\nXtremeSilica's MIPI solutions are versatile, making them suitable for a diverse range of applications, from mobile phones to automotive systems, where they support advanced functionalities like augmented reality and high-speed data communication. The scalability of these IPs ensures they are equipped to handle future advancements in device interconnectivity.
The Ultra-High Throughput JPEG 2000 Encoder by Alma Technologies is crafted to deliver superior image compression for high-resolution video formats. Featuring a scalable architecture capable of processing extensive data rates, this encoder directly addresses the needs of 4K/8K video applications. Utilizing state-of-the-art compression techniques, it efficiently compresses image data into a JPEG 2000 format, allowing for both lossless and lossy compression options. Designed for both ASIC and FPGA implementations, the encoder boasts a flexible and adaptable setup, permitting fine-tuning of its performance to align with available silicon technologies. It ensures high-quality image outputs through flexible sampling ratios, supporting a wide spectrum of color depths and dynamic ranges without necessitating additional external memory resources. The encoder's design is particularly advantageous for bandwidth-restricted applications such as streaming, where balancing image quality against transmission and storage limits is critical. This IP core maximizes both efficiency and effectiveness in high-performance video processing environments, ensuring Alma Technologies' reputation for delivering reliable and adaptable compression tools.
The JH7100 platform is a breakthrough product in intelligent vision processing, featuring dual-core processors and a sophisticated image processing subsystem. Tailored for edge computing applications, this platform excels in real-time video and image processing tasks. With compatibility for H.264, H.265, and JPEG encoding, the JH7100 seamlessly manages complex image data workloads. It incorporates Vision DSP and NNE technologies to bolster the system’s AI capabilities, enabling more efficient and accurate image recognition and processing. Ideal for applications such as smart surveillance, industrial intelligence, and smart home automation, the JH7100 represents StarFive's dedication to bridging the gap between powerful processing and practical application, ensuring lower power consumption and high-performance output.
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding Down-scaler (On-the-fly mode) MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
As an upgrade to its predecessor, the JH7110 platform integrates enhanced AI capabilities and processing power. Built to support a wider array of applications including cloud computing and industrial control, this platform is perfect for use in environments that require robust performance and security. It features a quad-core architecture and an enhanced GPU for superior graphics rendering. With improved memory bandwidth and a faster processor, the JH7110 delivers better performance metrics and a broader range of high-speed interfaces. This platform is designed for current and emerging markets, such as personal computing and NAS applications. StarFive ensures that the platform remains adaptable, giving developers a reliable foundation equipped for modern AI and multimedia processing.
The 4K Video Scaler by Zipcores is engineered for studio-quality RGB scaling, optimized specifically for UHD and 4K resolutions. It supports processing of 2 pixels per clock and can achieve an effective pixel clock rate of up to 600 MHz, making it suitable for mid-range FPGAs and SoCs. The scaler provides simple input and output interfaces that are compatible with the AXI4-stream standard, and it operates without the need for a frame buffer or external memory, enhancing its efficiency.
The Column A/D Converter serves as a pivotal component in CMOS image sensors, converting analog signals from pixels into a precise digital format for subsequent processing. Embedded with advanced signal processing techniques, this IP ensures minimal error margins and optimizes the performance of imaging systems by effectively handling noise and signal variance. Engineered to support high-speed and high-accuracy image conversions, this A/D converter is structured to accommodate single-slope and multi-slope methodologies to maximize data fidelity and resolution. Its flexibility allows it to adapt to varied operational contexts, ranging from consumer electronics to specialized industry applications like barcode scanning and biometric authentication. With a focus on minimizing power consumption while ensuring efficient signal conversion, this converter meets the stringent requirements for portable and battery-operated devices. Combining compact design with sophisticated algorithmic processing, the Column A/D Converter is integral to enhancing overall image quality and system efficiency, making it indispensable for modern imaging solutions prepared to meet tomorrow’s technological demands.
Video Codec Standard HEVC: Main/Main10 profile @ L6 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 (Interlaced coding tools are not supported) Performance 4K120fps@500MHz or 8K60fps@1GHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer *Optional AXI can be used to alleviate bandwidth usage
The v-MP6000UDX Visual Processing Unit is a highly versatile processor featuring a unified processing architecture. This unit specializes in enabling real-time execution of the most intensive neural network tasks with exceptional power efficiency and a minimal silicon footprint. It supports a broad array of processing needs, effectively integrating deep learning, computer vision, image processing, and video compression on a single architecture. Designed to meet the rigorous demands of modern applications, the v-MP6000UDX offers unparalleled performance with its single software-programmable platform. Developers benefit from reduced development complexity, faster speed to market, and increased product lifespans. The processor can efficiently map and execute all layers of neural networks, easing the burden on software engineers and allowing seamless transitions across different machine learning frameworks. The versatility and high efficiency of the v-MP6000UDX make it an ideal choice for industries such as automotive, gaming, and mobile devices. Its ability to seamlessly integrate into system-on-chip designs further broadens its appeal, offering enhanced optimization opportunities for developers and significantly reducing integration overhead.
Video Codec Standard AV1: Main profile @ L5.1 Main tier 50Mbps HEVC/H.265: Main/Main 10 profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L5.2 (Interlaced coding tools are not supported.) VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
TicoXS represents a revolutionary approach to image compression, setting new standards with its JPEG XS compliance. Designed by intoPIX, this technology ensures ultra-low latency and high-quality image transmission, suitable for live video feeds and other applications demanding real-time responsiveness. The IP cores are highly efficient, maintaining exceptional visual quality even at significantly reduced data rates, making it perfect for bandwidth-limited scenarios. TicoXS can be integrated into a wide range of devices including FPGAs and ASICs, offering remarkable flexibility for developers. Moreover, the support for multiple color spaces and sampling formats such as 4:2:2 and 4:4:4 makes it adaptable for varied image processing needs. TicoXS effortlessly tackles the challenges posed by high definition and ultra-high definition formats, delivering a seamless compression solution that is both resource-optimized and performance-tuned, underpinning its reputation for creating visually lossless compression even under extreme conditions.
Video Codec Standard AV1: Main profile @ L6 Main tier 50Mbps HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
The AVIF Image Encoder by BLUEDOT offers a cutting-edge solution for service providers facing network traffic challenges posed by the increasing use of images on web pages. This encoder primarily focuses on rapid processing and low computational resource usage, making it an ideal choice for real-time applications. Users can leverage its advanced capabilities for quick encoding, ensuring seamless and cost-effective delivery of image content while maintaining superior quality standards.
Supported standards for Decoder ISO/IEC23008-2 HEVC/H.265, ITU-T Rec. H.265 Main/Main10 Profile L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance Interface AMBA 32-bit APB interface for Host CPU AMBA 128-bit AXI interface for the external memory
The Ultra-High Throughput JPEG-LS Encoder from Alma Technologies is optimized to perform efficient, high-quality image data compression for applications requiring advanced image integrity. This encoder IP core excels in delivering lossless compression for full color and grayscale images, and is particularly effective within resource-limited environments, thanks to its minimal silicon footprint. Adapting to a transparent multi-engine architecture, the JPEG-LS Encoder divides image data into manageable chunks, processed simultaneously using parallel engines. This feature not only enhances throughput rates but also simplifies integration into both FPGA and ASIC systems. It retains image quality while ensuring performance remains unaffected by the limitations of system resources. Primarily used in environments where image quality cannot be compromised, such as medical imaging and professional photography, the JPEG-LS Encoder supports a broad dynamic range and various chroma sampling formats. This flexibility, along with its support for high-speed applications, makes it an essential component for any advanced imaging system requiring robust image compression capabilities.
The JPEG Codec from Shikino High-Tech offers a comprehensive solution for image compression needs, particularly in devices where efficiency and speed are paramount. This codec supports various JPEG formats, achieving high-speed processing capabilities. By embedding original algorithms, the JPEG Codec ensures minimal power consumption while maintaining compactness, making it suitable for integration into a variety of digital systems. The codec's design philosophy centers on versatility and robustness, allowing it to serve a broad array of applications from consumer electronics to high-performance graphic systems. This flexibility is complemented by its compatibility with different system architectures, facilitating seamless integration into existing workflows. The codec's efficient compression algorithms ensure that image quality is preserved, while the data size is significantly reduced, optimizing storage and transmission. Through this offering, Shikino High-Tech provides a competitive and reliable solution for developers and engineers looking to implement efficient image processing capabilities in their projects. The JPEG Codec stands out for its balance between performance and power efficiency, embodying Shikino's commitment to advanced semiconductor technologies.
Video Codec Standard AV1: Main profile @ L6 High tier HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
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