The JPEG Encoder from section5 is engineered to cater to real-time image compression demands, adhering to the baseline JPEG standard (ITU T.81) and supports Motion JPEG. This IP is capable of handling up to 12 bits of depth, although it defaults to 8 bits, which ensures high-quality image processing with super low latency, critical for applications in rolling shutter cameras. The encoder is designed to be fully bit and cycle accurate, with available simulation models to aid in verifying compliance.
One highlight of this JPEG Encoder IP is its minimal hardware requirements, needing no external RAM beyond an FPGA and an Ethernet PHY. This low power consumption IP benefits from clock synchronous, distributed operations. Available in two versions – the L1 variant for monochrome or YUV420 multiplexed pipelines and the L2 variant supporting simultaneous high-quality YUV422 encodings, it's optimized for varying standards such as MJPEG.
The IP supports seamless integration into existing systems, making use of real-time streaming solutions over UDP/Ethernet, aligning with RFC2435 standards. The encoder can be applied across a variety of performance needs, adapted to different FPGA families, all the while maintaining energy efficiency and high-performance throughput for applications like machine vision and video transmission.
