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Akida Neural Processor IP is a groundbreaking component offering a self-contained AI processing solution capable of locally executing AI/ML workloads without reliance on external systems. This IP's configurability allows it to be tailored to various applications, emphasizing space-efficient and power-conscious designs. Supporting both convolutional and fully-connected layers, along with multiple quantization formats, it addresses the data movement challenge inherent in AI, significantly curtailing power usage while maintaining high throughput rates. Akida is designed for deployment scalability, supporting as little as two nodes up to extensive networks where complex models can thrive.
The second generation of BrainChip's Akida platform expands upon its predecessor with enhanced features for even greater performance, efficiency, and accuracy in AI applications. This platform leverages advanced 8-bit quantization and advanced neural network support, including temporal event-based neural nets and vision transformers. These advancements allow for significant reductions in model size and computational requirements, making the Akida 2nd Generation a formidable component for edge AI solutions. The platform effectively supports complex neural models necessary for a wide range of applications, from advanced vision tasks to real-time data processing, all while minimizing cloud interaction to protect data privacy.
Overview: CMOS Image Sensors (CIS) often suffer from base noise, such as Additive White Gaussian Noise (AWGN), which deteriorates image quality in low-light environments. Traditional noise reduction methods include mask filters for still images and temporal noise data accumulation for video streams. However, these methods can lead to ghosting artifacts in sequential images due to inconsistent signal processing. To address this, this IP offers advanced noise reduction techniques and features a specific Anti-ghost Block to minimize ghosting effects. Specifications:  Maximum Resolution o Image : 13MP o Video : 13MP@30fps  -Input formats : YUV422–8 bits  -Output formats o DVP : YUV422-8 bits o AXI : YUV420, YUV422  -8 bits-Interface o ARM® AMBA APB BUS interface for ISP system control o ARM® AMBA AXI interface for data o Direct connection to sensor stream data (DVP) Features:  Base Noise Correction: AWGN reduction for improved image quality  Mask Filter: Convolution-based noise reduction for still images  Temporal Noise Data Accumulation: Gaussian Distribution-based noise reduction for video streams using 2 frames of images  3D Noise Reduction (3DNR): Sequential image noise reduction with Anti-ghost Block  Motion Estimation and Adaptive: Suppresses ghosting artifacts during noise reduction  Real-Time Processing: Supports Digital Video Port (DVP) and AXI interfaces for seamless integration  Anti-Ghost  Real time De-noising output
0.75V ESD power protection. The ESD clamp is designed to provide protection for 0.75 V Analog and Core domain using 0.75V FinFet transistors in TSMC N3E process. The target ESD robustness can be selected.
Sunplus' LVDS IP provides a high-speed solution for data transmission across electronic devices, optimizing communication between integrated circuits. LVDS, or Low-Voltage Differential Signaling, is an effective way to achieve rapid data transfer rates with minimal electromagnetic interference, making it ideal for high-performance computer and multimedia applications. The IP is a key component in facilitating the transfer of video and display data, ensuring a crisp and clear output. Its ability to handle high data transfer speeds while maintaining a reduced power footprint is advantageous for modern consumer electronics that prioritize both performance and energy efficiency. With its adaptable design, Sunplus' LVDS IP can be integrated across a wide array of devices, providing developers with the flexibility needed for customized solutions. Its robust signal management capabilities ensure that data integrity is preserved even in complex operational environments, enhancing overall system reliability and user satisfaction.
MetaTF is BrainChip's machine learning framework for developing systems on the Akida neural processor. Designed to aid in creating, training, and testing neural networks, MetaTF integrates seamlessly with TensorFlow models. Its key feature is the ability to convert CNN models to Spiking Neural Networks (SNN), facilitating low-latency, low-power operations suited for edge environments. By utilizing Python scripting and tools, MetaTF simplifies model conversion and optimization, delivering automatic CNN to SNN transitions without needing to learn new frameworks. MetaTF also includes various development tools, encompassing runtime simulation and robust testing environments.
The DDR5 Server DIMM Chipset by Rambus is designed for next-generation data center servers, offering maximum bandwidth of up to 8000 MT/s on RDIMMs and up to 12800 MT/s on MRDIMMs. It includes components such as Registering Clock Drivers (RCD), Power Management ICs (PMICs), Serial Presence Detect Hubs (SPD Hub), and Temperature Sensors for optimal performance. This chipset is engineered to support evolving data center requirements, enabling enhanced performance through higher memory speeds and improved power efficiency.
Overview: Lens distortion is a common issue in cameras, especially with wide-angle or fisheye lenses, causing straight lines to appear curved. Radial distortion, where the image is expanded or reduced radially from the center, is the most prominent type. Failure to correct distortion can lead to issues in digital image analysis. The solution involves mathematically modeling and correcting distortion by estimating parameters that determine the degree of distortion and applying inverse transformations. Automotive systems often require additional image processing features, such as de-warping, for front/rear view cameras. The Lens Distortion Correction H/W IP comprises 3 blocks for coordinate generation, data caching, and interpolation, providing de-warping capabilities for accurate image correction. Specifications:  Maximum Resolution: o Image: 8MP (3840x2160) o Video: 8MP @ 60fps  Input Formats: YUV422 - 8 bits  Output Formats: o AXI: YUV420, YUV422, RGB888 - 8 bits  Interface: o ARM® AMBA APB BUS interface for system control o ARM® AMBA AXI interface for data Features:  Programmable Window Size and Position  Barrel Distortion Correction Support  Wide Angle Correction up to 192°  De-warping Modes: o Zoom o Tilt o Pan o Rotate o Side-view  Programmable Parameters: o Zoom Factor: controls Distance from the Image Plane to the Camera (Sensor)
Overview: Cybersecurity IPs offer a range of essential security features to protect your digital assets and sensitive information. From True Random Number Generators (TRNG) to advanced encryption algorithms like AES, DES, 3DES, and cryptographic hash functions like SHA, as well as RSA for secure key exchange and digital signatures, the IPs provide a comprehensive suite of tools to safeguard your data. Key Features:  True Random Number Generator (TRNG): Generates unpredictable and unbiased random numbers for cryptographic applications.  Advanced Encryption Standard (AES): Provides robust encryption with symmetric key algorithms for securing data.  Data Encryption Standard (DES) and Triple DES (3DES): Implement legacy encryption algorithms for data protection.  Hash Functions: Includes secure cryptographic hash functions like SHA (Secure Hash Algorithm) for data integrity verification.  RSA: Enables secure key exchange, encryption, and digital signatures for secure communication. These cybersecurity IPs are designed to meet the stringent security requirements of modern applications, ensuring the confidentiality, integrity, and authenticity of your data.
Speedcore embedded FPGA (eFPGA) IP represents a notable advancement in integrating programmable logic into ASICs and SoCs. Unlike standalone FPGAs, eFPGA IP lets designers tailor the exact dimensions of logic, DSP, and memory needed for their applications, making it an ideal choice for areas like AI, ML, 5G wireless, and more. Speedcore eFPGA can significantly reduce system costs, power requirements, and board space while maintaining flexibility by embedding only the necessary features into production. This IP is programmable using the same Achronix Tool Suite employed for standalone FPGAs. The Speedcore design process is supported by comprehensive resources and guidance, ensuring efficient integration into various semiconductor projects.
Overview: The Camera ISP IP is an Image Signal Processing (ISP) IP developed for low-light environments in surveillance and automotive applications, supporting a maximum processing resolution of 13 Mega or 8Mega Pixels (MP) at 60 frames per second (FPS). It offers a configurable ISP pipeline with features such as 18x18 2D/8x6 2D Color Shading Correction, 19-Point Bayer Gamma Correction, Region Color Saturation, Hue, and Delta L Control functions. The ISP IP enhances image quality with optimal low-light Noise/Sharp filters and offers benefits such as low gate size and memory usage through algorithm optimization. The IP is also ARM® AMBA 3 AXI protocol compliant for easy control via an AMBA 3 APB bus interface. Specifications:  Maximum Resolution: o Image: 13MP/8MP o Video: 13MP @ 60fps / 8MP @ 60fps  Input Formats: Bayer-8, 10, 12, 14 bits  Output Formats: o DVP: YUV422, YUV444, RGB888 - 8, 10, 12 bits o AXI: YUV422, YUV444, YUV420, RGB888 - 8, 10, 12 bits  Interface: o ARM® AMBA APB BUS interface for ISP system control o ARM® AMBA AXI interface for data o Direct connection to sensor stream data (DVP) o Features:  Defective Pixel Correction: On-The-Fly Defective Pixel Correction  14-Bit Bayer Channel Gain Support: Up to x4 / x7.99 with Linear Algebra for Input Pixel Level Adjustment  Gb/Gr Unbalance Correction: Maximum Correction Tolerance Gb/Gr Rate of 12.5%  2D Lens-Shading Correction: Supports 18x18 / 8x6 with Normal R/Gb/Gr/B Channel Shading Correction and Color Stain Correction  High-Resolution RGB Interpolation: Utilizes ES/Hue-Med/Average/Non-Directional Based Hybrid Type Algorithm  Color Correction Matrix: 3x3 Matrix  Bayer Gamma Correction: 19 points  RGB Gamma Correction: 19 points  Color Enhancement: Hue/Sat/∆-L Control for R/G/B/C/M/Y Channels  High-Performance Noise Reduction: For Bayer/RGB/YC Domain Noise Reduction  High-Resolution Sharpness Control: Multi-Sharp Filter with Individual Sharp Gain Control  Auto Exposure: Utilizes 16x16 Luminance Weight Window & Pixel Weighting  Auto White Balance: Based on R/G/B Feed-Forward Method  Auto Focus: 2-Type 6-Region AF Value Return
The KL730 AI SoC is a state-of-the-art chip incorporating Kneron's third-generation reconfigurable NPU architecture, delivering unmatched computational power with capabilities reaching up to 8 TOPS. This chip's architecture is optimized for the latest CNN network models and performs exceptionally well in transformer-based applications, reducing DDR bandwidth requirements substantially. Furthermore, it supports advanced video processing functions, capable of handling 4K 60FPS outputs with superior image handling features like noise reduction and wide dynamic range support. Applications can range from intelligent security systems to autonomous vehicles and commercial robotics.
The agileADC analog-to-digital converter is a traditional Charge-Redistribution SAR ADC that is referenced to VDD, VSS. The architecture can achieve up to 12-bit resolution at sample rates up to 64 MSPS. It includes a 16-channel input multiplexor that can be configured to be buffered or unbuffered, and support differential or single-ended inputs. Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our automated design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. Our highly configurable and multi-node analog IP products are developed to meet the customer’s exact requirements. These digitally-wrapped and verified solutions can be seamlessly integrated into any SoC, significantly reducing complexity, time and costs.
Overview: The DDR5 RCD Controller is a registering clock driver utilized in DDR5 RDIMMs and LRDIMMs. It buffers the Command/Address (CA) bus, chip selects, and clock signals between the host controller and DRAMs. Additionally, it establishes a BCOM bus to control data buffers in LRDIMMs. Key Features:  Compliance with JEDEC's JESD82-511  Maximum SCL Operating speed of 12.5MHz in I3C mode  DDR5 server speeds up to 4800MT/s  Dual-channel configuration with 32-bit data width per channel  Support for power-saving mechanisms  Rank 0 & rank 1 DIMM configurations  Loopback and pass-through modes  BCOM sideband bus for LRDIMM data buffer control  In-band Interrupt support  Packet Error Check (PEC)  CCC Packet Error Handling  Error log register  Parity Error Handling  Interrupt Arbitration  I2C Fast-mode Plus (FM+) and I3C Basic compatibility  Switch between I2C mode and I3C Basic  Clearing of Status Registers  Compliance with JESD82-511 specification  I3C Basic Common Command Codes (CCC) Applications:  RDIMM  LRDIMM  AI (Artificial Intelligence)  HPC (High-Performance Computing)  Data-intensive applications
Overview: RCCC and RCCB in ISP refer to Red and Blue Color Correction Coefficients, respectively. These coefficients are utilized in Image Signal Processing to enhance red and blue color components for accurate color reproduction and balance. They are essential for color correction and calibration to ensure optimal image quality and color accuracy in photography, video recording, and visual displays. The IP is designed to process RCCC pattern data from sensors, where green and blue pixels are substituted by Clear pixel, resulting in Red or Clear (Monochrome) format after demosaicing. It supports real-time processing with Digital Video Port (DVP) format similar to CIS output. RCCB sensors use Clear pixels instead of Green pixels, enhancing sensitivity and image quality in low-light conditions compared to traditional RGB Bayer sensors. LOTUS converts input from RCCB sensors to a pattern resembling RGB Bayer sensors, providing DVP format interface for real-time processing. Features:  Maximum Resolution: 8MP (3840h x 2160v)  Maximum Input Frame Rate: 30fps  Low Power Consumption  RCCC/RCCB Pattern demosaicing
Overview: The UCIe IP supports multiple protocols (CXL/PCIe/Streaming) to connect chiplets, reducing overall development cycles for IPs and SOCs. With flexible application and PHY interfaces, The UCIe IP is ideal for SOCs and chiplets. Key Features:  Supports UCIe 1.0 Specification  Supports CXL 2.0 and CXL 3.0 Specifications  Supports PCIe Gen6 Specification  Supports PCIe Gen5 and older versions of PCIe specifications  Supports single and two-stack modules  Supports CXL 2.0 68Byte flit mode with Fallback mode for PCIe non-flit mode transfers  Supports CXL 3.0 256Byte flit mode  Supports PCIe Gen6 flit mode  Configurable up to 64-lane configuration for Advanced UCIe modules and 16 lanes for Standard UCIe modules  Supports sideband and Mainband signals  Supports Lane repair handling  Data to clock point training and eye width sweep support from transmitter and receiver ends  UCIe controller can work as Downstream or Upstream  Main Band Lane reversal supported  Dynamic sense of normal and redundant clock and data lines activation  UCIe enumeration through DVSEC  Error logging and reporting supported  Error injection supported through Register programming  RDI/FDI PM entry, Exit, Abort flows supported  Dynamic clock gang at adapter supported Configurable Options:  Maximum link width (x1, x2, x4, x8, x16)  MPS (128B to 4KB)  MRRS (128B to 4KB)  Transmit retry/Receive buffer size  Number of Virtual Channels  L1 PM substate support  Optional Capability Features can be Configured  Number of PF/VFDMA configurable Options  AXI MAX payload size Variations  Multiple CPI Interfaces (Configurable)  Cache/memory configurable  Type 0/1/2 device configurable
Primesoc's PCIE GEn7 IP is dual mode controller , supporting upto 128Gbps per lane data rate , which can work as root complex or as an endpoint. This is a soft IP which can support serdes and non serdes architectures and PIPE interface of 64bit and lanes configurable from 1/2/4/8/16.
The agilePMU Subsystem is an efficient and highly integrated power management unit for SoCs/ASICs. Featuring a power-on-reset, multiple low drop-out regulators, and an associated reference generator. The agilePMU Subsystem is designed to ensure low power consumption while providing optimal power management capabilities. Equipped with an integrated digital controller, the agilePMU Subsystem offers precise control over start-up and shutdown, supports supply sequencing, and allows for individual programmable output voltage for each LDO. Status monitors provide real-time feedback on the current state of the subsystem, ensuring optimal system performance. Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our automated design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. Our highly configurable and multi-node analog IP products are developed to meet the customer’s exact requirements. These digitally-wrapped and verified solutions can be seamlessly integrated into any SoC, significantly reducing complexity, time and costs.
Advanced Peripheral Bus (APB) is one of the Advanced Microcontroller Bus Architecture (AMBA) family protocols. It is a low-cost interface that is designed for low power consumption and interface simplicity. Unlike AHB, it is a non-pipelined protocol for connecting low-bandwidth peripherals. Mostly used to link external peripherals to the SOC. Every APB transfer requires at least two clock cycles (SETUP Cycle and ACCESS Cycle) to finish. The APB interface is designed for accessing the programmable control registers of peripheral devices. The APB protocol has two independent data buses, one for read data and one for write data. The buses can be 8, 16, or 32 bits wide. The read and write data buses must have the same width. Data transfers cannot occur concurrently because the read data and write data buses do not have their own individual handshake signals.
Silicon Creations' SerDes Interfaces are crafted to handle high-speed data transmission challenges over varied processes, ranging from 12nm to 180nm. Addressing multiple protocols such as CPRI, PCIe, and SATA, these interfaces demonstrate flexibility by supporting data transmission speeds from 100 Mbps to beyond 32 Gbps. The architecture incorporates a host of advanced features including adaptive equalization techniques and programmable de-serialization widths, making it stand out in terms of performance and signal integrity even under challenging conditions. With ultra-low latency PMAs, they sustain excellent operational speed and efficiency, imperative for sophisticated communication applications. Moreover, Silicon Creations partners with leading entities to provide comprehensive solutions, including complete PCIe PHY integrations. This synergy ensures that SerDes Interfaces are fully optimized for operational excellence, delivering stable and reliable communication signals. With an emphasis on low power and minimized area requirements, they cater to burgeoning industry needs for power-efficient and space-conservative designs.
Overview: The Expanded Serial Peripheral Interface (xSPI) Master/Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy SPI devices. It is designed to connect xSPI Master/Slave devices in computing, automotive, Internet of Things, embedded systems, and mobile processors to various peripherals such as non-volatile memories, graphics peripherals, networking devices, FPGAs, and sensor devices. Key Features:  Compliance with JEDEC standard JESD251 eXpanded SPI for Non-Volatile Memory Devices, Version 1.0  Support for Single master and multiple slaves per interface port  Single Data Rate (SDR) and Double Data Rate (DDR) support  Source synchronous clocking  Deep Power Down (DPD) enter and exit commands  Eight IO ports in standard, expandable based on system requirements  Optional Data Strobe (DS) for write masking  bit wide SDR transfer support  Profile 1.0 Commands for non-volatile memory device management  Profile 2.0 Commands for read or write data for various slave devices Applications:  Consumer Electronics  Defense & Aerospace  Virtual Reality  Augmented Reality  Medical  Biometrics  Automotive Devices  Sensor Devices
Our Expanded Serial Peripheral Interface (JESD251) Master controller features a low signal count and high data bandwidth, making it ideal for use in computing, automotive, Internet of Things, embedded systems, and mobile system processors. It connects multiple sources of Serial Peripheral Interface (xSPI) slave devices, including nonvolatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports a single master and multiple slaves per interface port. • Supports Single Data Rate and Double Data Rate. • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for writemasking. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands to read or writedata for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
The SPD5 Hub Function IP has been developed to interface I3C/I2C Host Bus and it allows an isolation of local devices like Temperature Sensor(TS), from master host bus. This SPD5 has Two wire serial interface like SCL, SDA
Overview: The Secure Enclave IPs are Common Criteria (CC) EAL5+PP0084/PP0117 and EAL5+PP0117 certification-ready Secure Enclaves, respectively. They are available as hard macros for seamless integration into SoCs. These Secure Enclave IPs provide the highest level of security for an SoC, incorporating patented design techniques and countermeasures against side-channel and perturbation attacks to ensure robust security while minimizing power consumption. Key Features:  Cryptographic Hardware Accelerators: Efficiently support standard cryptography and security operations to increase throughput while adhering to power constraints and security requirements.  BootROM and Secondary Boot Loader: Manage the certified life cycle of the Secure Enclave, enforcing and assuring security from manufacturing to deployment.  Proprietary IP: Based on proprietary IP that is free of 3rd party rights and royalties. Benefits: The Secure Enclave IPs offer robust security measures, efficient cryptographic support, and secure life cycle management, making them ideal for applications that require the highest levels of security and reliability. Applications: The Secure Enclave IP is versatile and suitable for a wide range of applications, including but not limited to:  Secured and Certified iSIM & iUICC  EMVco Payment  Hardware Cryptocurrency Wallets  FIDO2 Web Authentication  V2X HSM Protocols  Smart Car Access  Secured Boot  Secure OTA Firmware Updates  Secure Debug  Any design requiring a Secure Enclave, Secure Element, or Hardware Root of Trust protected against side-channel and perturbation fault attacks. Compliance and Support: The Secure Enclave is compliant with and ready for CC EAL5+ and EMVCo certification. It is delivered with an SDK and pre-certified CryptoLibrary and secure Boot Loader for seamless integration and enhanced security.
Overview: Human eyes have a wider dynamic range than CMOS image sensors (CIS), leading to differences in how objects are perceived in images or videos. To address this, CIS and IP algorithms have been developed to express a higher range of brightness. High Dynamic Range (HDR) based on Single Exposure has limitations in recreating the Saturation Region, prompting the development of Wide Dynamic Range (WDR) using Multi Exposure images. The IP supports PWL companding mode or Linear mode to perform WDR. It analyzes the full-image histogram for global tone mapping and maximizes visible contrast in local areas for enhanced dynamic range. Specifications:  Maximum Resolution: o Image: 13MP o Video: 13MP @ 60fps (Input/Output)  Input Formats (Bayer): o HDR Linear Mode: Max raw 28 bits o Companding Mode: Max PWL compressed raw 24 bits  Output Formats (Bayer): 14 bits  Interface: o ARM® AMBA APB BUS interface for ISP system control o ARM® AMBA AXI interface for data o Video data stream interface Features:  Global Tone Mapping based on histogram analysis o Adaptive global tone mapping per Input Images  Local Tone Mapping for adaptive contrast enhancement  Real-Time WDR Output  Low Power Consumption and Small Gate Count  28-bit Sensor Data Interface
AMBA AHB is a bus interface designed for high-performance synthesizable applications. It specifies the interface between components such as initiator , interconnects, and targets. AMBA AHB incorporates the features needed for high-performance, high clock frequency systems. The most common AHB targets are internal memory devices, external memory interfaces, and high-bandwidth peripherals.
The CXL 3.1 Switch by Panmnesia is a high-performance solution facilitating flexible and scalable inter-device connectivity. Designed for data centers and HPC systems, this switch supports extensive device integration, including memory, CPUs, and accelerators, thanks to its advanced connectivity features. The switch's design allows for complex networking configurations, promoting efficient resource utilization while ensuring low-latency communication between connected devices. It stands as an essential component in disaggregated compute environments, driving down latency and operational costs.
The ADQ35 digitizer is designed for high-throughput applications, featuring a dual-channel configuration capable of achieving a sampling rate up to 10 GSPS. This 12-bit digitizer is tailored for applications that require simultaneous data streams and efficient high-speed data transfer, making it ideal for use in advanced signal analysis.
The bus converter module transforms wide initiator data buses to smaller target data buses or vice-versa. A narrow target on a wide bus, only requires external logic and no internal design changes. * APB: 32-bit wide initiator data buses to 16-bit target data buses. * AHB: 64-bit wide initiator data buses to 32-bit target data buses. * AXI: 256-bit wide initiator data buses to 64-bit target data buses A wide target on a narrow bus, only requires external logic and no internal design changes. * APB: 16-bit wide initiator data buses to 32-bit target data buses. * AHB: 32-bit wide initiator data buses to 64-bit target data buses. * AXI: 64-bit wide initiator data buses to 256-bit target data buses.
Overview: The Multi-Protocol Accelerator IP is a versatile technology designed to support low latency and high bandwidth accelerators for efficient CPU-to-device and CPU-to-memory communication. It also enables switching for fan-out to connect more devices, memory pooling for increased memory utilization efficiency, and provides memory capacity with support for hot-plug, security enhancements, persistent memory support, and memory error reporting. Key Features:  CXL 3.0 Support: Compliant with CXL spec V3.X/V2.X  PCIe Compatibility: Supports PCIe spec 6.0/5.0  CPI Interface: Support for CPI Interface  AXI Interface: Configurable AXI master, AXI slave  Bus Support: PIPE/FLEX bus, Lane x1,x2,x4,x8,x16  Protocol Support: Gen3, Gen4, Gen5 & Gen6, Fallback Mode  Register Checks: Configuration and Memory Mapped registers  Dual Mode: Supports Dual Mode operation  Transfer Support: HBR/PBR & LOpt Transfers, Standard Cache and Mem Transfers  CXL Support: Can function as both CXL host and device  Data Transfer: Supports Standard IO, 68Byte Flit, and 256Byte Flit Transfers  FlexBus Features: FlexBus Link Features, ARB/MUX, ARB/MUX Bypass  Optimization: Latency Optimization, Credit Return Forcing, Empty Flits (Latency Optimized)  Power Management: Supports Power Management features  Enhancements: CXL IDE, RAS Features, Poison & Viral Handling, MLD/SLD  Testing: Compliance Testing and Error Scenarios support
SkyeChip's Coherent Network-on-Chip (NOC) is a scalable networking solution aimed at systems where memory coherency is critical. Engineered for many-core setups, it effectively mitigates routing congestion through innovative architectural strategies. This NOC is capable of operating at frequencies up to 2GHz, aligning with high-speed data demands while supporting a range of protocols, including ACE and CHI. Well-suited for partitioned interconnect systems, it surgically meshes with both SkyeChip's Non-Coherent NOC and various proprietary coherence protocols. Its strength in maintaining coherency makes it ideal for applications in computing environments that require seamless communication across cores and memory subsystems.
The NMP-750 is a high-performance accelerator designed for edge computing, particularly suited for automotive, AR/VR, and telecommunications sectors. It boasts an impressive capacity of up to 16 TOPS and 16 MB local memory, powered by a RISC-V or Arm Cortex-R/A 32-bit CPU. The three AXI4 interfaces ensure seamless data transfer and processing. This advanced accelerator supports multifaceted applications such as mobility control, building automation, and multi-camera processing. It's designed to cope with the rigorous demands of modern digital and autonomous systems, offering substantial processing power and efficiency for intensive computational tasks. The NMP-750's ability to integrate into smart systems and manage spectral efficiency makes it crucial for communications and smart infrastructure management. It helps streamline operations, maintain effective energy management, and facilitate sophisticated AI-driven automation, ensuring that even the most complex data flows are handled efficiently.
Overview: The Secure Boot IP is a turnkey solution that provides a secure boot facility for an SoC. It implements the Post Quantum secure Leighton-Micali Signature (LMS) as specified in NIST SP800-208. The Secure Boot IP operates as a master or slave peripheral to an Application Processor, serving as a secure enclave that securely stores keys to ensure their integrity and the integrity of the firmware authentication process. Features:  Post Quantum Secure LMS Signature: Utilizes a robust Post-Quantum secure algorithm for enhanced security.  Firmware Updates: Supports up to 32 thousand firmware updates with a minimal signature size of typically less than 5KBytes.  SESIP Level 3 Pre-Certification: Pre-certified to SESIP Level 3 for added security assurance.  RTL Delivery: Delivered as RTL for ease of integration into SoC designs.  Proprietary IP: Based on proprietary IP with no 3rd party rights or royalties. Operation: The Secure Boot IP operates as a master, managing the boot process of the Application Processor to ensure that it only boots from and executes validated and authenticated firmware. The Secure Boot IP also functions as a slave peripheral, where the Application Processor requests validation of the firmware as part of its boot process, eliminating the need for managing keys and simplifying the boot process. Applications: The Secure Boot IP is versatile and suitable for a wide range of applications, including but not limited to:  Wearables  Smart/Connected Devices  Metrology  Entertainment Applications  Networking Equipment  Consumer Appliances  Automotive  Industrial Control Systems  Security Systems  Any SoC application that requires executing authenticated firmware in a simple but secure manner.
The Advanced eXtensible Interface(AXI) bus is a high-performance parallel bus that connects on-chip peripheral circuits (or IP blocks) to processor cores. The AXI bus employs "channels" to divide read and write transactions into semi-independent activities that can run at their own pace. The Read Address and Read Data channels send data from the target to the initiator, whereas the Write Address, Write Data, and Write Response channels transfer data from the initiator to the target.
Axelera AI has crafted a PCIe AI acceleration card, powered by their high-efficiency quad-core Metis AIPU, to tackle complex AI vision tasks. This card provides an extraordinary 214 TOPS, enabling it to process the most demanding AI workloads. Enhanced by the Voyager SDK's streamlined integration capabilities, this card promises quick deployment while maintaining superior accuracy and power efficiency. It is tailored for applications that require high throughput and minimal power consumption, making it ideal for edge computing.
The Tianqiao-70 is engineered for ultra-low power consumption while maintaining robust computational capabilities. This commercial-grade 64-bit RISC-V CPU core presents an ideal choice for scenarios demanding minimal power usage without conceding performance. It is primarily designed for emerging mobile applications and devices, providing both economic and environmental benefits. Its architecture prioritizes low energy profiles, making it perfect for a wide range of applications, including mobile computing, desktop devices, and intelligent IoT systems. The Tianqiao-70 fits well into environments where conserving battery life is a priority, ensuring that devices remain operational for extended periods without needing frequent charging. The core maintains a focus on energy efficiency, yet it supports comprehensive computing functions to address the needs of modern, power-sensitive applications. This makes it a flexible component in constructing a diverse array of SoC solutions and meeting specific market demands for sustainability and performance.
The Speedster7t FPGA family is crafted for high-bandwidth tasks, tackling the usual restrictions seen in conventional FPGAs. Manufactured using the TSMC 7nm FinFET process, these FPGAs are equipped with a pioneering 2D network-on-chip architecture and a series of machine learning processors for optimal high-bandwidth performance and AI/ML workloads. They integrate interfaces for high-paced GDDR6 memory, 400G Ethernet, and PCI Express Gen5 ports. This 2D network-on-chip connects various interfaces to upward of 80 access points in the FPGA fabric, enabling ASIC-like performance, yet retaining complete programmability. The product encourages users to start with the VectorPath accelerator card which houses the Speedster7t FPGA. This family offers robust tools for applications such as 5G infrastructure, computational storage, and test and measurement.
Overview: PCIe Gen6 is a high-speed, layered protocol interconnect interface supporting speeds up to 64GT/s, featuring multi-lanes and links. The Transport, Data Link, and Physical layers specified in the PCIe specification are implemented, along with PIPE interface logic connecting to PHY and AXI Bridging logic for application connectivity. Specifications:  Supports PCIe Gen 6 and Pipe 5.X Specifications  Core supports Flit and non-Flit Mode  Lane Configurations: X16, X8, X4, X2, X1  AXI MM and Streaming supported  Supports Gen1 to Gen6 modes  Data rate support of 2.5 GT/s, 5 GT/s, 8 GT/s, 16 GT/s, 32 GT/s, 64 GT/s  PAM support when operating at 64GT/s  Encoding/Decoding Support: 8b/10b, 128b/130b, 1b/1b  Supports SerDes and non-SerDes architecture  Optional DMA support as plugin module  Support for alternate negotiation protocol  Can operate as an endpoint or root complex  Lane polarity control through register  Lane de-skew supported  Support for L1 states and L0P  Support for SKP OS add/removal and SRIS mode  No equalization support through configuration  Deemphasis negotiation support at 5GT/s  Supports EI inferences in all modes  Supports PTM, OBFF, MSI, MSIX, Power management, and all message formats
KPIT's expertise in AUTOSAR & Adaptive AUTOSAR Solutions empowers automakers to develop vehicles that are not only highly intelligent but also highly adaptable to technological advancements. By leveraging their extensive knowledge in middleware integration, KPIT assists manufacturers in crafting scalable and flexible software environments. Through their AUTOSAR-compliant platforms, KPIT provides foundational software building blocks that allow for efficient vehicle system configuration and integration. This streamlines the development process, reducing time-to-market while ensuring vehicles are equipped with advanced functionalities to meet the growing demands of contemporary consumers. Their solutions are tailored to facilitate both traditional and next-generation automotive architectures, making them integral for automakers aiming to harness the full potential of software-defined vehicles. By aligning with KPIT, manufacturers gain access to a suite of services that accelerate the deployment of innovative automotive technologies.
Exostiv is designed to provide significant visibility inside FPGA systems, enabling engineers to conduct real-environment testing and ensure that designs function efficiently before entering production. Featuring high-speed probes capable of capturing complex signals, Exostiv supports advanced FPGA debugging through its user-centric interface and adaptable insertion flows. It facilitates both pre-silicon validation and debugging by allowing in-depth monitoring across various clock domains. With connectivity options like QSFP28 and SAMTEC ARF-6, Exostiv empowers engineers with a flexible approach to manage different prototyping platforms effectively. The scalability of Exostiv allows its users to adapt to diverse FPGA configurations by adjusting the number and type of probes. Exostiv significantly reduces the likelihood of FPGA bugs in end-user environments by enabling engineers to thoroughly validate and adjust designs dynamically as needed. Its modular setup characterizes the adaptive nature of Exostiv’s architecture, making it suitable for application-specific optimizations in complex design environments.
Our Expanded Serial Peripheral Interface (JESD251) Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface (SPI) devices. It is used to connect xSPI Master devices in computing, automotive, Internet of Things, embedded systems, and mobile system processors to non-volatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports Single Data Rate (SDR) and Double Data Rate (DDR). • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for timing reference. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands for reading or writing data for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
Silvaco provides comprehensive Automotive IP solutions tailored for automotive applications, ensuring high value and silicon-proven reliability. This line includes controllers for In-Vehicle Networks (IVN) such as FlexCAN with CAN-FD, high-speed FlexRay, and LIN standards. These elements are integral for the development of modern automotive systems with robust flexibility and performance.<br><br>In addition, Silvaco offers significant advancements in SoC subsystems, embodying critical cores, subsystems, and necessary peripherals to enhance SoC designs for automotive applications. These systems integrate SPI, UART, and DMA Controllers, creating streamlined pathways for data and control within automotive electronics.<br><br>Furthermore, Silvaco supports seamless integration of I3C systems, providing Advanced and Autonomous controller features for diverse automotive needs. Through comprehensive support and customization capabilities, Silvaco's IP solutions stand out in delivering reliability and efficiency required for next-generation automotive electronics.
Analog Circuit Works specializes in designing digital to analog converters (DACs) focused on power efficiency and performance. These DACs are engineered to align with specific bandwidth requirements, ensuring efficient driving of loads under varying operational conditions while maintaining desired accuracy across multiple applications. Their DAC portfolio includes solutions optimized for a range of resolutions and sample rates, demonstrating flexibility in design to accommodate different system requirements. By focusing on power efficiency, they have developed DACs that support enhanced operational lifespans and energy conservation, making them ideal for energy-sensitive applications. The ability to deliver application-specific DAC solutions that can seamlessly integrate into complex systems underscores their commitment to quality and precision. These converters play a crucial role in translating digital signals back to analog form, enabling high-fidelity signal processing and performance in demanding electronic environments.
Silicon Creations' Free Running Oscillators provide dependable timing solutions for a range of applications such as watchdog timers and core clock generators in low-power systems. These oscillators, crafted with compactness and efficiency in mind, support a gamut of processes from 65nm to the latest 3nm technologies. These oscillators excel in low power consumption, often requiring less than 30µW during operation. Their robust design ensures they deliver high precision over a temperature range from -40°C to 125°C with supply voltage variabilities factored in. The simplicity in design negates the need for external components, promoting easier integration and reduced overall system complexity. Precise tuning capabilities allow for accuracy levels up to ±1.5% after process trimming, ensuring outstanding performance in volatile environmental conditions. This level of reliability makes them ideal for integration into various consumer electronics, automotive controls, and other precision-demanding applications where space and power constraints are critical.
The Multi-Protocol SERDES offered by Pico Semiconductor is a versatile solution capable of handling a variety of communication protocols. This series of SERDES includes a 4-channel configuration that supports data rates up to 32Gbps, designed for integration with XAUI, RXAUI, and SGMII. It is compatible with multiple process nodes provided by foundries like TSMC and GF, offering robust performance across different semiconductor environments. These SERDES are crafted to meet high-performance metrics, capturing speeds up to 16Gbps and 6.5Gbps across various models, with advanced versions reaching up to 32Gbps. This exceptional range not only ensures compatibility with current technologies but also prepares systems for future updates, sustaining high data throughput. By delivering reliable high-speed data transmission capabilities, the Multi-Protocol SERDES from Pico Semiconductor is integral for networking, high-speed computing, and data storage applications, where efficient and speedy data transfer is paramount.
Overview: The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features:  Compliance with MIPI-CSI-2 version 3.0  Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0  Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0  Compatibility with I2C and I3C (SDR, DDR) for CCI interface  Support for C-PHY 2.0, D-PHY 2.5, A-PHY, M-PHY with configurable PHY layer  Processor Interfaces: AHB Lite/APB/AXI for configuration  Lane Merging Function for consolidating packet data in CSI-2 Receiver  De-skew detection in D-PHY and sync word detection in C-PHY  Pixel Formats Supported: YUV, RGB, and RAW data  Virtual Channels: 16 for D-PHY, 32 for C-PHY  Error detection, interleaving, scrambling, and descrambling support  Byte to pixel conversion in LLP layer Applications:  Imaging  Surveillance  Gaming  Sensor devices  Internet of Things (IoT)  Wearable devices  Virtual Reality  Augmented Reality  Automotive Systems
The Wishbone System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a versatile design approach for semiconductor IP cores. Its goal is to promote design reuse by addressing system-on-chip integration issues. This is accomplished by providing a standard interface for IP cores. This increases the system's mobility and stability, resulting in a shorter time-to-market for end users.
Silicon Creations delivers precision LC-PLLs designed for ultra-low jitter applications requiring high-end performance. These LC-tank PLLs are equipped with advanced digital architectures supporting wide frequency tuning capabilities, primarily suited for converter and PHY applications. They ensure exceptional jitter performance, maintaining values well below 300fs RMS. The LC-PLLs from Silicon Creations are characterized by their capacity to handle fractional-N operations, with active noise cancellation features allowing for clean signal synthesis free of unwanted spurs. This architecture leads to significant power efficiencies, with some IPs consuming less than 10mW. Their low footprint and high frequency integrative capabilities enable seamless deployments across various chip designs, creating a perfect balance between performance and size. Particular strength lies in these PLLs' ability to meet stringent PCIe6 reference clocking requirements. With programmable loop bandwidth and an impressive tuning range, they offer designers a powerful toolset for achieving precise signal control within cramped system on chip environments. These products highlight Silicon Creations’ commitment to providing industry-leading performance and reliability in semiconductor design.
Avalon interfaces make system design easier by allowing you to connect components in Intel FPGAs. The Avalon interface family defines interfaces that can stream high-speed data, read and write registers and memory, and operate off-chip devices. Platform Designer components incorporate these standard interfaces. Furthermore, you can include Avalon APIs in custom components, increasing the interoperability of designs.
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