SLL's Modular PHY Type 01 Suite is a PVT aware, foundry and process agnostic, PHY for use with most single-ended LVCMOS protocols up to 400 MHz DDR. The PHY has a highly modular architecture that supports x1, x4, x8, and x16 data paths. Its has process-voltage-temperature (PVT) controls that are suitable for use in hard realtime systems (zero timing interference on PVT adjustments). The PHY includes a full standard cell library abstraction. The PHY also offers >1000 configurable options at compile time, enabling coarse grain capabilities such as pin-level deskew to be enabled/disabled, along with precise fine-grain control of mapping of RTL to gates through various data paths. It supports a range of protocols such as SPI, QSPI, xSPI, eMMC, .. and allows run-time configuration via an APB3 control port. It is designed to support easy place-and-route in a broad range of customer designs.
