All IPs > Wireline Communication > Optical/Telecom
In the realm of wireline communication, Optical and Telecom semiconductor IPs play a pivotal role in ensuring robust connectivity and high-speed data transfer across global networks. As the demand for faster and more reliable communication channels grows, these semiconductor IPs provide the foundational technology for modern telecommunication systems and fiber optic networks.
Optical/Telecom semiconductor IPs are critical for enabling the efficient transmission and reception of data over optical fibers. These IPs include various components such as optical transceivers, modulators, and detectors, which convert electronic signals into optical signals and vice versa. This conversion is essential for high-speed data transmission over long distances, a crucial requirement for both enterprise and consumer telecommunications.
Beyond merely converting signals, Optical/Telecom semiconductor IPs must handle complex signal processing tasks to reduce errors, maximize bandwidth, and optimize data integrity. This includes forward error correction (FEC), signal modulation, and wavelength division multiplexing (WDM) technologies. Such capabilities are vital for sustaining the rapidly increasing data loads due to burgeoning internet usage, video streaming, and cloud computing services.
Products in this category of semiconductor IP range from highly sophisticated optical communication modules to integration-ready telecom processors. They are developed to support a broad array of applications, such as backbone internet infrastructures, 5G networks, data centers, and undersea cable systems. These cutting-edge solutions ensure that network providers can offer seamless and reliable service, empowering users with exceptional connectivity experiences. By leveraging advanced Optical/Telecom semiconductor IPs, industries can continue to innovate and meet the ever-evolving demands of a digitally connected world.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
The EW6181 GPS and GNSS solution from EtherWhere is tailored for applications requiring high integration levels, offering licenses in RTL, gate-level netlist, or GDS formats. This highly adaptable IP can be ported across various technology nodes, provided an RF frontend is available. Designed to be one of the smallest and most power-efficient cores, it optimizes battery life significantly in devices such as tags and modules, making it ideal for challenging environments. The IP's strengths lie in its digital processing capabilities, utilizing cutting-edge DSP algorithms for precision and reliability in location tracking. With a digital footprint approximately 0.05mm² on a 5nm node, the EW6181 boasts a remarkably compact size, aiding in minimal component use and a streamlined Bill of Materials (BoM). Its stable firmware ensures accurate and reliable position fixations. In terms of implementation, this IP offers a combination of compact design and extreme power efficiency, providing substantial advantages in battery-operated environments. The EW6181 delivers critical support and upgrades, facilitating seamless high-reliability tracking for an array of applications demanding precise navigation.
LightningBlu is a cutting-edge solution provided by Blu Wireless, designed specifically to serve the high-speed rail industry. This technology offers consistent, on-the-move multi-gigabit connectivity between trackside and train, which ensures a reliable provision of on-board services. These services include seamless internet access, enhanced entertainment options, and real-time information, creating a superior passenger experience while traveling. Utilizing mmWave technology, LightningBlu is capable of offering carrier-grade performance, supporting Mobility applications with remarkable consistency even at speeds exceeding 300 km/h. Such capabilities promise to revolutionize the connectivity standards within the high-speed rail networks. By integrating this advanced system, railway operators can ensure uninterrupted communication channels, thus optimizing their operations and boosting passenger satisfaction. The solution primarily operates within the mmWave spectrum of 57-71 GHz, making it a future-proof choice that aligns with the expanding global demand for high-quality, high-speed railway communications. With LightningBlu, Blu Wireless is spearheading the movement towards carbon-free, robust connectivity solutions, setting a new standard in the transportation sector.
EXTOLL's High-Speed SerDes for Chiplets is a pioneering connectivity solution crafted for seamless integration in chiplet-based systems. It serves as a core technology in facilitating swift data transfer across different chiplets, ensuring robust and efficient performance. This SerDes excels in maintaining low power consumption to optimize energy efficiency, crucial for modern computing needs. By leveraging innovative design principles, this SerDes supports mainstream technology nodes ranging from 12nm to 28nm. The flexibility provided by such support makes it a versatile choice for various high-speed data applications, ensuring adaptability to future technological advances. This capability underscores its role in facilitating heterogeneous integration, a crucial aspect in cutting-edge semiconductor environments. Furthermore, the High-Speed SerDes is crafted to cater to applications requiring reduced latency and enhanced bandwidth capabilities. Ideal for systems such as data centers and communications infrastructure, it empowers device manufacturers to implement scalable and sustainable solutions efficiently.
Designed to ensure reliable communication in automotive networks, the TSN Switch for Automotive Ethernet orchestrates robust timing and synchronization across multiple network components. It leverages Time-Sensitive Networking (TSN) standards to guarantee real-time performance and low latency, which are critical in vehicular communication systems. This switch is pivotal for managing complex data flows in automobiles, supporting advancements in autonomous vehicle technologies by enabling the seamless integration of various data streams. The switch is engineered to align with the increasing demands for high-speed connectivity in modern automobiles. With a focus on enhancing safety and operational efficiency, it allows for precise control over packet transmission, minimizing the risk of data collisions and ensuring that high-priority information is accurately transmitted through the network. This focus on precise data management makes the TSN Switch vital for deploying advanced driver-assistance systems (ADAS) and infotainment solutions. By incorporating TSN protocols, this switch enhances the reliability of vehicle networks, thereby facilitating a safer and more interconnected driving experience. It supports the integration and coordination of sensors, processors, and communication networks within the vehicle, making it an indispensable component in the development of next-generation smart transportation solutions.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
ntRSE core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
ntRSD_UF core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length, maximum number of parity symbols as well as I/O data width, internal datapath and decoding engines parallelism. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD_UF core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The core is designed and optimized for applications that need very high throughput data rates. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
ArrayNav harnesses adaptive antenna technology to enhance GNSS functionality, optimizing performance in environments with complex multichannel challenges. By leveraging various antennas, ArrayNav achieves enhanced sensitivity and coverage, significantly mitigating issues such as multipath fading. This results in greater positional accuracy even in dense urban environments known for signal interference. This adaptive approach presents an invaluable asset for automotive Advanced Driver Assistance Systems (ADAS), where high precision and rapid response times are critical. The improved antenna diversity offered by ArrayNav not only augments signal strength but also robustly rejects interference and jamming attempts, assuring consistent operation and accuracy. In terms of power efficiency, ArrayNav stands out by combining exceptional accuracy with reduced power needs, offering a flexible solution adaptable for both standalone and cloud-computing modes. This dual capability ensures that system designers have the optimal framework for developing customized solutions catering to specific application requirements. Overall, ArrayNav’s cutting-edge technology fosters improved GNSS operations by delivering enhanced sensitivity and accuracy, thereby meeting the stringent demands of modern automotive and navigation systems.
eSi-Comms brings highly parametisable communications technology to the table, offering a flexible solution that can be tailored to specific interfacing needs. This IP supports a range of communication protocols and is designed to meet critical system requirements while minimizing integration risks and optimizing performance.
The ntLDPC_8023CA (17664,14592) IP Core is defined in IEEE 802.3ca-2020 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCE_8023CA encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer when multiplied by the 14592 payload block pro-duces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1 to 6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_8023CA decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_8023CA decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
**Ceva-BX2 baseband processor IP** handles both signal-processing and control workloads with up to 16 GMACs per second performance and high-level-language programming. It supports a range of integer and floating-point data types for a wide range of baseband applications like 5G PHY control, and exploits a high degree of parallelism, but with remarkably compact code size. Optimized high-speed interfaces expedite connection to other Ceva cores or to accelerators. The Ceva-BX2 combines the capabilities of signal processing and control-code execution into a single, compact DSP. Computational speed comes from quad-32×32/octal-16×16 MACs with added support for 16×8 and 8×8 MAC operations, organized into two parallel compute engines within an 11-stage pipeline. Each compute engine can add optional half- and single-precision IEEE floating-point units. These resources are directed by a five-way VLIW instruction set architecture with optimizations for single-instruction-multiple-data (SIMD) operation, including a hardware loop buffer for kernel execution. Efficient execution of control code is aided by dynamic branch prediction and a branch target cache. On signal-processing tasks the Ceva-BX2 can reach up to 16 GMACs per second, and on control workloads it can achieve up to 5.46 CoreMark/MHz. The hardware design is optimized for speed, achieving 2 GHz operation implemented in a TSMC 7nm process node with only common standard cells and memory compilers. [**Learn more about Ceva-BX2>**](https://www.ceva-ip.com/product/ceva-bx2/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_bx2_page)
The RWM6050 is a key component designed for sophisticated wireless communication tasks, playing a critical role in Blu Wireless's high-speed connectivity solutions. This baseband modem supports real-time processing of complex tasks, enabling the higher efficiency and accuracy required for leading-edge communications infrastructure. Suitable for a wide range of applications, the RWM6050 ensures adaptive modulation and robust filtering, making it indispensable for dynamic wireless environments. The modem operates efficiently across a variety of use cases, including private network deployments and high-throughput data applications, which demand reliable and flexible connectivity. With the ability to accommodate the constantly evolving needs of wireless infrastructures, the RWM6050 provides versatile support for today's high-bandwidth requirements. Designed to integrate seamlessly with Blu Wireless's portfolio of networking solutions, the RWM6050 is optimized for performance and scalability, delivering exceptional processing capability indispensable in high-speed connectivity systems. This modem underscores Blu Wireless's commitment to offering advanced and comprehensive communication technology to its clients.
The ISDB-T Modulator delivers robust capabilities for both professional TV networks and custom point-to-point radio links. This modulator core is fully compliant with ARIB STD-B31 and ABNT NBR 15601, ensuring compatibility across a broad range of broadcasting applications. Its adaptable framework makes it suitable for diverse broadcast needs, facilitating the efficient transmission of digital television signals. Through this, broadcasters can achieve a more reliable and consistent service quality across different market segments.
PhantomBlu by Blu Wireless is engineered for defense applications, focusing on delivering high-speed, secure, and reliable tactical communications. This mmWave networking solution is designed to be independent of conventional fibre optic or cabled networks, granting greater flexibility and range. With the capability to easily integrate with both legacy platforms and upcoming technological assets, PhantomBlu ensures interoperability and robust connectivity in demanding environments. The mmWave technology used in PhantomBlu allows for multi-gigabit data transmission over significant distances, catering to the dynamic needs of military operations. It can be configured to function as a PCP (hub) or STA (client), enhancing its adaptability in tactical scenarios. This flexibility is vital for mission-critical communications, ensuring data-rich, secure connections even in highly contested environments. By employing low Probability of Detection (LPD) and Low Probability of Interception (LPI) techniques, PhantomBlu provides stealthy communication capabilities, significantly reducing the risks of detection and interference by adversaries. This advanced technology strengthens the defense sector's communication arsenal, providing reliable gigabit connectivity that supports strategic and operational superiority on the battlefield.
Designed for maximum compatibility and efficiency, the ATSC 8-VSB Modulator serves both professional TV network applications and custom point-to-point radio links. Its comprehensive compliance with ATSC A/53 8-VSB standards guarantees reliable performance across multiple broadcast scenarios. The modulator's versatile design supports varied operational environments, making it indispensable for broadcasters who require versatile and robust transmission solutions. Its emphasis on delivering flawless signal integrity ensures top-notch broadcast quality for diverse applications.
The DVB-T2 Modulator stands out with its powerful FPGA or ASIC implementation, designed to perform efficient modulation as per the DVB-T2 ETSI EN302 755 standards. This comprehensive solution encompasses all necessary functions to facilitate high-performance terrestrial broadcasts. The modulator is crafted for use in a range of broadcast networks, offering flexibility and adaptability in its application. This makes it a go-to solution for broadcasters aiming to leverage the power of DVB-T2 technology to deliver superior terrestrial broadcast services.
The Multi-channel ATSC 8-VSB Modulator enhances broadcasting flexibility by supporting multiple channels within ATSC A/53 8-VSB standards. Tailored to meet professional TV network and custom point-to-point radio link needs, this modulator core facilitates complex broadcast operations. It enables seamless integration and high-quality signal transmission across varied operational environments. By efficiently managing multiple channels, it empowers broadcasters to optimize signal delivery and enhance their overall transmission capabilities.
Designed for versatility in high-speed networking, the LineSpeed FLEX Family encompasses 100G PHY products adept at multiple roles including retiming, gearboxing, and multiplexing. Regarded for supporting modulation-independent functionality across line cards, these devices integrate easily with existing infrastructure to facilitate seamless telecom and data-center environments. By adopting common register and packaging structures, they simplify deployment while ensuring adherence to industry standards. These products enable high-performance routing and redundant link setups, meeting the demands of modern network requirements with RS-FEC supported Gearbox and Retimer options.
The 12G-SDI Playback and Capture System is a versatile FPGA-based solution designed for video capture and playback over Quad 3G-SDI interfaces. The system includes an FPGA image set for generating test patterns, capturing data from SDI inputs, and playing back over SDI. It can be integrated with a PCIe interface for enhanced performance in host machines, featuring Linux-based software and drivers to facilitate video processing. This IP core is available independently or paired with the High Performance FPGA PCIe Accelerator Card, offering a robust solution for applications requiring high-definition video handling and processing.
The ntLDPC_Ghn IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCD_Ghn decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the ITU-T G.9960 G.hn standard. The ntLDPCE_Ghn encoder IP implements a 360-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. The ntLDPCD_Ghn decoder IP implements a 360-LLR parallel systematic LDPC layered decoder. A separate off-line profiling Matlab script is used to profile the layered matrices and resolve any possible memory access conflicts. Each layer corresponds to Z=[14, 80, 360, 60, 270, 48 or 216] expanded rows of the original LDPC matrix, depending on the mode selected expansion factor. Each layer element corresponds to the active ZxZ shifted identity sub-matrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been executed. The decoder also IP features a powerful optional early termination (ET) criterion, to maintain practically the same error correction performance, while significantly increasing its throughput rate. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI.
LeWiz's Time Sensitive Network IP Core is engineered for fault-tolerant networking with precise data handling capabilities. Scalable from 1Gbps to 10Gbps, it integrates features like babbling protection and anti-masquerading to maintain network integrity and security. By utilizing the AXI standard, it offers a user-friendly interface for hardware and software implementations. This IP core is crucial for applications that require synchronized data transmission with minimal latency, such as in automotive and industrial IoT environments.
The 5G ORAN Base Station is designed to be a cornerstone in the next generation of mobile networking. With 5G, wireless communication will see unprecedented growth in data capacity and opportunities for novel wireless applications. This base station enhances the efficiency and coverage of mobile networks, fostering the growth of smart cities, connected devices, and industrial automation. It integrates seamlessly with various network architectures, making it a versatile component in the telecommunications sector.
Rockley Photonics' Multi-Channel Silicon Photonic Chipset is engineered for high-speed data transmission applications. The chipset integrates hybrid III-V DFB lasers and electro-absorption modulators into a silicon photonics framework, allowing it to support 4×106Gb/s 400 GBASE-DR4 data rates over multiple channels. This highly efficient setup delivers significant optical modulation amplitude (OMA) and maintains a low TDECQ penalty, fully complying with IEEE standards. This chipset is particularly suited for optical communications, providing the robustness and speed necessary for demanding data centers and telecommunication infrastructures.
The Digital Down Conversion (DDC) module is a critical component in signal processing, transforming downlink signals from RF to baseband for further digital processing. Including a set of intricately designed carrier selectors, frequency converters, and filters, this module ensures the accurate retrieval and processing of transmitted data. Its contribution is significant in any digital communication system demanding precise downlink signal management.
TurboConcept's DVB-S2X LDPC Decoder is engineered for high-performance satellite communication systems, offering cutting-edge error correction. This IP core facilitates robust and reliable data transmission by utilizing advanced LDPC codes, essential for maintaining signal integrity in satellite broadcasts. Designed to operate seamlessly within DVB-S2X compliant systems, the decoder ensures compatibility and adaptability across various satellite platforms. Its architecture supports both ASIC and FPGA deployments, allowing for flexible integration that caters to diverse system requirements. The DVB-S2X LDPC Decoder is an invaluable asset for broadcasters and service providers looking to enhance their satellite communication services, delivering superior error-correction performance and improving overall signal quality.
The SpaceWire Node is engineered for critical communications in space networking environments. Integrating the AXI-Stream and SpaceWire interfaces, it facilitates robust data transfer speeds up to 200Mbps. The interface compliance with ECSS-E-ST-50-12C standards assures reliability and compatibility within the standardized space systems. Equipped with an internal management interface via AXI4-Lite, the SpaceWire Node can be efficiently controlled and monitored. The node's architecture is optimized for secure and efficient routing of space-borne data, aligning with the stringent reliability requirements of the aerospace sector. It comes with extensive features such as statistic registers for monitoring and performance evaluation, ensuring the node's abilities to meet rigorous performance benchmarks. Its design reflects an emphasis on interoperability and future scalability within complex space communications networks.
Focusing on receiving capabilities, the TRV003TSM40LP Quad Rx-Path Phased Array RFIC pushes the boundaries of precision within Ku-Band frequency operations. Developed in a 40nm CMOS platform, this RFIC excels in high-frequency applications demanding accuracy and low-noise reception. Incorporating quad reception paths, the RFIC offers dual-beam and dual-polarization functionality, making it adept for electronically-steered phased array systems prevalent in satellite and communication industries. Its design promotes high integration efficiency, enhancing large-scale application viability with controlled costs. This RFIC's architecture supports significant gains in data quality and reliability, crucial for robust satellite communications. Its adaptability to dynamic environmental conditions and inherent compatibility with advanced systems underscores its integral role in expanding communication capabilities and supporting future-oriented technology initiatives in broad-scale deployment.
The TRV004TSM40LP Quad Tx-Path Phased Array RFIC is engineered for complexity and adaptability within modern communication infrastructures. It operates on a 40nm CMOS process, focusing on the Ku-Band frequency spectrum, which is ideal for electronically-steered phased array systems. Equipped with quad transmission paths, this RFIC facilitates dual-beam and dual-polarization functionality, critical for satellite communication environments that require dynamic beam steering and enhanced spatial efficiency. The design promotes high integration with minimal area consumption due to its advanced process technology, thereby offering economic viability and technical prowess. The phased array capabilities incorporated in this RFIC make it optimal for expanded communication reach and accuracy in satellite platforms. This adaptation to modern communication demands enables greater data throughput and signal reliability, catering to the needs of broadband satellite services and next-generation internet access technologies.
The P19800B is a 4GHz RF spectrometer ASIC that represents the second generation of advanced spectrometric analysis. This ASIC is built to facilitate precise RF measurement and analysis, making it an ideal choice for applications where frequency accuracy and signal integrity are paramount. Designed with advanced CMOS and SiGe technology, it promises remarkable performance under various demanding conditions. One of the standout features of the P19800B is its ability to work in complex RF environments with high selectivity and sensitivity. This makes it a valuable tool in fields like telecommunications, remote sensing, and advanced research where accurate RF detection is crucial. Built to handle expansive bandwidths, this spectrometer ASIC aids in maintaining signal clarity and reduces noise interference, enhancing overall operational efficiency. With a focus on delivering superior performance at reduced power consumption, the P19800B accommodates varying design needs. Its robust architecture ensures long-term reliability and adaptability, catering to evolving technological demands. Whether integrated into larger systems or used in standalone roles, this spectrometer ASIC is a versatile component that keeps pace with the fast-changing landscape of advanced RF technology.
An improvement upon its predecessor, the P19800C continues the legacy of precise 4GHz RF analysis by providing enhanced features for even more rigorous applications. Harnessing cutting-edge CMOS technology, this third-generation spectrometer offers a high balance of performance and efficiency, catering to sophisticated RF analysis tasks across varied settings. With an expanded feature set, the P19800C addresses the needs of modern telecommunication systems and remote diagnostics. It boasts an improved noise floor and signal resolution, allowing operators to monitor and control spectral integrity with unmatched precision. The device's versatility allows it to perform in a diverse array of environments, meeting the ever-evolving demands of the RF spectrum. Designed for low power consumption while maintaining high output, the P19800C presents a balance that suits both large and compact systems. Its architecture supports high-level integration with existing platforms, facilitating easy adoption in ongoing projects. As the spectrum's analytical demands grow, the P19800C positions itself as a critical tool in achieving superior RF management and analysis.
The P23801A is an advanced dual-channel spectrometer ASIC renowned for its capability to operate at 10GHz with polarimetric analysis features. This device is engineered specifically for environments demanding high-frequency RF measurements and nuanced spectral analysis, offering functionalities that support complex diagnostics and communication strategies. Featuring dual-channel processing, the P23801A significantly enhances spectral analysis by handling multiple inputs with precision and speed. It is particularly effective in polarimetric contexts, which demand detailed distinction between orthogonal signal components. This capability is invaluable in applications such as advanced radio astronomy, remote sensing, and high-frequency broadband communications. Capable of integrating seamlessly into existing analytic frameworks, the P23801A’s innovative design enhances signal clarity and bandwidth utilization. Its architecture facilitates a comprehensive analysis of both spectral and polarimetric data, thus providing users with a thorough understanding of the RF environment. Such versatility ensures that the P23801A remains a staple for state-of-the-art spectrum analytics.
The P19810B is a specialized correlation radiometer ASIC capable of handling signals up to 10GHz, with a focus on dual-sideband, dual-input operations across 64 channels. This ASIC delivers remarkable performance in signal detection and correlation, pivotal for fields like metrology, atmospheric science, and telecommunications. This correlation radiometer is designed to offer high sensitivity and accuracy, crucial for capturing the subtle nuances in RF signal environments required for precise measurements. The dual-sideband technology allows for greater bandwidth utilization within limited spectral resources, enhancing the effectivity of signal differentiation and analysis. Equipped with robust processing abilities, the P19810B supports complex applications that necessitate detailed correlation of signal inputs. Its multifaceted approach provides the flexibility required in modern analytic tools, ensuring that varying data types are addressed with precision. The P19810B stands as a cornerstone in environments where exactitude and robust analysis are mandatory, integrating seamlessly into larger systems to enhance performance efficiencies.
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