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All IPs > NAND Flash Controller IP Core

NAND Flash Controller IP Core

From iWave Global

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Description

iWave NAND Host Controller provides an easy interface to access NAND Flash Memory devices. This IP forms a bridge between the NAND flash and User (Processor), enabling to store, read and erase the data in NAND flash. The Controller has two different variants depending on the availability of the processor towards user side. One being the AXI complaint interface for accessing through processor and other is custom interface which can be used without the processor.

Features
  • 8-bit Asynchronous or Synchronous Interface to NAND device
  • SLC or MLC NAND Flash Memory
  • Page Size: Up-to 16KByte (Compile time configurable)
  • 16K-Byte Buffer for write data
  • 16K-Byte Buffer for read data
  • Separate Chip Select, Write Enable, Read Enable and Ready/Busy for each die and the IO signals are shared between the die
  • ECC Logic: Hamming code for 1-bit error correction and 2- bit error detection or BCH code which can correct up to 8 bit errors
  • Commands supported towards NAND Flash Memory: Read, Reset, Page Program, Block Erase and Read Status
  • Core is compliant with ONFI specification
  • Supports both processor and non-processor environments with two different variants
  • This IP will issue the necessary command address and controls all the necessary actions required to program, erase and read data using NAND flash
  • Controller supports rich set of NAND commands
  • Software support includes the standard NAND driver for Linux, u-boot and simplified baremetal NAND driver
  • Supports standard flash file systems like JFFS2 and UBIFS
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NAND Flash Controller IP Core
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