The Network Protocol Accelerator Platform (NPAP) is designed to optimize network protocol processing using FPGA technology. Developed in collaboration with Fraunhofer Heinrich-Hertz-Institute, NPAP facilitates ultra-high-speed data communication over Ethernet connections ranging from 1G to 100G. The IP core offloads TCP/UDP/IP processing to programmable logic, significantly enhancing network throughput while reducing latency. NPAP is a flexible and customizable turnkey solution suitable for both FPGA and ASIC implementations, boasting an impressive feature set that includes multiple parallel TCP engines and a robust stream interface for data handling.
This accelerator caters to environments requiring seamless and rapid data exchanges, such as smart network interface cards (SmartNICs), in-network compute acceleration, and video-over-IP setups. Supporting full TCP/UDP/IP protocol stacks implemented in HDL, the NPAP enables FPGAs to achieve line rates up to 70 Gbps, with even higher capabilities in ASIC form. Optional enhancements like DPDK stream interfaces and Corundum NIC integrations further broaden its application range, making it ideal for demanding tasks in test and measurement or automotive systems.
MLE provides a remote evaluation system for NPAP, allowing for hands-on testing in a controlled setting, thus enabling clients to assess performance before implementation. The platform's implementation includes the use of Xilinx's Zynq UltraScale+ MPSoC, leveraging cutting-edge FPGA technology to bring these high-speed communication solutions to life.
