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All IPs > Analog & Mixed Signal > Clock Synthesizer > pPLL02F Family

pPLL02F Family

From Perceptia Devies Australia

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Description

The pPLL02F Family comprises a series of comprehensive all-digital Fractional-N PLLs, designed to deliver exceptional performance in a compact footprint. These PLLs are engineered for applications requiring clock sources in moderate-speed digital systems and microprocessors, with operational frequencies reaching up to 2GHz. The pPLL02F is acclaimed for its minimal jitter, ensuring stable performance across various clocking tasks.

The family is built on advanced second-generation digital PLL technology, capable of both integer and fractional multiplications for flexible design adaptation. This technology ensures consistent performance across multiple manufacturing processes, immune to fluctuations in PVT conditions. Besides its compact size, each PLL in this family operates with reduced power consumption, making it optimal for systems with multiple PLL requirements sharing power supplies.

equipped with features such as an integrated power supply regulator and support for multi-clock domain systems, pPLL02F integrates seamlessly within SOC designs. It offers straightforward integration support and is compatible with industry-standard backend flows, facilitating its use in mainstream SoC development.

Features
  • Low jitter, suitable for many clocking applications
  • Extremely small die area (< 0.01 sq mm)
  • Output frequency up to 2GHz
  • Second-generation digital PLL architecture
  • Integer and fractional multiplication capabilities
Foundries & Process Nodes
Foundry Process Nodes
GLOBALFOUNDARIES 55nm
Intel Foundry 10nm
Samsung 55nm
TSMC 16nm
28nm
UMC 55nm
Tech Specs
Applications
  • Moderate speed digital systems
  • Microprocessors
  • General-purpose PLL
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