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All IPs > Processor > Processor Cores > SCR3 Microcontroller Core

SCR3 Microcontroller Core

From Syntacore

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Description

The SCR3 Microcontroller Core is an efficient RISC-V processor tailored for embedded applications that demand high performance in power-sensitive environments. This 32/64-bit microcontroller-class core features a sophisticated 5-stage in-order pipeline with support for atomic instructions, compressed extensions, and integer multiplication and division. The design is enriched with a dynamic branch predictor and supports up to 4-core symmetric multiprocessing for improved performance and memory coherency.\n\nThe SCR3's memory architecture includes tightly coupled memory (TCM) with error correction features, L1/L2 caches, and a configurable memory protection unit that supports various privilege modes. A robust interrupt system is facilitated by industry-standard interfaces such as AHB, AXI4, and JTAG, making it a powerhouse for real-time operating systems and heterogeneous cluster integration.\n\nApplications of the SCR3 core expand into industrial automation, IoT, smart meters, and storage devices. The processor's optimization for energy efficiency, small area, and high performance addresses the unique requirements of these fields, ensuring smooth operation of automation systems, smart home applications, and automotive systems.

Features
  • Power-sensitive optimization
  • High performance
  • Small area efficiency
Tech Specs
Class Value
Categories Processor > Processor Cores
Processor > CPU
Processor > DSP Core
Processor > Microcontroller
Processor > Building Blocks
Core ISA RV32/RV64(IM[A]C)
Pipeline 3-5 stages
Memory Subsystem Tightly-Coupled Memory (TCM) Up to 256KB, error protection — ECC
Interrupt Subsystem IPIC Up to 32 interrupt lines, PLIC Up to 1023 interrupt lines
Multicore Support (SMP) Up to 4 cores with cache coherency
Availability All Countries & Regions
Applications
  • Industrial automation
  • Internet of things
  • Storage devices
  • Smart meters
  • Automotive
  • Smart home
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