Optimized for Intel and AMD FPGAs, the Stream Buffer Controller from Enclustra facilitates efficient data transfer by bridging streams to memory-mapped DMA. This versatile IP core supports up to 16 independent streams, offering a virtual FIFO capability up to 4GB of buffer memory. It utilizes AMBA AXI4-Stream interfaces, enhancing data throughput and flexibility in various data-intensive applications.
The core is highly configurable, allowing adjustments in buffer size and addressing to meet specific project needs. Operating modes for each channel include FIFO, write, read, and ROM, providing tailored memory access solutions. This configuration is managed through a memory-mapped slave interface, making it adaptable for use with an embedded CPU or a dedicated stream configuration controller.
With support for multiple operational modes, data width conversions, and a unified bus interface, the Stream Buffer Controller is ideal for complex data handling applications like image processing and embedded systems. Its stand-alone capability makes it particularly attractive for projects aiming to minimize additional processing overhead, with a clear layout for straightforward integration into larger system designs.
