The Synthesizable Programmable Core (SPC) by ADICSYS is a soft FPGA IP tailored for integration into ASICs, SOCs, and general silicon IPs. The primary advantage of SPC is its flexibility in addressing specification errors and changes, enabling designers to incorporate customizable logic efficiently. This IP helps reduce development and verification times while enhancing debugging capabilities, ultimately accelerating time-to-market for critical system components.
SPC operates seamlessly within standard ASIC CAD tools and methods, imposing no constraints on the ASIC design flow. It offers compatibility with various stages of design processes, including simulation, synthesis, backend, and testing, thus delivering a transparent experience without introducing design phase delays. The IP is highly portable, thanks to its RTL composition, which circumvents the need for silicon-proofing new instances. This approach leverages standard cells to facilitate ease of synthesis with minimal physical design constraints.
In addition to its portability and design flexibility, the SPC provides extensive customization opportunities, such as late-stage modifications and variable scale inclusion. It's based entirely on standard cell ASIC technology, benefiting from powerful modern CAD tools to extend the ASIC lifecycle. Through offering the ability to implement upgrades or modifications post-production, the SPC aids in future-proofing devices and accommodating potential late-stage project adjustments.
