The TimeServo System Timer is an advanced IP core designed to provide high-resolution timekeeping for FPGAs. With its sub-nanosecond resolution and sub-microsecond accuracy, it is particularly suited for applications like packet timestamping, which demands precise time measurement. The core's PI-DPLL allows it to synchronize its operations using an external Pulse Per Second (PPS) signal.
One of the key features of TimeServo is its ability to handle multiple independent clock domains, offering flexibility with up to 32 runtime-switchable outputs. This capability makes it a versatile solution for applications requiring different timing formats, including binary, IEEE ordinary, and IEEE transparent modes. The internal logical 120-bit phase accumulator and a digital phase-locked loop ensure that timekeeping operations are conducted with the utmost precision.
Engineered for seamless integration, the timer’s capabilities can be further extended with the TimeServoPTP solution, providing a complete IEEE-1588v2/PTP ordinary slave device. This makes the TimeServo System Timer a comprehensive tool for network time synchronization tasks in FPGA contexts.
