All IPs > Wireline Communication > Ethernet
The wireline communication category of Ethernet semiconductor IPs is pivotal in the development of modern high-speed data transfer technologies. Ethernet technology, a mainstay in networking, facilitates the connection of computers to local networks (LANs) and wide-area networks (WANs). This category focuses on semiconductor IPs that implement Ethernet protocols, enabling manufacturers to integrate high-performance networking capabilities into their electronic devices efficiently and cost-effectively.
Ethernet semiconductor IPs are crucial for designing networking chips used in a variety of enterprise, consumer, and industrial applications. These IPs provide the foundational building blocks for implementing Ethernet standards from legacy 10/100 Mbps to the latest Multi-Gigabit Ethernet, including 1G, 10G, 25G, and beyond. Enhanced with features like Energy Efficient Ethernet (EEE) and advanced security mechanisms, these semiconductor IPs ensure optimized performance and reliability essential for today’s data-intensive applications.
The products in this category include a diverse range of Ethernet MAC(medium access control) cores, PHY(physical layer) cores, and network interface controllers, among others. These components work together to manage data packet transmission over Ethernet networks, ensuring seamless communication between connected devices. Designers leverage these Ethernet IPs to create routers, switches, servers, and Internet of Things (IoT) devices that require sophisticated data handling capabilities.
By integrating Ethernet semiconductor IPs, developers and OEMs can achieve faster time-to-market while reducing design risk and cost. These IPs are pre-verified, ensuring compliance with the current Ethernet standards, which accelerates the development cycle for networking equipment. Consequently, Ethernet semiconductor IPs are indispensable for any entity aiming to innovate within the competitive landscape of wireline communication technologies.
Axelera AI's Metis AIPU PCIe AI Accelerator Card is engineered to deliver top-tier inference performance in AI tasks aimed at heavy computational loads. This PCIe card is designed with the industry’s highest standards, offering exceptional processing power packaged onto a versatile PCIe form factor, ideal for integration into various computing systems including workstations and servers.<br><br>Equipped with a quad-core Metis AI Processing Unit (AIPU), the card delivers unmatched capabilities for handling complex AI models and extensive data streams. It efficiently processes multiple camera inputs and supports independent parallel neural network operations, making it indispensable for dynamic fields such as industrial automation, surveillance, and high-performance computing.<br><br>The card's performance is significantly enhanced by the Voyager SDK, which facilitates a seamless AI model deployment experience, allowing developers to focus on model logic and innovation. It offers extensive compatibility with mainstream AI frameworks, ensuring flexibility and ease of integration across diverse use cases. With a power-efficient design, this PCIe AI Accelerator Card bridges the gap between traditional GPU solutions and today's advanced AI demands.
The "1G to 224G SerDes" solution from Alphawave Semi offers an extensive range of multi-standard connectivity IPs, designed to deliver optimal high-speed data transfer. These full-featured building blocks can be integrated into various chip designs, providing scalability and reliability across numerous protocols and standards. Supporting data rates from 1 Gbps to 224 Gbps, this SerDes solution accommodates diverse signaling schemes, including PAM2, PAM4, PAM6, and PAM8. Alphawave Semi's SerDes IP is engineered to meet the demands of modern communication systems, ensuring connectivity across a wide spectrum of applications. These include data centers, telecom networks, and advanced networking systems where high data transfer speeds are a necessity. This solution is crafted with energy efficiency in mind, helping reduce power consumption while maintaining a robust data connection. The SerDes solutions come equipped with advanced features like low latency and noise resilience, which are crucial for maintaining signal integrity over various transmission distances. This facilitates seamless integration into enterprises looking to boost their processing capabilities while minimizing downtime and operational inefficiencies. These capabilities make Alphawave Semi's SerDes IP a vital component in the evolving landscape of technology connectivity applications.
Ethernet MAC 10M/100M/1G/2.5G IP is a solution that enables the host to communicate data using the IEEE 802.3 standard for 10M, 100M, 1G, 2.5G speeds and is suited for use in networking equipment such as switches and routers. The Client-side interface for the IP is AXI-S and the Ethernet MAC IP comes with GMII, RGMII or MII interfaces on the PHY side. The Ethernet MAC 10M/100M/1G/2.5G IP features a compact and low latency solution, it is highly configurable and can optionally include IEEE 1588 Timestamping Unit (TSU). The Silicon agnostic Ethernet MAC IP, suitable for ASICs and FPGAs, is prepared for easy integration with Ethernet PCS 10M/ 100M/1G/2.5G IP from Comcores.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
The ARINC 818 Product Suite is a comprehensive solution designed for professionals working with advanced avionics systems. It provides a robust framework for implementing, testing, and simulating ARINC 818 systems. The product suite includes a variety of tools and resources tailored for the lifecycle of ARINC 818 systems, ensuring that clients can develop mission-critical systems with confidence. With a primary focus on performance and scalability, the ARINC 818 Product Suite is developed to cater to complex requirements and to seamlessly integrate within existing technology stacks. Users benefit from its extensive compatibility and the ability to manage high-speed data effectively, making it a vital asset for those working in aviation and defense sectors.
Time-Triggered Ethernet (TTEthernet) is a pioneering development by TTTech that offers deterministic Ethernet capabilities for safety-critical applications. This technology supports real-time communication between network nodes while maintaining the standard Ethernet infrastructure. TTEthernet enables reliable data delivery, with built-in mechanisms for fault tolerance that are vital for spaces like aviation, industrial automation, and space missions. One of the key aspects of TTEthernet is its ability to provide triple-redundant communication, ensuring network reliability even in the case of multiple failures. Licensed for significant projects such as NASA's Orion spacecraft, TTEthernet demonstrates its efficacy in environments that require dual fault-tolerance. As part of the ECSS engineering standard, the protocol supports human spaceflight standards and integrates seamlessly into space-based and terrestrial networks. The application of TTEthernet spans across multiple domains due to its robust nature and compliance with industry standards. It is particularly esteemed in markets that emphasize the importance of precise time synchronization and high availability. By using TTEthernet, companies can secure communications in networks without compromising on the speed and flexibility inherent to Ethernet-based systems.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
RapidGPT is a next-generation electronic design automation tool powered by AI. Designed for those in the hardware engineering field, it allows for a seamless transition from ideas to physical hardware without the usual complexities of traditional design tools. The interface is highly intuitive, engaging users with natural language interaction to enhance productivity and reduce the time required for design iterations.\n\nEnhancing the entire design process, RapidGPT begins with concept development and guides users through to the final stages of bitstream or GDSII generation. This tool effectively acts as a co-pilot for engineers, allowing them to easily incorporate third-party IPs, making it adaptable for various project requirements. This adaptability is paramount for industries where speed and precision are of the essence.\n\nPrimisAI has integrated novel features such as AutoReview™, which provides automated HDL audits; AutoComment™, which generates AI-driven comments for HDL files; and AutoDoc™, which helps create comprehensive project documentation effortlessly. These features collectively make RapidGPT not only a design tool but also a comprehensive project management suite.\n\nThe effectiveness of RapidGPT is made evident in its robust support for various design complexities, providing a scalable solution that meets specific user demands from individual developers to large engineering teams seeking enterprise-grade capabilities.
Digital Predistortion (DPD) is a sophisticated technology crafted to optimize the power efficiency of RF power amplifiers. The flagship product, FlexDPD, presents a complete, adaptable sub-system that can be customized to any ASIC or FPGA/SoC platform. Thanks to its scalability, it is compatible with various device vendors. Designed for high performance, this DPD solution significantly boosts RF efficiencies by counteracting signal distortion, ensuring clear and effective transmission. The core of the DPD solution lies in its adaptability to a broad range of systems including 5G, multi-carrier platforms, and O-RAN frameworks. It's built to handle transmission bandwidths exceeding 1 GHz, making it a versatile and future-proof technology. This capability not only enhances system robustness but also offers a seamless integration pathway for next-generation communication standards. Additionally, Systems4Silicon’s DPD solution is field-tested, ensuring reliability in real-world applications. The solution is particularly beneficial for projects that demand high signal integrity and efficiency, providing a tangible advantage in competitive markets. Its compatibility with both ASIC and FPGA implementations offers flexibility and choice to partners, significantly reducing development time and cost.
The EZiD211, also known as Oxford-2, is a leading-edge demodulator and modulator developed by EASii IC to facilitate advanced satellite communications. It embodies a sophisticated DVB-S2X wideband tuner capable of supporting LEO, MEO, and GEO satellites, integrating proprietary features like Beam Hopping, VLSNR, and Super Frame applications. With EZiD211 at the helm, satellite communications undergo a transformation in efficiency and capacity, addressing both current and future demands for fixed data infrastructures, mobility, IoT, and M2M applications. Its technological forefront facilitates seamless operations in varied European space programs, validated by its full production readiness. EZiD211's design offers a unique capability to manage complex satellite links, enhance performance, and ensure robust and reliable data transmission. EASii IC provides comprehensive support through evaluation boards and samples, allowing smooth integration and testing to meet evolving satellite communication standards.
Digital Blocks' AXI4 DMA Controller is a robust solution designed for transferring data efficiently between systems over the AXI4 interface. Supporting up to 16 independent channels, it excels in high data throughput both for small and large data sets. Its capabilities are extended with advanced DMA features, allowing custom configurations to minimize silicon usage and licensing costs. Precise control over DMA operations is facilitated through its customizable settings, supporting a flexible range of interface buses and addressing modes.
The SerDes PHY is a high-performance solution designed to facilitate high-speed data transmission within sophisticated data infrastructures. Offering support for various signaling options from 28G to 224G, this PHY is engineered to provide reliable, high-bandwidth communication required by next-generation AI and data centers. With the highly adaptable architecture, it ensures seamless integration into multiple designs including those that require long reach and very short reach plus options. Its design emphasis is on achieving low latency and high reliability, making it indispensable in environments demanding maximum uptime and efficiency. Incorporating cutting-edge mixed signal DSP technology, the SerDes PHY can effectively manage high data rates, making it ideal for switch fabric ASICs, AI ASICs, and machine learning applications. The underlying technology is manufactured on advanced process nodes, which enhances both the performance and power efficiency of the solutions. Through its innovative design, the SerDes PHY supports a range of applications that include interconnecting AI clusters, supporting cloud infrastructures, and enhancing hyperscale networking systems. It stands out for its ability to support seamless operation at various data rates, ensuring future-proofing for scaling AI and data center demands. Utilizing this PHY can enable the development of high-performance, optimized solutions that push the boundaries of current technological capabilities.
The ePHY-5616 is a versatile SerDes solution tailored to support data rates from 1 to 56Gbps, making it suitable for a variety of applications across different technology sectors. Designed with flexibility in mind, it operates efficiently on 16nm and 12nm nodes, providing scalability to adapt to varying insertion losses and data rate requirements. This product is engineered to deliver superior performance in enterprise equipment such as routers and switches, as well as for network interface cards. Its robustness in Clock Data Recovery (CDR) and minimal latency make it a preferred choice for data centers that require reliable high-speed data transmissions. The ePHY-5616 capitalizes on advanced DSP techniques to ensure extreme resistance to interference and data rate variability, offering a scalable architecture that can be customized to fit specific deployment scenarios. The inclusion of a comprehensive set of diagnostic features further aids in system bring-up and performance tuning, enabling operators to maintain optimal operational conditions.
The HOTLink II Product Suite is designed to facilitate high-speed connectivity and data transfer in demanding environments. This suite of products offers robust solutions for those needing reliable and fast data links, catering to industries where performance and precision are crucial. As part of Great River Technology's offerings, HOTLink II stands out by providing comprehensive support throughout product lifecycles and ensuring compatibility with various systems. With HOTLink II, users can expect exceptional levels of performance and reliability thanks to its advanced design, which is geared towards meeting the rigorous demands of aerospace and defense applications. Whether implementing new systems or upgrading existing infrastructures, the HOTLink II Product Suite provides the versatility and capability needed to meet diverse clients' needs. The suite is particularly beneficial for engineers requiring high-performance link solutions that integrate seamlessly within larger systems, enhancing operational effectiveness and efficiency. It includes all the necessary tools to ensure a smooth deployment process while minimizing potential downtime associated with new technology integration.
VeriSyno Microelectronics Co., Ltd. offers a comprehensive range of high-speed interface solutions. These IPs are well-suited for systems requiring reliable and quick data transfer capabilities. Their high-speed interface technologies support various advanced manufacturing processes, from 28nm to 90nm, making them adaptable to modern semiconductor needs. They also provide customized migration services to meet specific process requirements ranging from 90nm to 180nm, ensuring optimal performance across different technology standards. The high-speed interfaces offered by VeriSyno cater to applications that demand elevated data processing rates and robust connectivity. These solutions facilitate seamless integration with components like USB, DDR, MIPI, HDMI, PCIe, and SATA. Each interface is engineered to minimize power consumption while maximizing throughput, allowing for efficient and effective communication between digital systems. By providing adaptable IP solutions that meet the rigorous demands of current and future electronic devices and systems, VeriSyno aims to enhance both the speed and reliability of data transmission. Their high-speed interfaces not only meet current industry standards but also pave the way for innovation, encouraging the development of smarter and faster technologies of tomorrow.
The Digital Radio (GDR) from GIRD Systems is an advanced software-defined radio (SDR) platform that offers extensive flexibility and adaptability. It is characterized by its multi-channel capabilities and high-speed signal processing resources, allowing it to meet a diverse range of system requirements. Built on a core single board module, this radio can be configured for both embedded and standalone operations, supporting a wide frequency range. The GDR can operate with either one or two independent transceivers, with options for full or half duplex configurations. It supports single channel setups as well as multiple-input multiple-output (MIMO) configurations, providing significant adaptability in communication scenarios. This flexibility makes it an ideal choice for systems that require rapid reconfiguration or scalability. Known for its robust construction, the GDR is designed to address challenging signal processing needs in congested environments, making it suitable for a variety of applications. Whether used in defense, communications, or electronic warfare, the GDR's ability to seamlessly switch configurations ensures it meets the evolving demands of modern communications technology.
The Ultra-Low Latency 10G Ethernet MAC from Chevin Technology is designed for FPGA applications that prioritize speed and efficiency. This IP core achieves exceptional data transfer rates with minimized latency, making it ideal for projects where time-sensitive communication is critical. Its design focuses on reducing the complexity and power consumption typical of high-speed Ethernet solutions. A key advantage of this ultra-low latency MAC is its ability to operate without the need for additional CPUs or software, thanks to its all-logic architecture. This not only simplifies integration but also reduces the overall footprint of the design, allowing more space for other functionalities within the FPGA. Targeting industries such as defense and data storage, this Ethernet MAC ensures high reliability and performance. It allows for seamless implementation into various FPGA platforms, demonstrating Chevin Technology's commitment to versatile and adaptable design solutions that meet specific industry needs.
High-Speed SerDes for Chiplets is engineered to provide exceptional interconnect solutions tailored for chiplet architectures. This product offers ultra-low power consumption while maintaining high data transfer rates, essential for modern multi-die systems. By facilitating rapid communication between chiplets, it enhances overall system efficiency and performance. This SerDes solution is optimized for integration with a range of tech nodes, ensuring compatibility with various semiconductor manufacturing processes. Its design is focused on providing robust data integrity and reducing latency, which are crucial for efficient system operation in complex, integrated circuits. High-Speed SerDes addresses the growing demand for advanced interconnect solutions in chiplet architectures, making it an indispensable tool for developing next-generation semiconductor devices. Its ability to support high data throughput while keeping power use minimal makes it a standout choice in high-performance design environments.
The LightningBlu solution from Blu Wireless is a premier mmWave technology specifically designed to cater to the rigorous demands of high-speed rail connectivity. It provides multi-gigabit, continuous communication solutions between tracksides and trains. This connectivity ensures reliable on-board services such as internet access, entertainment, and passenger information systems. The versatile solution is engineered to perform seamlessly even at speeds greater than 300 km/h, enhancing the passenger experience by delivering consistent, high-speed internet and data services. Built to leverage the 57-71 GHz mmWave spectrum, LightningBlu guarantees carrier-grade connectivity that accommodates the surge of digital devices passengers bring aboard. The technology facilitates a robust communication network that empowers high-speed rail services amidst challenging dynamics and ensures that passengers enjoy uninterrupted service across wide geographic expanses. This significant technical prowess positions LightningBlu as an indispensable asset for the future of rail transport, effectively shaping the industry's move towards digital transformation. With a focus on sustainability, LightningBlu also supports the transition to a carbon-free transport ecosystem, providing an advanced data communication solution that interlinks seamless connectivity with environmentally responsible operation. Its application in rail systems positions it at the heart of modernizing rail services, fostering an era of enhanced rider satisfaction and operational efficiency.
The 10G Ethernet MAC and PCS from Chevin Technology offers a high-performance solution for FPGA-based applications requiring efficient data transfer. Designed to maximize link utilization, this IP core provides sustained high throughput with minimal latency, utilizing a compact architecture that saves space and power. The core is suitable for environments that demand reliable Ethernet connectivity, ensuring optimal performance in FPGA designs. This IP core is particularly beneficial for energy-conscious applications as it operates with lower power consumption compared to solutions requiring additional CPU or software components. The design is optimized for both Intel and AMD FPGAs, providing a versatile solution that is easy to integrate into existing projects. By providing robust data transfer capabilities, the 10G Ethernet MAC and PCS core supports cutting-edge applications in fields such as industrial imaging, data storage, and scientific research. Its design ensures that users can implement multiple cores within a single FPGA, offering flexibility and scalability for a range of Ethernet needs.
The 10G TCP Offload Engine is a sophisticated high-performance solution designed to offload TCP processing from the host CPU. Utilizing ultra-low latency technology, this IP incorporates a TCP/UDP stack integrated into high-speed FPGA hardware, ideal for networking environments demanding efficient processing and high throughput. Designed to handle up to 16,000 concurrent sessions, it manages TCP stacks within an impressive 77 nanoseconds, offering unmatched performance without straining the CPU. The engine supports 10 Gigabit Ethernet connectivity, ensuring seamless network integration and optimal data flow. With features like full TCP stack implementation and zero host CPU processing requirement, the offload engine is perfect for real-time cloud computing and AI networking applications, significantly reducing power consumption and enhancing bandwidth utilization. Equipped with a range of additional functions, such as large send offload and checksum offload, it optimizes network operations by eliminating bottlenecks typically associated with software-based solutions. It's an excellent choice for data centers and enterprise environments struggling with CPU bottlenecks.
The DisplayPort 1.4 core provides a comprehensive solution for DisplayPort requirements, implementing both source and sink capabilities. It supports link rates ranging from 1.62 Gbps to 8.1 Gbps, fitting standard DisplayPort and eDP scenarios efficiently. Users can take advantage of its support for multiple lanes, specifically 1, 2, and 4 lanes configurations, enabling versatile video interface options such as Native and AXI stream interfaces. This facilitates a strong multimedia performance, catering to both Single Stream Transport (SST) and Multi Stream Transport (MST) modes. The video processing toolkit accompanying this IP aims at aiding users in diverse video operations. These tools include a timing generator, a versatile test pattern generator, and crucial video clock recovery mechanisms. To simplify the integration into various systems, the IP is supported across a broad range of FPGA devices, including AMD and Intel lines, providing users with choice and flexibility for their specific application needs. Notably, it supports diverse video formats and color spaces, such as RGB, YCbCr 4:4:4, 4:2:2, and 4:2:0 at pixel depths of 8 and 10 bits. Secondary data packets handling audio and metadata enhance its multimedia capabilities. Furthermore, Parretto offers the source code on GitHub for ease of custom development, ensuring developers have the tools they need to adapt the IP to their unique systems.
The Ethernet Real-Time Publish-Subscribe (RTPS) IP Core is crafted to provide a comprehensive hardware implementation of the Ethernet RTPS protocol. This core is indispensable in real-time communication networks that require the seamless integration of data streams with minimal latency. It ensures low-latency operation and efficient data exchange, which are crucial for mission-critical applications. Designing systems capable of maintaining integrity and synchronous data dissemination is the primary goal of this IP core. It is optimally structured to ensure swift data processing, making it a key component in systems where real-time data publishing and subscription minimize response delays. The RTPS IP Core stands out as a strategic solution for real-time networking in communication-intensive industries.
The Time-Triggered Protocol (TTP) is a cornerstone of TTTech's offerings, designed for high-reliability environments such as aviation. TTP ensures precise synchronization and communication between systems, leveraging a time-controlled approach to data exchange. This makes it particularly suitable for safety-critical applications where timing and order of operations are paramount. The protocol minimizes risks associated with communication errors, thus enhancing operational reliability and determinism. TTP is deployed in various platforms, providing the foundation for time-deterministic operations necessary for complex systems. Whether in avionics or in industries requiring strict adherence to real-time data processing, TTP adapts to the specific demands of each application. By using this protocol, industries can achieve dependable execution of interconnected systems, promoting increased safety and reliability. In particular, TTP's influence extends into integrated circuits where certifiable IP cores are essential, ensuring compliance with stringent industry standards such as RTCA DO-254. Ongoing developments in TTP also include tools and methodologies that facilitate verification and qualification, ensuring that all system components communicate effectively and as intended across all operating conditions.
AccelerComm’s High PHY Accelerators serve as the cornerstone of their full physical layer offerings. These accelerators, available as ASIC and FPGA-ready IP cores, integrate with customer solutions using standard interfaces, bolstered by bit-accurate models for simulation and verification, expediting system-level integration with minimum risk. Incorporating space-hardened platforms from industry leaders, these accelerators leverage patented algorithms to maximize throughput and minimize both power consumption and hardware demands. This ensures they are perfectly suited for deploying in high-performance, space-specific applications where environmental factors impose unique restrictions. Designed to be adaptable across multiple platforms, these accelerators capitalize on years of technological advancement to provide efficient solutions, thereby elevating the capabilities of modern communication systems to meet and exceed the sophisticated demands of the 5G and 6G landscape.
The High Speed Data Bus (HSDB) IP Core is engineered to provide a seamless PHY and Mac layer implementation that is fully compatible with the HSDB standard. It is specifically designed for easy integration, offering a user-friendly interface that can be incorporated into a variety of systems without a hitch. Known for its exceptional throughput, this core ensures F-22 aircraft compatibility, making it a robust choice in demanding avionics applications. This IP core excels in establishing reliable high-speed communication links, crucial for applications where data integrity and timing are paramount. By facilitating streamlined data flow with minimized latency, the HSDB IP Core enhances operational efficiency significantly. It is an ideal solution for environments requiring stringent adherence to high data rates and precise timing protocols.
The GNSS ICs AST 500 and AST GNSS-RF are crafted by Accord Software & Systems as part of their extensive lineup of GNSS-centric products. These ICs are pivotal for applications requiring precision navigation, especially where stringent environmental and operational parameters are paramount. Built for robustness and accuracy, these ICs thrive under challenging conditions, providing users with reliable GPS and GNSS solutions. The AST 500 and AST GNSS-RF are tailored for seamless integration into complex systems, ensuring they meet the high demands of precision and performance. They offer enhanced capabilities for both time-sensitive and location-critical applications across various sectors, including aerospace, defense, and commercial industries. These integrated circuits leverage Accord's cutting-edge technology to maintain precise positioning and timing, which is essential for applications demanding unfailing synchronization and navigation. These ICs support various navigation systems and are designed to accommodate multiple constellation signals, including GPS, GLONASS, and more. Their comprehensive design encompasses complete GNSS functionality, which includes signal acquisition, tracking, and data output, ensuring continuous performance even in environments with high interference or dynamics. Providing both user-friendly integration and exceptional performance, these ICs form the backbone for Accord's reliable GNSS modules. In addition to interoperability across a range of navigation systems, the ICs are optimized for low-power consumption, making them suitable for portable and power-sensitive applications. This energy efficiency, coupled with advanced signal processing capabilities, ensures that the AST 500 and AST GNSS-RF remain at the forefront of GNSS technology.
The nxFeed Market Data System is an FPGA-based feed handler designed to significantly enhance the efficiency of market data processing. By handling the data feeds directly on an FPGA, nxFeed reduces latency and server load. This system is ideal for financial applications requiring ultra-low latency data feeds, providing a streamlined, plug-and-play solution that integrates seamlessly with existing trading infrastructure. The system processes raw market data from various exchanges, normalizes it, and makes it available to applications via a simplified API. This approach not only reduces latency but also allows developers to focus on creating core business logic rather than dealing with the complexities of data normalization. With features like TCP-based application resynchronization and UDP multicast distribution, nxFeed provides robust options for data handling. Designed with scalability in mind, nxFeed can be utilized in environments ranging from single server installations to complex multi-site trading networks. It supports centralized management and live monitoring, providing detailed latency statistics to ensure optimal operation. This system is highly beneficial for firms looking to optimize market data processing and improve trading performance across their platforms.
The TSN Switch for Automotive Ethernet is designed to manage real-time data traffic within automotive networks. This high-performance switch provides low-latency communications, making it ideal for modern vehicle architectures that rely heavily on seamless integration and timing precision. Utilizing Time-Sensitive Networking (TSN) protocols, this switch offers enhanced coordination among automotive components, ensuring safety and efficiency in complex vehicular systems. With its robust configuration capabilities, the switch supports the intensive data rates and reliability demands of automotive networks. It's perfectly tailored for the increasingly data-centric environment of smart vehicles, where system reliability and network redundancy are paramount. The TSN Switch excels in providing guaranteed data delivery, essential for applications such as autonomous driving and advanced driver-assistance systems. The integration of this switch into vehicle networks aids in simplifying complex electronic environments, offering manufacturers a scalable solution that adapts to varying production needs. This flexibility ensures that manufacturers can optimize for both current requirements and future advancements in automotive technology. The TSN Switch's comprehensive feature set is aligned with the strict safety requirements of the automotive industry, ensuring compliance with global standards and enhancing vehicle intelligence.
The RISCV SoC developed by Dyumnin Semiconductors is engineered with a 64-bit quad-core server-class RISCV CPU, aiming to bridge various application needs with an integrated, holistic system design. Each subsystem of this SoC, from AI/ML capabilities to automotive and multimedia functionalities, is constructed to deliver optimal performance and streamlined operations. Designed as a reference model, this SoC enables quick adaptation and deployment, significantly reducing the time-to-market for clients. The AI Accelerator subsystem enhances AI operations with its collaboration of a custom central processing unit, intertwined with a specialized tensor flow unit. In the multimedia domain, the SoC boasts integration capabilities for HDMI, Display Port, MIPI, and other advanced graphic and audio technologies, ensuring versatile application across various multimedia requirements. Memory handling is another strength of this SoC, with support for protocols ranging from DDR and MMC to more advanced interfaces like ONFI and SD/SDIO, ensuring seamless connectivity with a wide array of memory modules. Moreover, the communication subsystem encompasses a broad spectrum of connectivity protocols, including PCIe, Ethernet, USB, and SPI, crafting an all-rounded solution for modern communication challenges. The automotive subsystem, offering CAN and CAN-FD protocols, further extends its utility into automotive connectivity.
The 2D FFT IP extends the power of the traditional FFT by enabling two-dimensional transforms, essential for image and signal processing where data is structured in matrices. With an impressive balance of speed and resource utilization, the 2D FFT handles massive data efficiently using internal or external memory interfaces to fit broad application demands. Its adaptability for FPGA and ASIC applications makes it an ideal candidate for high-performance computing tasks needing complex data manipulation.
This platform stands out for its ability to offload and accelerate network protocol processing at an impressive speed of up to 100 Gbps using FPGA technology. The Network Protocol Accelerator Platform is designed to enhance network-related tasks, providing distinct performance advantages by leveraging MLE's patented technology. This IP is highly suitable for those requiring efficient data processing in high-speed networking applications, offering scalable solutions from point-to-point connections to complex network systems. The platform's innovation lies in its ability to seamlessly manage a wide array of network protocols, making communication between devices efficient and effective. With its high-speed capability, the platform aids in reducing data processing time significantly. The robustness of this platform ensures that data integrity is maintained across various network tasks, including data acceleration and offloading critical network processes. Furthermore, this platform is particularly useful for industries like telecommunications and data centers where processing large volumes of data rapidly is crucial. The ability to upgrade and maintain such technology provides users with flexibility and adaptability in response to changing network demands. With its broad applicability, the Network Protocol Accelerator Platform remains a strategic asset for enhancing operational efficiency in digital infrastructure management.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The L5-Direct GNSS Receiver by oneNav offers cutting-edge performance by exclusively leveraging L5-band signals for navigation. This receiver directly captures signals in the L5 band, bypassing traditional L1 signals, which are often susceptible to interference and jamming. Designed for modern GNSS applications, it provides unmatched accuracy and robustness in urban areas and other challenging environments. The L5-direct technology boasts innovative features such as an Application Specific Array Processor (ASAP), which ensures rapid location acquisition without sacrificing sensitivity. It supports over 70 satellite signals across multiple constellations, including GPS, Galileo, BeiDou, and QZSS. This capability guarantees reliable positioning, making it ideal for users who require accurate and tamper-resistant navigation data. One of the unique aspects of the L5-Direct GNSS Receiver is its low power consumption, thanks to its optimized processing efficiencies. It is crafted to cater to applications with stringent size and cost restrictions, such as wearables and IoT devices. Furthermore, the receiver offers a single RF chain design, simplifying integration and reducing system complexity. This innovation makes oneNav's solution a compelling choice for next-generation GNSS receivers in diverse technological contexts.
The FCM1401 Dual-Drive™ Power Amplifier is tailored for Ku-band applications, utilizing CMOS technology to deliver solutions between 12.4 to 16 GHz. This product is designed to optimize power output while maintaining a compact silicon footprint. Notable for its excellent efficiency, the FCM1401 addresses the specific demands of telecom and satellite communications applications. The amplifier provides reliable performance characterized by a gain of 22 dB and a Psat of 19.2 dBm, achieving a power-added efficiency of 47% while operating at a supply voltage of 1.8V. Through these specifications, it positions itself as an ideal solution for applications requiring high power output and minimal heat generation. This product benefits from world-class CMOS integration, ensuring compatibility with modern telecom systems, enhancing their range and reducing their energy costs. The FCM1401 is equipped with a QFN/EVB package, allowing for straightforward implementation in various industrial contexts. It sets itself apart by offering an increased frequency range while delivering robust power handling capabilities, facilitating the high RF power needs of contemporary communication systems. The dual-drive capability of the FCM1401 means that it can effectively double the input signal power into the output without losing efficiency, making it highly suited for use in mission-critical operations where reliability and performance are paramount. Its high power-added efficiency also translates to cooler operation, reducing the need for extensive thermal management solutions, thus lowering associated costs.
The 10G TCP Offload Engine (TOE) is engineered to provide superior network performance by offloading TCP/IP processing tasks from the CPU. Implemented on advanced FPGA platforms, it ensures ultra-low latency and exceptional throughput by handling TCP tasks directly within the hardware. This engine supports high-performance applications by streamlining network data flow, drastically cutting down CPU load, and providing efficient data packet handling with minimal delay. Its architecture allows for optimal CPU usage, enabling it to support a larger number of sessions and superior bandwidth handling. The 10G TOE is especially suited for environments where efficient data processing and low latency are vital, such as financial trading platforms, real-time analytics, and other enterprise-level applications. The integration of direct hardware processing ensures consistent high-speed performance.
The InfiniBand DDR Link Layer Core from Polybus Systems offers enhanced data transfer capabilities with Double Data Rate (DDR) technology. Running at 250 MHz, it achieves 20 Gbps bidirectional communication, requiring a 5 GHz SerDes. It's suitable for high-speed data exchanges in advanced Xilinx and Altera FPGA platforms, providing middle-grade performance through efficient integration in networked systems.
ntRSE core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The RecAccel N3000 AI Inference Chip is at the forefront of AI technology, specifically crafted to handle vast amounts of data for real-time inference tasks. Aimed at enhancing machine learning deployments, this chip offers impeccable efficiency and speed, allowing enterprises to harness the full potential of AI-driven insights. With its fine-tuned ASIC design, the chip is ideal for deep learning models, particularly in recommendation systems that demand quick, accurate results. It effectively distributes workloads away from traditional CPUs, reducing computational stress and improving overall performance across digital platforms. Such optimization is critical for businesses that are scaling AI capabilities in competitive markets. Designed for flexibility, the RecAccel N3000 can seamlessly integrate into a variety of system configurations, providing a reliable base for expanding AI functions. Its energy-efficient operation supports sustainable IT strategies, ensuring that companies can pursue innovative solutions without incurring excessive energy usage costs.
MLE's Low Latency Ethernet 10G/25G MAC IP is developed to address the needs for high-performance and low-latency Ethernet connectivity. This IP core is particularly suitable for environments where data must be transmitted with minimal delay, enhancing network efficiency and communication between interconnected devices at both 10G and 25G speeds. The core is designed to ensure that data packets are transmitted effectively, maintaining the integrity and speed necessary for demanding applications. With detailed IEEE compliance, the MAC core facilitates smooth integration into various networking systems, ensuring that connectivity protocols are efficiently managed. This IP is highly regarded in sectors that prioritize swift and reliable data transfer, such as finance, telecommunications, and high-frequency trading environments. By minimizing data latency, this MAC core helps maintain high standards of data transmission, vital for real-time operations. The combination of speed and efficiency this IP offers ensures it is a preferred choice for cutting-edge networking solutions.
ntRSD_UF core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length, maximum number of parity symbols as well as I/O data width, internal datapath and decoding engines parallelism. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD_UF core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The core is designed and optimized for applications that need very high throughput data rates. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
SiFive Performance family processors are specifically engineered to deliver outstanding performance and efficiency across a wide range of applications. These processors cater to diverse market demands, including data centers, consumer electronics, and AI-driven workloads. They feature high-performance, 64-bit out-of-order cores with optional vector engines, making them ideal for heavy-duty tasks requiring maximum throughput and scalability. The series incorporates a variety of architectural features that optimize performance and energy efficiency. It includes cores scalable from three-wide to six-wide, supporting up to 256-bit vector operations, which are particularly advantageous for AI and multimedia processing applications. This optimal balance ensures that each core offers superior compute density and power efficiency. Additionally, the SiFive Performance series emphasizes flexibility, allowing users to mix and match cores to achieve the desired balance between performance and power consumption. This makes the series a perfect fit for both performance-intensive and power-sensitive applications, enabling developers to create customized solutions tailored to their specific needs.
eSi-Comms brings highly parametisable communications technology to the table, offering a flexible solution that can be tailored to specific interfacing needs. This IP supports a range of communication protocols and is designed to meet critical system requirements while minimizing integration risks and optimizing performance.
Chevin Technology's TCP/IP Offload Engine is crafted to enhance the performance of network systems within FPGA infrastructures. This IP core effectively manages TCP/IP processing, offloading tasks from the main processor to improve data handling efficiency. By optimizing network throughput and minimizing overhead, the engine is an invaluable asset for scalable network solutions. With support for both 10G and 25G Ethernet, the TCP/IP Offload Engine provides broad compatibility and functionality, ensuring smooth operations across diverse FPGA applications. The core's design reduces latency and power draw, aligning with industry needs for efficient and sustainable technology solutions. Successful integrations of the TCP/IP Offload Engine have been seen in sectors such as medical research and industrial imaging, where high-speed data transfer and processing are crucial. This IP core underscores Chevin Technology's dedication to delivering performance-driven solutions that cater to complex network environments.
Naneng Microelectronics offers a versatile Universal High-Speed SERDES capable of operating in a broad range of speeds from 1Gbps to 12.5Gbps. This SERDES is engineered to provide seamless and agile data transmission, underpinning critical communications infrastructure in various applications. The high-speed capabilities of this serializer/deserializer underline its suitability for high-performance networking solutions. Its flexible deployment options make it an ideal candidate for integration in a variety of system architectures, promoting a balance between speed and signal integrity. The design includes robust features to counter signal degradation and maintain the integrity of transmitted data, ensuring reliable operation across extensive data networks. Support for high data rates ensures this SERDES component meets and exceeds industry standards, delivering enhanced data throughput and supporting next-generation electronic systems. With adaptability at its core, the Universal High-Speed SERDES exemplifies comprehensive technological solutions in the semiconductor industry.
The 4K Video Scaler by Zipcores is tailored for providing high-quality digital scaling solutions suitable for 4K/UHD content. Harnessing state-of-the-art processing technology, this scaler ensures crisp image quality even at high resolutions, without the need for complex external memory setups. Designed for integration into mid-range FPGA and SoC platforms, the scaler supports dual pixels per clock and operates with an effective pixel clock rate of 600 MHz. This capability is crucial for systems in need of high-definition video processing without additional memory overhead. The simple AXI4-stream input/output interfaces of the 4K Video Scaler make it compatible across a range of designs, facilitating easy deployment in various multimedia projects. It is the ideal choice for applications focused on delivering superior video quality, such as broadcasting equipment and high-end consumer electronics.
Optimized for 5G NTN hybrid networks, AccelerComm's Complete 5G NR Physical Layer solution enhances link performance while maintaining industry-leading size, weight, and power (SWaP) metrics. Designed to support diverse use cases such as broadband, direct-to-device (D2D), and defense applications, the solution is adaptable across various platforms including ARM CPUs, AI Engines, FPGA, and ASIC-ready IP cores. The solution allows early end-to-end integration by running on a range of Commercial off the Shelf (COTS) boards, reducing project risk. Employing innovative algorithms, the physical layer not only achieves high throughput but also supports a vast number of users per chipset, capable of scaling to the capacity needs of next-generation satellite constellations. Moreover, AccelerComm’s unique approach emphasizes flexibility and rapid integration, utilizing standardized interfaces that ensure smooth inclusion in a variety of projects. With a focus on minimizing latency and enhancing error correction capabilities, this solution is crafted to resolve the unique challenges presented by 5G NTN environments.
Offering a seamless radio communication solution, ShortLink’s Complete RF Transceiver for 433, 868, and 915 MHz comes packed with a robust set of features crafted to enhance wireless connectivity. This transceiver complies with the IEEE 802.15.4 standard, offering reliable data transfer in Sub-GHz bands renowned for their long-range capabilities. With transmit power adjustable from -20 to +8 dBm, the transceiver excels in scenarios demanding energy efficiency and vast reach. Supporting data rates up to 250 kbps, it's ideal for various IoT applications offering dependable indoor and outdoor connectivity. Designed for easy integration, the RF transceiver incorporates built-in voltage regulators, a bandgap reference, and bias generation to simplify system-level implementation. One of its standout capabilities is its ability to adopt custom radio protocols, enabling tailored communication paths that can significantly reduce power consumption and extend battery life. With its support for multiple global frequencies, the design ensures a wide applicability range across different regions, making it the perfect choice for developers looking to harness Sub-GHz for expansive communication reach. The crystal oscillators within provide high stability for clock generation, ensuring precise system operation. This tightly integrated RF solution does away with the need for additional radio chips, allowing for a reduced bill-of-materials (BOM) and a more compact final product footprint. The transceiver is compatible with a variety of process technologies, adding another layer of flexibility for system designers to achieve the perfect balance between performance and energy efficiency.
The Centralized Network Configurator (CNC) developed by Comcores serves as a pivotal component of Time-Sensitive Networking (TSN) infrastructure. Aimed at coordinating TSN-based Ethernet networks, the CNC is designed to manage and optimize traffic flows, synchronizing network behaviors across various devices and network nodes. This synchronization is vital for applications requiring precise timing and reliable data exchange, especially in automotive, industrial, and aerospace environments. The CNC supports advanced TSN standards, ensuring network components work harmoniously by scheduling network resources with minimal delay and maximum efficiency. Through such precise configuration, it enhances the overall resiliency and adaptability of the network, meeting stringent demands for data integrity and timing accuracy.
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