All IPs > Security IP > Cryptography Cores
In today's interconnected world, the importance of secure communication and data protection cannot be overstated. Cryptography cores are a crucial subset of semiconductor IPs designed to provide foundational security solutions across a variety of electronic systems. At their core, these IPs implement complex algorithms that ensure the confidentiality, integrity, and authenticity of data being processed and exchanged.
The cryptography cores available in this category offer a diverse range of features tailored to different security needs. From symmetric-key algorithms like AES to asymmetric-key systems such as RSA and ECC, these cores ensure that systems can securely encrypt and decrypt information, protecting it from unauthorized access and tampering. By embedding these cryptographic functions directly into hardware, it becomes possible to achieve faster processing speeds and higher levels of security compared to software implementations.
These semiconductor IPs are widely used in applications where data security is paramount. This includes, but is not limited to, industries such as finance, telecommunications, and healthcare. Devices utilizing cryptography cores can range from secure payment systems, ensuring safe financial transactions, to mobile devices for secure communications, to medical devices that safeguard sensitive health information. Additionally, with the rise of the Internet of Things (IoT), cryptography cores are increasingly crucial in providing secure connections for a myriad of smart devices.
By integrating cryptography cores into your designs, you not only improve security but also future-proof your products against many potential vulnerabilities. As security threats continue to evolve, having robust cryptography solutions is essential for maintaining trust and reliability in your products and services. Whether you're developing a new application or enhancing an existing one, our category of cryptography cores offers the semiconductor IP solutions you need to meet today's stringent security demands.
The Akida IP is a state-of-the-art neural processor that harnesses the power of brain-inspired computing principles. Engineered for ultra-low power consumption, it excels in real-time AI processing at the edge. The Akida architecture is characterized by its innovative use of sparsity, allowing it to focus computational resources on the most pertinent data while minimizing energy usage. This IP supports a variety of AI workloads, efficiently running both convolutional and fully-connected neural network layers. One of Akida's standout features is its on-chip learning capability. This functionality empowers devices to adapt and learn from new data with minimal need for cloud connectivity, enhancing both privacy and latency. Additionally, the Akida IP is highly configurable, offering extensive post-silicon flexibility, which ensures its adaptability across numerous applications such as vision processing, audio analysis, and sensor fusion. The platform's scalability is another notable advantage, allowing configurations from single to multiple neural nodes. This flexibility makes it a suitable choice for a wide range of AI applications, from small-scale consumer devices to larger industrial implementations. The successful integration of Akida IP in various products highlights its potential to revolutionize AI at the edge.
Overview: Cybersecurity IPs offer a range of essential security features to protect your digital assets and sensitive information. From True Random Number Generators (TRNG) to advanced encryption algorithms like AES, DES, 3DES, and cryptographic hash functions like SHA, as well as RSA for secure key exchange and digital signatures, the IPs provide a comprehensive suite of tools to safeguard your data. Key Features: True Random Number Generator (TRNG): Generates unpredictable and unbiased random numbers for cryptographic applications. Advanced Encryption Standard (AES): Provides robust encryption with symmetric key algorithms for securing data. Data Encryption Standard (DES) and Triple DES (3DES): Implement legacy encryption algorithms for data protection. Hash Functions: Includes secure cryptographic hash functions like SHA (Secure Hash Algorithm) for data integrity verification. RSA: Enables secure key exchange, encryption, and digital signatures for secure communication. These cybersecurity IPs are designed to meet the stringent security requirements of modern applications, ensuring the confidentiality, integrity, and authenticity of your data.
The aiWare NPU (Neural Processing Unit) by aiMotive is a high-performance hardware solution tailored specifically for automotive AI applications. It is engineered to accelerate inference tasks for autonomous driving systems, ensuring excellent performance across a variety of neural network workloads. aiWare delivers significant flexibility and efficiency, capable of scaling from basic Level 2 applications to complex multi-sensor Level 3+ systems. Achieving up to 98% efficiency, aiWare's design focuses on minimizing power utilization while maximizing core performance. It supports a broad spectrum of neural network architectures, including convolutional neural networks, transformers, and recurrent networks, making it suitable for diverse AI tasks in the automotive sphere. The NPU's architecture allows for minimal external memory access, thanks to its highly efficient dataflow design that capitalizes on on-chip memory caching. With a robust toolkit known as aiWare Studio, engineers can efficiently optimize neural networks without in-depth knowledge of low-level programming, streamlining development and integration efforts. The aiWare hardware is also compatible with V2X communication and advanced driver assistance systems, adapting to various operational needs with great dexterity. Its comprehensive support for automotive safety standards further cements its reputation as a reliable choice for integrating artificial intelligence into next-generation vehicles.
The SiFive Intelligence X280 is a high-performance CPU core tailored for advanced AI and ML workloads, featuring sophisticated vector and matrix compute capabilities. It offers developers a vast toolkit for crafting efficient AI solutions that can be deployed at the edge, thanks to a focus on providing both high performance and scalability. The X280’s architecture allows for the integration of custom accelerator engines, making it highly adaptable to shifting demands in AI technology. Boasting advanced vector compute engines, the X280 is designed to handle large datasets efficiently, ideal for inference tasks and model training. This processor stands out with its high bandwidth interconnects, facilitating seamless data flow and control across custom computing engines integrated using RISC-V custom instructions. Its capabilities mark it as a versatile choice for complex machine learning applications spanning various industry segments. The SiFive Intelligence X280 supports a broad range of tools and frameworks designed to simplify deployment and integration. By using a RISC-V architecture, it promotes open innovation and reduces dependency on traditional proprietary models. This freedom translates into increased optimization opportunities, enabling rapid iteration and development cycles critical for maintaining a competitive edge in AI technology.
Polar ID from Metalenz offers a cutting-edge face unlock solution, using advanced meta-optic technology to provide secure, high-resolution facial recognition capabilities. It captures the unique "polarization signature" of a human face, making it resistant to both 2D photos and sophisticated 3D masks. Polar ID operates efficiently in a variety of lighting conditions, from bright daylight to dark environments, ensuring its utility extends across all smartphone models without sacrificing security or user experience. This technology replaces complex structured light modules, incorporating a single near-infrared polarization camera and active illumination source. It significantly reduces costs and footprint, supporting a broad adoption across hundreds of millions of mobile devices. With its low price point and high performance, Polar ID elevates smartphone security, offering robust protection for digital transactions and identity verification. By enabling this on an embedded platform with compatibility for Qualcomm's Snapdragon processors, Metalenz ensures widespread applicability. The key advantage of Polar ID is its affordability and ease of integration, as it eliminates the need for larger, more intrusive notches in phone designs. Its sophisticated polarization sensing means secure authentication is possible even if the user wears sunglasses or masks. Polar ID sets a new benchmark in smartphone security by delivering convenience and enhanced protection, marking it as the first polarization sensor available for smartphones.
PUFrt is a formidable security solution designed to create a robust hardware root of trust for various semiconductor applications. Built using patented NeoPUF technology, it generates a unique and unclonable 1024-bit identification code and root key directly within the chip. This feature ensures that the secret keys never leave the hardware, significantly minimizing the risk of extraction or duplication. The architecture of PUFrt encompasses a comprehensive security framework with components such as secure OTP storage for safeguarding sensitive data, a true random number generator complying with NIST standards, and an anti-tamper shell designed to protect against physical attacks. These elements contribute to a secure environment that can seamlessly integrate with other Crypto Engines and Security Coprocessors, ensuring wide application across IoT, automotive, and edge AI systems. With PUFrt, users can deploy a secure boot mechanism and ensure the integrity and confidentiality of digital communications. Its resilience to tampering and high integration capabilities make it a cornerstone in securing the semiconductor supply chain while enhancing device authentication and protection against reverse engineering.
AES-XTS, an innovative encryption solution from Helion Technology, is specialized for securing data stored on physical storage devices. This mode of AES encryption is particularly suited for digital data protection on hard drives and storage networks, where ensuring data integrity and confidentiality is essential. AES-XTS operates by using two keys to enhance its cryptographic strength, providing a layer of encryption that is resistant to theft and tampering. It is commonly used in full disk encryption systems, ensuring that data remains secure even if physical access to storage devices is compromised. AES-XTS is designed to accommodate the dynamic nature of modern storage technologies. This encryption solution supports a wide array of storage devices and integrates seamlessly with existing systems. It provides an excellent balance between performance and security, catering to applications ranging from personal computing to enterprise-level storage solutions. Helion ensures the ease of integration with detailed documentation and technical support, making AES-XTS a reliable choice for storage device encryption.
Up to 1M KeyEnc/sec with improved power efficiency PQPerform-Lattice is a powerful hardware-based product designed for high throughput, high-performance, and high speed. It adds post-quantum cryptography for applications that typically handle a large number of transactions, such as high-capacity network hardware applications and secure key management HSMs. Optimizable for secure boot, as well as other use-cases, PQPerform-Lattice supports FIPS 204 ML-DSA for quantum-secure digital signature verification, as well as FIPS 203 ML-KEM for quantum key exchange. PQPerform-Lattice supports AXI4, PCIe, and is deployable in multiple instances, making it a powerful solution for existing systems and infrastructure requirements.
Helion Technology's SHA Hashing solution provides a means of secure data verification across ASIC and FPGA platforms. SHA (Secure Hash Algorithm) is integral for ensuring data integrity through cryptographic hash functions that convert input data into a fixed-size string of bytes. This process is crucial for applications where data accuracy and security are paramount. The SHA hashing offered by Helion supports multiple variants, including SHA-1, SHA-256, SHA-384, and SHA-512, each designed to meet different security requirements based on cryptographic strength and processing power. This adaptability makes SHA hashing ideal for a range of applications, from digital signatures to integrity checking in secure communications. Helion's SHA hashing cores are optimized for performance, delivering fast processing speeds while maintaining efficiency in resource-constrained environments. This hashing technology is instrumental in securing data transmission in networks, database security, and verifying digital contents against tampering. With comprehensive support from Helion, integrating SHA Hashing into systems is straightforward, enhancing the robustness of data security strategies.
The eSi-Crypto suite from EnSilica offers a comprehensive range of cryptographic cores for ASIC and FPGA applications, focusing on low resource utilization and high throughput performance. A key component is the True Random Number Generator (TRNG), which meets NIST 800-22 standards, ensuring robust randomness and security for cryptographic processes. These cores support various interfaces including AMBA APB/AHB/AXI bus, making them versatile for multiple system architectures. The cryptographic algorithms within eSi-Crypto cover a broad spectrum, including CRYSTALS Kyber for secure key encapsulation, Dilithium for digital signatures, as well as established standards like ECC/ECDSA, RSA, and AES. These are vital for secure communications and data protection in modern digital environments. ChaCha20, Poly1305, and TDES/DES are also supported, offering a wide choice of encryption and authentication methods. Particularly noteworthy is eSi-Crypto's post-quantum readiness, thanks to the PQC-HT library designed to handle future challenges posed by quantum computing. This makes it an ideal solution for forward-thinking applications requiring top-tier security across wired and wireless networks.
FIPS 140-3 CAVP-compliant, compact PQC hardware acceleration for subsystems PQPlatform-CoPro combines hash-based and lattice-based post-quantum cryptography that can be added to an existing security subsystem. It can be optimized for minimum area, maintaining high-performance, and is designed to be run by an existing CPU using PQShield-supplied firmware, meaning it involves low integration effort and flexible configurations to support a wide variety of use cases, including quantum-safe secure boot. Solutions are available for hardware acceleration of SHA-3, SHAKE, ML-KEM, ML-DSA, alongside traditional cryptography. In addition, PQPlatform-CoPro can be configured with side-channel protection. PQPlatform-CoPro is covered by multiple PQShield implementation patents.
Post-quantum Software Development Kit Provides easy-to-use software implementations of both post-quantum and classical cryptographic primitives. It’s designed with prototyping and experimentation in mind, consisting of an integration of PQShield’s PQCryptoLib library with two popular high-level cryptography libraries: OpenSSL and mbedTLS. OpenSSL: a widely-adopted secure-communication library mbedTLS: primarily intended for use in embedded system and IoT deployments
The QUIC Protocol Core by Design Gateway is a high-speed, low-latency communication core designed to optimize network traffic in environments prone to congestion. It offers exceptional performance benefits over traditional protocols, leveraging the latest technology in secure and reliable data transmission.\n\nThis core is engineered to support high-speed environments, enhancing data throughput while reducing the likelihood of packet loss. It is particularly effective in networks with high congestion, where maintaining a seamless and efficient flow of data is critical. The QUIC Protocol Core's design focuses on minimizing latency, providing faster data exchange and enhancing overall network performance.\n\nIntegrating this protocol core into existing network infrastructure supports secure, encrypted data communication, vital for maintaining data integrity across various network environments. Its high-performance capabilities reduce overhead and improve application response times, making it indispensable for modern, high-speed data networks.\n\nBy incorporating the QUIC Protocol Core, businesses can optimize their network capabilities, ensuring secure, efficient, and reliable communications that are crucial for today's technology-driven communication systems.
AES-GCM (Advanced Encryption Standard - Galois/Counter Mode) is a premium solution by Helion Technology that combines encryption and authentication into a single process, making it a preferred choice for data privacy and integrity in digital communications. This IP is extensively used in scenarios where ensuring data confidentiality and authenticity concurrently is critical. AES-GCM is designed for high efficiency, providing fast and secure encryption that is ideal for low-latency applications. The mode implements a combination of counter mode encryption and Galois field multiplication, allowing for rapid encryption without sacrificing the authenticity of the data. This makes it particularly useful in high-speed networks and secure data storage applications. In environments like wireless communication and secure digital transactions, AES-GCM provides a robust framework by offering both encryption and verification functions, minimizing the risk of data breaches. It is compatible with various FPGA and ASIC platforms, allowing seamless integration and deployment. With its comprehensive set of features, AES-GCM strengthens data security infrastructures significantly.
FIPS 140-3 CAVP-compliant, compact lattice-based hardware PQC engine PQPlatform-Lattice is a compact FIPS 140-3 CAVP-compliant, PQC engine that adds post-quantum support for hardware components and embedded devices, using lattice-based cryptographic algorithms such as ML-KEM (FIPS 203) for post-quantum key exchange, and ML-DSA (FIPS 204) – post-quantum digital signature verification. It provides secure acceleration of lattice-based PQC alongside support for traditional cryptography. Its use cases include strong user authentication, protecting hardware keys, and small-footprint, configurable side-channel protection. PQPlatform-Lattice is designed for minimal area as well as maximum compatibility and can be deployed with optional firmware-backed side-channel countermeasures. It is covered by multiple PQShield implementation patents.
The RISC-V Hardware-Assisted Verification by Bluespec is a high-performance platform designed for swift and precise verification of RISC-V cores. It supports testing at both the core level (ISA) and system level, accommodating RTOS and Linux-based environments. This solution can verify standard ISA extensions, custom ISA extensions, and integrated accelerators, making it a versatile tool for various verification needs. One of the standout features of this platform is its scalability and accessibility via the AWS cloud, which ensures that resources can be tapped into as needed, enabling efficient verification anytime, anywhere. Such scalability is crucial for teams that require the flexibility to test various designs without being confined to local server limitations. With an emphasis on broad compatibility, the RISC-V Hardware-Assisted Verification platform is ideal for those involved in developing RISC-V based systems. It assists developers in ensuring their designs are accurate and reliable before deployment, reducing errors and speeding up time-to-market.
The NS Class is Nuclei's crucial offering for applications prioritizing security and fintech solutions. This RISC-V CPU IP securely manages IoT environments with its highly customizable and secure architecture. Equipped to support advanced security protocols and functional safety features, the NS Class is particularly suited for payment systems and other fintech applications, ensuring robust protection and reliable operations. Its design follows the RISC-V standards and is accompanied by customizable configuration options tailored to meet specific security requirements.
Trilinear Technologies' HDCP Encryption-Decryption Engine is a sophisticated solution designed to safeguard digital content as it traverses various transmission channels. This engine is compliant with the HDCP standards 1.4 and 2.3, offering robust protection mechanisms to ensure that digital media investments are secure from unauthorized access and piracy. The engine’s hardware acceleration capabilities represent a crucial advantage, significantly reducing the load on the system processor while maintaining real-time encryption and decryption functions. This not only enhances performance but also extends the operational life of the hardware involved, making it suitable for high-demand media applications across sectors such as broadcast, entertainment, and corporate environments. Trilinear’s HDCP Encryption-Decryption Engine ensures compatibility with a wide array of consumer and professional-grade video equipment, providing seamless protection without interference in media quality or transmission speed. Its flexible integration options allow it to be smoothly incorporated into existing infrastructures, whether in standalone media devices or complex SoC architectures. Supported by comprehensive software resources, the HDCP Encryption-Decryption Engine provides an all-encompassing solution that includes necessary software stacks for managing device authentication and link maintenance. Its ability to safeguard high-definition content effectively makes it an invaluable asset for entities focused on secure content delivery and rights management.
Specially engineered for the automotive industry, the NA Class IP by Nuclei complies with the stringent ISO26262 functional safety standards. This processor is crafted to handle complex automotive applications, offering flexibility and rigorous safety protocols necessary for mission-critical transportation technologies. Incorporating a range of functional safety features, the NA Class IP is equipped to ensure not only performance but also reliability and safety in high-stakes vehicular environments.
Suite-Q SW is a versatile cryptographic software library designed to offer flexibility in code size, performance, and memory usage, making it an essential tool for developers working on resource-limited devices. Engineered for high adaptability, this software package provides a robust framework for implementing secure cryptographic operations across diverse platforms, including 8-bit to 64-bit processors. The library is meticulously crafted to support various configuration options that balance speed with memory efficiency, ensuring it meets custom specifications while preserving system integrity. Portable C code and high-speed, hand-optimized assembly variants are available to provide the ideal blend of compatibility and performance required in modern applications. Key features of Suite-Q SW include seamless integration as plug-in modules, support for a wide range of hardware offloads, and extensive compatibility with general-purpose and embedded CPUs. Validated through rigorous testing and performance measurements, it provides a reliable basis for secure software development, ensuring rapid deployment with minimized risk. As such, Suite-Q SW remains an indispensable part of PQSecure's comprehensive cryptographic offerings, perfect for adapting to the ever-changing landscape of digital security.
The FPGA Lock Core is an innovative FPGA solution designed to secure FPGAs and hardware against unauthorized access and counterfeiting, leveraging a Microchip ATSHA204A crypto authentication IC. It reads a unique ID, generates a 256-bit challenge, and uses secure hashing to verify the hardware's authenticity, ensuring hardware integrity in sensitive applications like military and medical fields. This solution allows hardware protection against IP theft by enforcing authentication and disables FPGA functionality if unauthorized access is detected. The core utilizes minimal logic resources and one FPGA pin, communicating through a bidirectional open drain link. The clarity of this system is enhanced by providing the core in VHDL, allowing users to thoroughly understand its functionality, supported by example designs on Cyclone10 and Artix 7 boards, catering to both Intel and Xilinx FPGA platforms. Complementing this security measure is the Key Writer Core, which allows programming of custom secret keys into the ATSHA204A in situ on assembled boards, ensuring a seamless integration with the FPGA Lock system. Available for various FPGA platforms, the Efinix version, distributed with TRS Star, expands its applicability, with webinars and user guides offering in-depth implementation insights.
AES (standard modes) is a robust encryption solution provided by Helion Technology for securing data in ASIC and FPGA environments. Known for its efficiency and reliability, this encryption technology supports multiple modes, tailored to cater to varying security needs. These versatile modes optimize cryptographic operations, enabling a balance between strong security and performance. AES is particularly favored in applications demanding high-speed encryption without compromising the integrity of the data. It is widely implemented in networking, wireless communication, and storage security, offering protection against unauthorized data access. This solution is highly adaptable, making it suitable for a wide range of technologies, including those from leading FPGA manufacturers like Xilinx and Altera. Incorporating AES encryption into your systems allows for secure data handling, contributing to secure communications in various industries. The integration process is simplified through Helion's meticulous documentation and support, ensuring a seamless implementation. AES standard modes enhance data security frameworks, safeguarding sensitive information from potential threats.
The Individual IP Core Modules by ResQuant are comprehensive components engineered to support diverse post-quantum cryptographic standards, including Dilithium, Kyber, XMSS, SPHINCS+, AES, and the SHA-2 family. These modules offer organizations the flexibility to select specific cryptographic functionalities tailored to their security needs, without the necessity of entire systems or hardware changes. Each module is designed to integrate easily into existing infrastructure, ensuring minimal disruption while enhancing security measures against potential future quantum threats. This approach allows industries to gradually implement PQC standards, ensuring a seamless transition to quantum-resistant cryptographic measures. Tailored for flexibility, the ResQuant Individual IP Core Modules can be used across a wide array of applications, from IoT devices to complex military and IT systems. By offering component-level integration, these modules empower companies to future-proof their offerings incrementally while maintaining robust security practices in their operations.
FIPS 140-3 CAVP compliant ultra-fast, compact, and power efficient secure hash acceleration PQPlatform-Hash is a power side-channel accelerator, supporting a wide range of Hash-Based Signature Schemes (HBSS). PQPlatform-Hash deploys tried-and-tested HBSS including quantum-safe LMS and XMSS (not hybrid). It provides acceleration of HBSS in embedded devices, especially where high throughput is required, or resource constraints necessitate minimal additional area. For example, PQPlatform-Hash is a solution for secure first-stage boot loading with hash-based signature schemes. HBSS offer different trade-offs of memory/area to lattice-based schemes, and as a result, PQPlatform-Hash is ideally suited for smaller key sizes, larger signature sizes, and processing times for key generation, signature generation and verification.
Suite-Q HW is a robust system-on-chip (SoC) solution that envelops all the necessary cryptography required for secure protocols within compact and efficient hardware. Targeted at both high-end servers and low-end embedded systems, this solution emphasizes the dual benefits of scalability and adaptability. Suite-Q HW efficiently offloads demanding symmetric and asymmetric cryptographic processes by leveraging specialized accelerators, offering enhanced execution speeds that cater to different application requirements. A key component of its utility lies in its support for a wide array of cryptographic operations. This includes classical public key methods, such as ECDSA and ECDH, alongside emerging post-quantum techniques within isogeny and lattice frameworks. The hardware is further augmented by secure hash algorithms and diverse AES encryption modes, delivering comprehensive protection across a variable security landscape. Incorporating optional Differential Power Analysis (DPA) countermeasures and validated security standards, Suite-Q HW ensures security for sensitive data against contemporary and emerging threats. It facilitates integration with existing development flows across SoCs and FPGAs, optimizing power and silicon footprint according to specific needs. Furthermore, the hardware package provides comprehensive resources for integration, from testbench data to simulation scripts, enhancing its adaptability and effectiveness in today's digital security paradigm.
The Cyclone V FPGA with Integrated PQC Processor by ResQuant is a specialized product that comes pre-equipped with a comprehensive NIST PQC cryptography suite. This FPGA is tailored for applications requiring a robust proof-of-concept for quantum-safe implementations. It ensures seamless integration into existing systems, providing a practical platform for testing and deployment in quantum-secure environments. This product is available at a competitive price and represents an ideal starting point for entities looking to explore and adopt quantum-resilient technologies. Its configuration allows for straightforward implementation in diverse hardware infrastructures while offering a reliable option for organizations aiming to stay ahead in the evolving cyber security landscape. By incorporating the latest in cryptographic standards and ensuring vendor independence, the Cyclone V FPGA with Integrated PQC Processor by ResQuant effectively bridges current hardware technologies and future-proof security needs. It supports industry-wide applications, from IoT and ICT to automotive and military sectors, underscoring ResQuant's versatility in hardware security solutions.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
Featuring G15, this IP is optimized for 2KB correction blocks, suitable for NAND devices with larger page sizes, such as 8KB. The design is aligned with methods seen in the G14X, but it extends its reach with longer codewords for comprehensive coverage of high-density NAND. The design supports a wide array of block sizes and configurational setups, making it highly adaptable to varying design needs. Additional error correction capabilities can be integrated based on client requirements, reinforcing its bespoke delivery.
SphinX offers high-performance and low-latency AES-XTS encryption and decryption, crucial for securing data in transit and storage in modern digital infrastructures. It is designed with independent, non-blocking encryption and decryption channels to ensure seamless data processing without bottleneck issues. The technology provides robust security features while maintaining minimal impact on system performance, making it ideal for environments that require both high-speed data handling and stringent security protocols. Its design prioritizes data protection, ensuring encryption processes do not become a performance impediment. Deploying SphinX enhances cybersecurity capabilities significantly, offering both flexibility and scalability within existing systems. It supports modern sustainability efforts by providing strong security measures without requiring additional energy-consuming hardware, aligning with ZeroPoint's commitment to efficient, eco-friendly technology.
The NI Class RISC-V CPU IP caters to communication, video processing, and AI applications, providing a balanced architecture for intensive data handling and processing capabilities. With a focus on high efficiency and flexibility, this processor supports advanced data crunching and networking applications, ensuring that systems run smoothly and efficiently even when managing complex algorithms. The NI Class upholds Nuclei's commitment to providing versatile solutions in the evolving tech landscape.
The patented QDID PUF by Crypto Quantique utilizes quantum tunneling current variations to produce a unique identity in standard CMOS processes. This solution leverages oxide thickness variations and trap distributions in the gate oxide to create an unpredictable and unclonable physically unclonable function (PUF). As a hardware root-of-trust, it simplifies secure provisioning and emits high-entropy seeds resistant to side-channel attacks, supporting up to 256-bit security strength. The QDID PUF's robustness is confirmed through extensive testing, including adherence to NIST standards, making it an ideal choice for secure device identity and post-quantum cryptographic applications.
The G13/G13X series is tailored for 512B correction blocks, particularly used in NAND setups with 2KB to 4KB page sizes. While both variants are crafted to manage the demands of SLC NAND transitions to finer geometries, the G13X allows for correction of a higher number of errors. Designed to fit seamlessly into existing controller architectures, it enables extensions of current hardware and software capabilities without extensive new investments. It offers area optimization through parameter adjustments and supports a range of channel configurations for broad applicability.
Designed for seamless integration of the V-by-One HS interface with FPGA development platforms, the Alcora V-by-One HS Daughter Card supports high-speed video data transmission. This card can interface with FPGA boards using 8 RX and 8 TX lanes, allowing for extensive bandwidth utilization. The Alcora card is distinguished by its two available versions, differing by their header pin count: 51-pin and 41-pin. Optimized for high-definition video transmission, it supports resolutions of 4K at 120Hz or 8K at 30Hz by combining two daughter cards for enhanced lane capacity. To maintain signal integrity, Alcora incorporates two clock generators to manage transceiver reference clock synthesis and reduce recovered RX clock jitter. As a high-speed digital video interface solution, it is tailored particularly for display applications that demand rigorous performance and reliability standards.
NeoPUF is revolutionizing hardware security by providing up to 100 times faster random number generation. This advanced security technology plays a critical role in safeguarding semiconductor devices against emerging threats. It incorporates a hardware-based random number generator which powers the development of the next generation of secure chips, ensuring robust protection from unauthorized access. Positioned as a critical component in the development of secure semiconductors, NeoPUF integrates seamlessly into existing systems, offering a quantum-resilient solution. This capability is vital in defense against potential quantum-era threats, providing security that remains effective even as technology landscapes shift. NeoPUF supports operations across diverse applications, particularly in sensitive environments where data integrity is paramount. As part of PUFsecurity's comprehensive lineup, NeoPUF not only enhances secure storage options but also facilitates reliable identification and anti-cloning features. It is a key enabler of trusted computing across numerous industries, underlining its importance in the modern era where security is indispensable.
The AES Core by Algotronix is a sophisticated solution tailored for securing data using advanced encryption methods. This core supports various encryption modes such as ECB, CBC, CTR, CFB, OFB, CCM, GCM, and XTS, which cater to a wide array of applications requiring different levels and methods of data protection. The flexibility in supported modes allows for tailored implementations in different security-critical environments. This encryption core is known for its deployment among prominent defense electronics organizations, and it has been operational within several NATO member states, testifying to its high-level security assurance and operational readiness in sensitive global contexts. Offered typically in source code form, the AES Core ensures that users can perform thorough security audits and tailor enhancements specific to their security policies and infrastructural needs. This capability positions Algotronix's offering as an optimal choice for organizations prioritizing stringent security postures.
The AIoT Platform from SEMIFIVE merges artificial intelligence with Internet of Things applications, providing a robust infrastructure for the next generation of smart devices. This platform capitalizes on the synergy between AI and IoT, designed to deliver high efficiency and seamless integration for diverse IoT ecosystems. Utilizing the latest process technologies and silicon-proven IPs, the AIoT Platform enables rapid development cycles. It supports a wide range of AIoT applications, enhancing functionalities such as edge computing, smart home technologies, and advanced IoT networks. Developers opting for SEMIFIVE's AIoT Platform benefit from a scalable and flexible architecture, allowing for customizable implementations tailored to specific application needs. The platform ensures that all components work harmoniously to optimize performance while maintaining energy efficiency, catering to the growing demands of interconnected smart devices.
Fully autonomous, FIPS 140-3 CAVP compliant PQC subsystem PQPlatform-SubSys is a cryptographic subsystem, designed to provide offloaded cryptographic services with minimal integration effort and full autonomy from an existing security subsystem, as well as configurable side-channel protection. These services include post-quantum signature generation, verification, and secure key establishment. It’s built with optimal performance in mind, as well as crypto agility with its provision of traditional, PQ/T hybrid and fully post-quantum algorithms. PQPlatform-SubSys uses its built-in RISC-V CPU independently from the surrounding system, allowing cryptographic services to be offloaded efficiently from the system processor.
AndeSoft SW Stack encompasses a comprehensive set of software building blocks and middleware optimized for AndesCore processors. This rich collection includes operating systems, libraries, drivers, and middleware components, all meticulously designed to enhance software development speed and quality. By providing ready-to-use components, AndeSoft enables developers to focus on crafting their application-specific solutions, significantly reducing time-to-market. Its seamless integration with AndeSight IDE further enhances development efficiency, supporting diverse operating systems and being adaptable to various processor configurations for optimal performance.
VeriSyno Microelectronics offers Digital Systems and Security Solutions designed to enhance the robustness and efficiency of modern digital applications. This comprehensive suite includes IPs for PSRAM interfaces, network protocols like vMAC, and security mechanisms, addressing the critical needs for secure and efficient digital communications. The digital solutions are engineered to meet stringent security protocols, ensuring data integrity and protection in various applications. VeriSyno's expertise in digital system design enables the development of reliable solutions that integrate seamlessly into existing infrastructures, enhancing both system performance and security. These solutions are suitable for a broad spectrum of digital applications, including consumer electronics, automotive, and industrial systems, where efficient data handling and security are paramount. With ongoing innovation, VeriSyno maintains its competitive edge by adapting to emerging industry requirements and introducing forward-thinking digital solutions.
The AES Encrypt/Decrypt IP provided by Secantec offers a highly secure solution for data encryption and decryption, supporting 128, 192, and 256-bit key lengths. Adhering to the Advanced Encryption Standard (AES), this IP ensures that data confidentiality is maintained across various platforms and applications. With its comprehensive encryption capability, this IP is pivotal in protecting sensitive data against unauthorized access, making it indispensable in secure communication systems, data storage solutions, and more. It provides a robust security framework that can be implemented efficiently within existing infrastructures. By leveraging the versatility of AES algorithms, the IP can be seamlessly integrated into a wide range of environments, from high-performance computing systems to portable devices requiring secure data channels. Its design ensures minimal latency and resource overhead, delivering a swift and reliable encryption mechanism.
The DSHA2-512 core specializes in the SHA2-512 hashing algorithm, providing a highly efficient means to process hashing functions in data-intensive environments. It is designed to comply with FIPS PUB 180-4 standards, ensuring that it meets established guidelines for secure hashing operations necessary in a variety of industry settings. With interfaces that include APB, AHB, and AXI, the DSHA2-512 exhibits broad compatibility with existing digital infrastructures, enabling it to be deployed across a wide array of technology solutions. This core is ideal for sectors where ensuring data integrity and authenticity is critical, such as finance, governmental, and secure communications sectors. Its enhanced technical capabilities mean that the DSHA2-512 core supports extensive data processing requirements while maintaining the security integrity of hashes, making it an essential component for applications that demand reliable hash computation and data security.
The SHA-3 Crypto Engine is a hardware accelerator designed for cryptographic hashing, offering high throughput and area efficiency. It adheres to the NIST FIPS 202 standard, supporting all variants of the SHA-3 family, including SHA-3-224, SHA-3-256, SHA-3-384, and SHA-3-512, along with extendable output functions SHAKE-128 and SHAKE-256. Designed to resist time-based side-channel attacks, this IP core is integrated as a fully synchronous design supporting AMBA AXI4-Stream interfaces, making it versatile for various secure applications. Applications for the SHA-3 Crypto Engine span from secure message authentication to encryption protocols within IPsec and TLS/SSL engines, secure boot processes, and decentralized blockchain technologies. It is particularly suitable for e-commerce platforms and financial transaction processing, where data integrity and authenticity are paramount. Its ease of integration and robust performance ensure it is a preferred choice for next-generation security solutions. Offering resource-optimized performance, the SHA-3 engine is available with a range of deliverables, including Verilog RTL, testbenches, and comprehensive documentation. Its resource utilization across different FPGA and ASIC platforms demonstrates compatibility and efficiency, ensuring developers can implement secure hashing functions seamlessly within their devices.
The Customizable Cryptography Accelerator offered by ResQuant is designed to meet varied client needs with an extensive array of configurable options. It integrates seamlessly with all NIST PQC standards like Dilithium, Kyber, XMSS, and SPHINCS+, and is extendible with additional algorithms, including customer-specific implementations. The accelerator is built to be DPA, timing, and SCA resistant, and is AXI 4 ready, ensuring robust protection in a variety of applications. This innovation allows for customizable tuning in performance and size, addressing the specific security requirements of customers from various industries. The accelerator demonstrates ResQuant's commitment to flexibility and adaptability, enabling clients to implement cutting-edge encryption with ease. With ongoing enhancements to extend its capabilities, the accelerator stands as a critical component in defenses against future computational threats posed by quantum technologies. In addition to its technical capabilities, the ResQuant Customizable Cryptography Accelerator is engineered for efficient power use and minimized physical footprint, making it suitable for integration into a wide range of hardware setups. This solution underscores ResQuant's dedication to delivering high-security standards and unmatched versatility in cryptographic processing solutions.
The CANsec Controller Core is engineered to provide enhanced security features for automotive CAN networks. Traditional CAN networks are not inherently secure, posing challenges in protecting against unauthorized access and data tampering. This controller core integrates security protocols directly into the CAN framework, offering an encryption-enabled solution tailored for modern automotive needs. This controller core implements standardized security measures, ensuring confidentiality, integrity, and authenticity of CAN messages. By incorporating advanced cryptographic algorithms, the CANsec Controller Core meets stringent security requirements without compromising the performance that automotive applications demand. Its design focuses on minimizing resource consumption while providing robust security enhancements. Ideal for vehicles requiring secure communication between various electronic control units (ECUs), the core upholds the automotive industry’s increasing emphasis on cybersecurity. The CANsec Controller Core is versatile in its implementation, suitable for both new vehicle architectures and as an upgrade to existing systems, making it a vital component of future-proof automotive design.
The IPSEC Core by Algotronix is designed to secure IP communications by providing robust encryption and authentication mechanisms. Essential for ensuring data confidentiality and integrity over IP networks, this core is suitable for embedding into network devices and systems aimed at safeguarding data against potential interception or tampering. Catering to a broad range of IP-based communication systems, the IPSEC Core offers flexibility and reliability, making it a preferred choice for developers focusing on secure data exchange methods. The ease of integration allows for its deployment in both new and existing network architectures, underpinning secure transmissions across increasingly complex digital environments. Its wide acceptance and deployment in secure communications underscore the IPSEC Core's effectiveness in delivering critical security features, thus supporting enterprises in protecting sensitive data across diverse network topologies.
Post-Quantum Cryptography IPs are designed to safeguard systems against future quantum-computing threats, providing robust cryptographic measures that withstand the computational power expected from quantum computers. These IPs offer algorithms that secure data and communications much beyond the capabilities of traditional public-key cryptography. Their implementation is crucial for forward-looking industries that require enhanced security measures to protect sensitive information, ensuring a seamless transition into a quantum-secure future. Secure-IC actively contributes to the development and implementation of these algorithms, ensuring their clients are equipped for forthcoming cybersecurity challenges.
The 802.11 LDPC core by Wasiela is designed to provide high data rate wireless communication with increased error correction capabilities. Leveraging low-density parity-check (LDPC) codes, this product significantly enhances the reliability of wireless networks by correcting errors that occur during data transmission. It is particularly tailored for environments where maintaining high throughput is critical, such as in dense urban areas or during streaming high-definition content across networks. Wasiela’s design implements an efficient iterative decoding process, adjusting the number of iterations dynamically to ensure optimal performance. The 802.11 LDPC is compatible with various wireless communication standards, making it a versatile choice for manufacturers aiming to integrate robust error correction features in their devices. This core is also optimized for low power consumption, ensuring it meets the power efficiency standards required by modern wireless devices. By ensuring frame-to-frame configuration capabilities, the 802.11 LDPC core not only operates efficiently under varying conditions but also provides seamless adaptability across different data rates. This adaptability makes it well-suited for evolving network demands, meeting the needs of next-generation applications with ease.
The MACSEC Core provides an essential building block for implementing Ethernet data security, supporting protocols crucial for protecting data at the MAC layer in network infrastructure. It ensures confidentiality and integrity of the communications, making it invaluable for environments where data transmission security is paramount. A vital tool for network security, the MACSEC Core integrates seamlessly into various network processors, offering robust security for both small-scale and extensive network architectures. It stands out for its efficiency in encrypting and authenticating Ethernet packets, ensuring data remains protected from eavesdropping and unauthorized access. Designed for versatile network applications, the MACSEC Core can easily adapt to existing network configurations, enabling quick deployment and teeming with existing systems, thereby enhancing overall network security without extensive reconfigurations.
PUFcc serves as an advanced crypto coprocessor that provides a complete security foundation by integrating a hardware root of trust with a comprehensive suite of cryptographic engines. This solution excels in delivering secure key generation, storage, and full-scale encryption capabilities across diverse applications in the IoT, AI, and automotive sectors. Featuring NIST CAVP-certified and OSCCA standards-compliant engines, PUFcc is adaptable to various security requirements and performs rapid cryptographic operations with exceptional security. The architecture incorporates APB and AXI interfaces to enable swift access to system memory, optimizing the security infrastructure with its modular design. The latest iteration, PUFcc7, further enhances the design with upgrades to public key cryptography and hashing algorithms, aligning with TLS 1.3 standards to ensure robust security for evolving digital communication needs. The PUFcc series stands as a superior crypto engine heavily relied upon for securing high-value data and devices in complex digital ecosystems.
ReRAM as FTP/OTP Memory by CrossBar provides flexible, non-volatile memory solutions suitable for few-time and one-time programmable memory applications. Its integration into CMOS processes makes it a versatile choice for secure computing environments where PUF keys are necessary. The technology's shared architecture allows FTP, OTP, and MTP configurations within a common monolithic design, optimizing chip space and costs.
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