All IPs > Analog & Mixed Signal
Analog & Mixed Signal semiconductor IPs are essential components in modern electronics, serving as the backbone for a wide range of applications that require the processing, conversion, and management of both analog and digital signals. This category encompasses a diverse array of integrated circuit designs and modules that facilitate the seamless handling of signal variations, ensuring the performance and efficiency of electronic devices.
The category includes Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters, crucial for the conversion of signals between their analog and digital forms, enabling precise data processing and communication in devices such as smartphones, audio equipment, and sensor interfaces. Amplifiers, Analog Comparators, and Analog Filters further enhance signal fidelity by boosting signal strength, comparing voltages, and removing unwanted noise or frequency components, respectively.
Analog & Mixed Signal IPs also feature specialized components like Phase-Locked Loops (PLLs) and Delay-Locked Loops (DLLs) that are pivotal in frequency synthesis and timing signal alignment in high-speed data communication systems. Power Management IPs, including DC-DC Converters, ensure optimal energy efficiency by effectively regulating voltage levels and power distribution across electronic systems.
Additional solutions such as Clock Synthesizers, RF Modules, and Photonics components address the growing needs for high-frequency signal generation, wireless communication enhancement, and optical signal processing. The category also contains Analog Front Ends and Multiplexers, which are integral in conditioning and selecting signals in complex systems, highlighting the expansive utility of Analog & Mixed Signal semiconductor IPs in contemporary electronic design and innovation.
The agileADC analog-to-digital converter is a traditional Charge-Redistribution SAR ADC that is referenced to VDD, VSS. The architecture can achieve up to 12-bit resolution at sample rates up to 64 MSPS. It includes a 16-channel input multiplexor that can be configured to be buffered or unbuffered, and support differential or single-ended inputs. Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our automated design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. Our highly configurable and multi-node analog IP products are developed to meet the customer’s exact requirements. These digitally-wrapped and verified solutions can be seamlessly integrated into any SoC, significantly reducing complexity, time and costs.
The agilePMU Subsystem is an efficient and highly integrated power management unit for SoCs/ASICs. Featuring a power-on-reset, multiple low drop-out regulators, and an associated reference generator. The agilePMU Subsystem is designed to ensure low power consumption while providing optimal power management capabilities. Equipped with an integrated digital controller, the agilePMU Subsystem offers precise control over start-up and shutdown, supports supply sequencing, and allows for individual programmable output voltage for each LDO. Status monitors provide real-time feedback on the current state of the subsystem, ensuring optimal system performance. Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our automated design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. Our highly configurable and multi-node analog IP products are developed to meet the customer’s exact requirements. These digitally-wrapped and verified solutions can be seamlessly integrated into any SoC, significantly reducing complexity, time and costs.
CoreVCO is a sophisticated voltage-controlled oscillator specifically designed to endure harsh environments and applications like space and military operations. This VCO comprises two distinct, radiation-hardened wideband SiGe designs, optimized for ultra-low phase noise over an extensive frequency range. This design enhances reliability and functionality in environments with high radiation levels, making CoreVCO a leading choice for high-performance applications.\nThe VCO operates efficiently in frequencies ranging from 0.7 GHz to 6.6 GHz, offering different configurations for optimal phase noise across varied uses. The integration of bandgap references and LDOs supports operational flexibility, with a single power supply voltage of 5.0V facilitating uniform performance across applications.\nEnd users will benefit from its digital calibration capabilities, which provide stability against temperature and process variations, and its small form factor, packaged in a 6mm x 6mm footprint. CoreVCO suits a spectrum of applications from satellite communications to advanced military systems, demonstrating CoreHW's commitment to high-quality, durable design.
Silicon Creations' Free Running Oscillators provide dependable timing solutions for a range of applications such as watchdog timers and core clock generators in low-power systems. These oscillators, crafted with compactness and efficiency in mind, support a gamut of processes from 65nm to the latest 3nm technologies. These oscillators excel in low power consumption, often requiring less than 30µW during operation. Their robust design ensures they deliver high precision over a temperature range from -40°C to 125°C with supply voltage variabilities factored in. The simplicity in design negates the need for external components, promoting easier integration and reduced overall system complexity. Precise tuning capabilities allow for accuracy levels up to ±1.5% after process trimming, ensuring outstanding performance in volatile environmental conditions. This level of reliability makes them ideal for integration into various consumer electronics, automotive controls, and other precision-demanding applications where space and power constraints are critical.
Silicon Creations' Analog Glue solutions provide essential analog functionalities to complete custom SoC designs seamlessly. These functional blocks, which constitute buffer and bandgap reference circuits, are vital for seamless on-chip clock distribution and ensure low-jitter operations. Analog Glue includes crucial components such as power-on reset (POR) generators and bridging circuits to support various protocols and interfaces within SoCs. These supplementary macros are crafted to complement existing PLLs and facilities like SerDes, securing reliable signal transmission under varied operating circumstances. Serving as the unsung heroes of chip integration, these Analog Glue functions mitigate the inevitable risks of complex SoC designs, supporting efficient design flows and effective population of chip real estate. Thus, by emphasizing critical system coherency, they enhance overall component functionality, providing a stable infrastructure upon which additional system insights can be leveraged.
The agileDAC is a digital-to-analog converter that uses a traditional capacitive DAC architecture. The agileDAC uses its own internal reference voltage. The architecture can achieve up to 10-bit resolution at sample rates up to 16 MSPS. Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our automated design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. Our highly configurable and multi-node analog IP products are developed to meet the customer’s exact requirements. These digitally-wrapped and verified solutions can be seamlessly integrated into any SoC, significantly reducing complexity, time and costs.
The KL730 AI SoC is equipped with a state-of-the-art third-generation reconfigurable NPU architecture, delivering up to 8 TOPS of computational power. This innovative architecture enhances computational efficiency, particularly with the latest CNN networks and transformer applications, while reducing DDR bandwidth demands. The KL730 excels in video processing, offering support for 4K 60FPS output and boasts capabilities like noise reduction, wide dynamic range, and low-light imaging. It is ideal for applications such as intelligent security, autonomous driving, and video conferencing.
Silicon Creations crafts highly reliable LVDS interfaces designed to meet diverse application needs, going from bi-directional I/Os to specialized uni-directional configurations. Spanning process compatibilities from 90nm CMOS to advanced 7nm FinFET, these interfaces are a cornerstone for high-speed data communication systems, thriving particularly in video data transmission and chip-to-chip communications. Supporting robust data rates over multiple channels, the LVDS Interfaces guarantee flexible programmability and protocol compatibility with standards such as FPD-Link and Camera-Link. They capitalize on proven PLL and CDR architectures for superior signal integrity and error-free data transfers. Operating efficiently in various technology nodes, they remain highly effective across collaborative chipset environments. The interfaces are fortified with adaptable features like dynamic phase alignment to stabilize data sequences and on-die termination options for superior signal integrity. Their proven record places them as a critical enabler in applications where consistent high-speed data transfer is paramount, demonstrating Silicon Creations’ prowess in delivering industry-leading communication solutions.
Silicon Creations delivers precision LC-PLLs designed for ultra-low jitter applications requiring high-end performance. These LC-tank PLLs are equipped with advanced digital architectures supporting wide frequency tuning capabilities, primarily suited for converter and PHY applications. They ensure exceptional jitter performance, maintaining values well below 300fs RMS. The LC-PLLs from Silicon Creations are characterized by their capacity to handle fractional-N operations, with active noise cancellation features allowing for clean signal synthesis free of unwanted spurs. This architecture leads to significant power efficiencies, with some IPs consuming less than 10mW. Their low footprint and high frequency integrative capabilities enable seamless deployments across various chip designs, creating a perfect balance between performance and size. Particular strength lies in these PLLs' ability to meet stringent PCIe6 reference clocking requirements. With programmable loop bandwidth and an impressive tuning range, they offer designers a powerful toolset for achieving precise signal control within cramped system on chip environments. These products highlight Silicon Creations’ commitment to providing industry-leading performance and reliability in semiconductor design.
The VCO24G, offering a robust 24GHz tuning from Pacific MicroCHIP, is designed for precision frequency control in advanced RF systems. Its Colpitts oscillator architecture ensures low noise and high stability, critical for demanding broadband communication networks.
WAVE6 represents the pinnacle of multi-standard video coding. It supports AV1 encoding, known for its efficient use of bandwidth and high compression quality. Featuring a simple architecture, it boasts a single-clock domain that synchronizes the entropy and video codec engines on the fly. The efficiency of WAVE6 is further enhanced by its power-efficient design, which minimizes consumer energy requirements through effective clock gating. It serves various sectors, including data centers and surveillance systems, operating with a remarkable performance of up to 8K60fps @ 1GHz. The integration of advanced coding techniques ensures a reduced need for external memory, thanks to the proprietary CFrame lossless compression.
The pPLL03F-GF22FDX is an advanced all-digital PLL optimized for low-jitter clocking requirements as seen in performance computing domains. Capable of handling frequencies up to 4GHz, it serves as a reliable clock source for sophisticated computing architectures needing precise timing for ADCs and DACs. Its design emphasizes small size and power efficiency, positioning it as a practical solution for dense and power-conscious SoC designs. This PLL leverages Perceptia's refined second-generation digital technology to deliver uniform performance that remains unaffected by variations in temperature, voltage, or process (PVT) conditions. With capabilities for both integer-N and fractional-N operations, it provides the flexibility needed to meet diverse application requirements and synchronization needs. Its ultra-compact footprint and low power requirements support efficient integration in systems where space and power are constrained. Integrated power regulation allows the pPLL03F to operate with either shared or dedicated power supplies, aligning with the necessities of systems with multiple clock domains. The package includes a comprehensive set of views and design models facilitating seamless incorporation into existing SoC environments, ensuring minimal design disruption and maximizing operational efficiency.
Chevin Technology's Ultra-Low Latency 10G Ethernet MAC is engineered to meet the demanding performance needs of modern telecommunications environments. This IP core optimizes data processing speed with its cutting-edge design, ensuring minimal latency and consistent data throughput. The Ultra-Low Latency 10G Ethernet MAC is particularly suited for real-time data exchange applications where swift data transmission is essential. It leverages a compact logic structure to achieve outstanding efficiency, minimizing resource requirements while bolstering performance capabilities. The core's versatile design supports straightforward integration into both new and existing systems across various FPGA platforms. It stands out for its energy-efficient operation, offering sizeable power savings over CPU-based implementations, and provides a robust licensing model to offer cost flexibility for developers.
The ORC3990 SoC is a state-of-the-art solution designed for satellite IoT applications within Totum's DMSS™ network. This low-power sensor-to-satellite system integrates an RF transceiver, ARM CPUs, memories, and PA to offer seamless IoT connectivity via LEO satellite networks. It boasts an optimized link budget for effective indoor signal coverage, eliminating the need for additional GNSS components. This compact SoC supports industrial temperature ranges and is engineered for a 10+ year battery life using advanced power management.
Archband Labs offers a PDM-to-PCM Converter that excels in translating Pulse Density Modulated (PDM) audio signals into Pulse Code Modulated (PCM) format. This conversion is crucial in audio signal processing where digital formats require conversions for accurate playback or further audio processing. Ideal for modern multimedia systems and portable audio devices, the PDM-to-PCM Converter provides high fidelity in signal conversion, ensuring sound quality is preserved during the process. This IP is highly efficient, making it perfect for applications where power conservation is important, such as battery-powered gadgets and smart wearables. Its compact design provides easy integration into existing systems, facilitating upgrades without significant redesigns. With reliable performance, this converter supports the growing demand for adaptable and high-efficiency audio processing solutions, aiding engineers in achieving cutting-edge audio clarity.
The agileCMP programmable threshold comparator features a user-selectable (enable/disable) hysteresis as well as programmable threshold with 10mV step size, a latched output as well as an active (unlatched) output. With a focus on long battery life, the agileCMP can be used to monitor external analog signals and enable wake-up events as is essential in many modern SoCs. The agileCMP programmable threshold comparator is ideally suited for interrupt generation in application areas such as HPC, IoT, security, automotive and AI. Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our automated design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. Our highly configurable and multi-node analog IP products are developed to meet the customer’s exact requirements. These digitally-wrapped and verified solutions can be seamlessly integrated into any SoC, significantly reducing complexity, time and costs.
The Ring PLLs offered by Silicon Creations illustrate a versatile clocking solution, well-suited for numerous frequency generation tasks within integrated circuit designs. Known for their general-purpose and specialized applications, these PLLs are crafted to serve a massive array of industries. Their high configurability makes them applicable for diverse synthesis needs, acting as the backbone for multiple clocking strategies across different environments. Silicon Creations' Ring PLLs epitomize high integration with functions tailored for low jitter and precision clock generation, suitable for battery-operated devices and systems demanding high accuracy. Applications span from general clocking to precise Audio Codecs and SerDes configurations requiring dedicated performance metrics. The Ring PLL architecture achieves best-in-class long-term and period jitter performance with both integer and fractional modes available. Designed to support high volumes of frequencies with minimal footprint, these PLLs aid in efficient space allocation within system designs. Their use of silicon-proven architectures and modern validation methodologies assure customers of high reliability and quick integration into existing SoC designs, emphasizing low risk and high reward configurations.
This ADC features a 12-bit resolution and a sampling rate up to 1 MSPS, making it suitable for precise analog-to-digital conversions in various applications. It is designed to deliver high-performance data acquisition while maintaining power efficiency. This single-channel converter supports enhanced signal processing capabilities, catering to applications that demand reliable and accurate digital representation of analog signals. The ADC integrates seamlessly into custom IC designs and can be utilized in sectors such as industrial automation and medical devices.
The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI). The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
The RT990 TIA is uniquely tailored for optical Cable Television (CATV) applications, where high performance in signal amplification is required. Integrated with a wide dynamic range, the RT990 handles input signals proficiently, converting them efficiently with minimal noise. This feature makes it ideal for maintaining signal clarity over long distances, essential in the delivery of high-quality television content. With its high linear gain and advanced automatic gain control, the RT990 ensures broadcast reliability even in fluctuating signal environments.
The MXL4254A is a silicon proven Quad Gigabit SerDes implemented in digital CMOS technology. Each of the four channels supports data rate up to 4.25 Gbps. It is compatible with router-backplane links, PCI Express, SATA, RapidIO, 10 Gbps Ethernet (XAUI), FibreChannel, SFI-5, SPI-5, and other communication applications.
Aeonic Power provides scalable on-die voltage regulation for power delivery in SOCs and chiplets. It features an architecture designed for energy optimization, offering functionalities like static IR drop mitigation and virtual power islands. This IP family is pivotal for meeting stringent power distribution requirements, particularly beneficial in the dynamic environments of digital cores and interface solutions, enabling simplification of power delivery structures.
The Bandgap offering from SkyeChip is a precise voltage reference circuit aimed at maintaining stability across variations in temperature and power supply. This analog IP delivers a consistent output voltage of about 0.9V with minimal deviation, making it crucial for applications requiring stability across a wide temperature range from -40C to 125C. Its low power consumption and robust design suit a variety of circuits where voltage stability is critical. The Bandgap circuit ensures effective performance in diverse conditions, contributing to the reliability and accuracy of the systems it supports.
The Cap-less LDO Regulator by Archband Labs eliminates the need for bulky external capacitors, offering a streamlined solution for voltage regulation in electronic devices. The removal of capacitors results in a simplified design and reduced component costs, making this LDO regulator an attractive choice for compact applications. Despite its minimalist design, it maintains excellent performance in regulating voltage, ensuring stable power supply across different components. This functionality is vital for precision electronics used in portable devices, IoT systems, and embedded applications, where space and power efficiency are key considerations. By providing reliable voltage regulation without the added footprint of capacitors, this LDO regulator helps engineers tackle challenges related to size constraints and power management. As a result, it supports the development of smaller, more efficient electronic devices that align with modern consumer electronic trends.
This innovative chiplet offers a complete transmission solution, integrating a 16-channel 112G modulator and driver. The chip is designed for optimal performance in transmitting optical signals and features advanced digital control for precision tuning and stability. It is built to support systems requiring high bandwidth and efficient modulation, making it ideal for deployment in next-generation telecommunication networks. The combination of integrated modulator and driver ensures reduced power consumption and higher signal integrity, addressing the needs of modern data center applications.
The AFX010x Product Family is a sophisticated lineup of analog front-end ICs designed for benchtop and portable data-acquisition systems. Each product within this family boasts up to four channels, delivering resolutions up to 16-bit and sampling rates up to 5 GS/s. A key feature is the digitally-selectable 3dB bandwidth, ranging up to 300MHz, complemented by an integrated single-to-differential amplifier and offset DAC. This family represents cutting-edge innovation, tailored for applications demanding minimal power consumption, superior signal fidelity, high sampling frequencies, broad bandwidth, and heightened integration levels. Each channel is meticulously designed, encompassing programmable input capacitance, a programmable gain amplifier (PGA) for single-ended to differential outputs, an offset DAC, an ADC, and an integrated digital processor. The compact design of these solutions, housed in a standard 12 mm × 12 mm, 196-Ball BGA package, ensures easy integration with existing systems. An integral part of these products is the SCCORETM technology, which significantly cuts down on PCB space and slashes power requirements by up to 50%. These AFEs achieve standardization with features such as an on-chip clock synthesizer and voltage reference, combined with low power usage of 425 mW per channel at peak sampling rates. They support various high-resolution data acquisition applications, enabling versatile use in USB & PC-based oscilloscopes, benchtop digital storage oscilloscopes, and more complex diagnostic tools.
The MIPITM V-NLM-01 is a Non-Local Means (NLM) image noise reduction core, designed to enhance image quality by minimizing noise while preserving detail. This core is highly configurable, allowing users to customize the search window size and the number of bits per pixel, thereby tailoring the noise reduction process to specific application demands. Specially optimized for HDMI output resolutions of 2048x1080 and frame rates from 30 to 60 fps, the V-NLM-01 utilizes an efficient algorithmic approach to deliver natural and artifact-free images. Its parameterized implementation ensures adaptability across various image processing environments, making it essential for applications where high fidelity image quality is critical. The V-NLM-01 exemplifies VLSI Plus Ltd.'s prowess in developing specialized IP cores that significantly enhance video quality. Its capacity to effectively process high-definition video data makes it suitable for integration in a wide range of digital video platforms, ensuring optimal visual output.
The Mixed-Signal CODEC offered by Archband Labs is engineered to enhance the performance of audio and voice devices, handling conversions between analog and digital signals efficiently. Designed to cater to various digital audio interfaces such as PWM, PDM, PCM conversions, I2S, and TDM, it ensures seamless integration into complex audio systems. Well-suited for low-power and high-performance applications, this CODEC is frequently deployed in audio systems across consumer electronics, automotive, and edge computing devices. Its robust design ensures reliable operation within wearables, smart home devices, and advanced home entertainment systems, handling pressing demands for clarity and efficiency in audio signal processing. Engineers benefit from its extensive interfacing capabilities, supporting a spectrum of audio inputs and outputs. The CODEC's compact architecture ensures ease of integration, allowing manufacturers to develop innovative and enhanced audio platforms that meet diverse market needs.
The 10G Ethernet MAC and PCS from Chevin Technology is designed to deliver exceptional network performance for FPGA systems. This IP core boasts high throughput and low latency, ensuring efficient data transmission capabilities. Tailored for flexibility, it can integrate seamlessly into a variety of systems, providing reliability and reduced hardware complexity through its all-logic architecture. Offering compatibility with both Intel and Xilinx FPGAs, the core is intended for high-efficiency applications, making it suitable for use in environments where space and power consumption are critical factors. With its support for the latest Ethernet standards, it enhances network communication within embedded systems. Engineered for design efficiency, this MAC and PCS IP can lower system costs and footprint by fitting numerous cores on a single chip. By maximizing space for other logic components, it provides a cost-effective solution without compromising on performance.
SkyeChip’s High-Speed PLL excels in offering frequency synthesis for a wide range of applications. Capable of supporting reference clock frequencies from 100MHz to 350MHz, it incorporates a versatile FBDIV range, enhancing its division capabilities. The PLL can generate output frequencies ranging from 300MHz to 3.2GHz, marking its adaptability in high-speed data processing. It is designed to consume minimal power, making it an optimal choice in energy-constrained environments. This PLL ensures stability and precision across its frequency range, proving indispensable for modern high-speed digital designs.
The Mixel MIPI D-PHY IP (MXL-DPHY) is a high-frequency low-power, low cost, source-synchronous, physical layer compliant with the MIPI® Alliance Standard for D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) Although primarily used for connecting cameras and display devices to a core processor, this MIPI PHY can also be used for many other applications. It is used in a master-slave configuration, where high-speed signals have a low voltage swing, and low-power signals have large swing. High-speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The D-PHY is partitioned into a Digital Module – CIL (Control and Interface Logic) and a Mixed Signal Module. It is provided as a combination of Soft IP views (RTL, and STA Constraints) for Digital Module, and Hard IP views (GDSII/CDL/LEF/LIB) for the Mixed Signal Module. This unique offering of Soft and Hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the lane module. The interface between the D-PHY and the protocol is called the PHY-Protocol Interface (PPI). During normal operation, the data lane switches between low-power mode and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling certain electrical functions. These enable and disable events do not cause glitches on the lines that would otherwise result in detections of incorrect signal levels. Therefore, all mode and direction changes occur smoothly, ensuring proper detection of the line signals. Mixel’s D-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. This MIPI PHY is fully integrated and has analog circuitry, digital, and synthesizable logic. Our D-PHY is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI) using the PHY Protocol Interface (PPI). Mixel has provided this IP in many different configurations to accommodate different applications. The Universal Lane configuration can be used to support any allowed use-case, while other configurations are optimized for many different use cases such as Transmit only, Receive only, DSI, CSI, TX+ and RX+. Both TX+ and RX+ configurations support full-speed loopback operation without the extra area associated with a universal lane configuration.
Pacific MicroCHIP's REFS serves as a reliable band-gap and PTAT current reference suited for mixed-signal and RF ICs. It offers multiple output current settings, enhancing compatibility across varied circuit designs for consistent performance.
The CT25203 is a component of Canova Tech's comprehensive IP offering, designed for facilitating the development of PMD transceivers compliant with the OA TC14 specification. It interacts efficiently with host MCUs, Zonal Gateway Controllers, or Ethernet switches, delivering robust performance for 10BASE-T1S digital PHY applications. The transceiver's high-voltage process technology enhances EMC performance, with an 8-pin package optimized for compact and efficient design, tailored for automotive and industrial communication requirements.
The ADQ35 model is designed to provide flexible data acquisition with a two-channel configuration operating at a 5 GSPS sampling rate or a single-channel at 10 GSPS. Its programmable DC-offset capability makes this digitizer suitable for sampling unipolar signals. It boasts an open onboard Xilinx Kintex Ultrascale KU115 FPGA which accommodates real-time digital signal processing, ensuring that users can customize their operations seamlessly.
The agileTSENSE_D temperature sensor provides a digital output, extending the capabilities of traditional temperature sensing by incorporating digital signal processing. It retains the core analog sensing mechanism but wraps the output in a digital format for easier integration into modern digital systems, including IoT devices and data centers. This product is designed for environments where digital interfacing is critical. With its adaptable architecture, the agileTSENSE_D delivers precision temperature measurements over a broad operational range, ensuring that systems maintain optimal performance and safety. This functionality is crucial for thermal monitoring and management. Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our automated design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. Our highly configurable and multi-node analog IP products are developed to meet the customer’s exact requirements. These digitally-wrapped and verified solutions can be seamlessly integrated into any SoC, significantly reducing complexity, time and costs.
Dolphin Technology's digital Delay-Locked Loop (DLL) IP offers a cutting-edge solution for precise timing and synchronization in digital circuits. This DLL IP spans a broad frequency range from 40 MHz to 1 GHz, providing flexibility to match specific application requirements. It comes with high precision, controlled through coarse and fine adjustments to reduce resolution error and improve delay accuracy. Designed as a fully digital solution, the DLL has features like external bypass and is developed to minimize EMI, ensuring high signal integrity in densely packed circuits. This suitability for digital integration makes it highly adaptable to various technology nodes, from older generation silicon to advanced process nodes. Ideal for high-speed digital designs, the DLL facilitates efficient communication within semiconductor devices, playing a crucial role in applications requiring synchronized timing across various parts of an integrated circuit. The extensive frequency range further ensures it meets diverse operational needs across a spectrum of industries.
The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components. It employs optional pre-emphasis to enable transmission over a longer distance while achieving low BER. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
Building on its predecessor, the WAVE5 series offers robust multi-standard video encoding capabilities with an established reputation within media and entertainment sectors. WAVE5 is versatile, boasting formats like HEVC and AVC, and delivers outstanding performance, with outputs like 4K240fps at 1GHz. It has been fine-tuned to handle complex multi-instance operations by efficiently managing data transfer and conversion tasks. Its ability to maintain high visual fidelity while offering low installation costs makes it a strategic choice for multiple application fields such as automotive and mobile entertainment. The use of secondary AXI ports and a fully integrated rotation and scaling mechanic add to its versatility.
The ePHY-5616 product is crafted to handle data rates from 1 to 56Gbps. Operating prominently on 16 and 12nm technology nodes, this solution is ideal for applications that demand scalable insertion loss and data rate adaptability. The architecture is robust, leveraging advanced DSP techniques to provide exceptional clock data recovery and superior BER (Bit Error Rate), catering to both enterprise and data center needs. Its utility extends to routers, switches, and other critical data infrastructure components.
The MIPITM CSI2MUX-A1F stands as a formidable CSI2 Video Multiplexor, crafted to manage inputs from multiple cameras, aggregating them into a single enhanced video stream. Compatible with CSI2 rev 1.3 and DPHY rev 1.2 protocols, it boasts the ability to handle input from up to four CSI2 cameras, funneling this data into a unified, high-quality video output. This multiplexor excels in consolidating various video inputs, making it an optimal choice for systems necessitating centralized video management. With a capacity of 4 x 1.5Gbps, it ensures there is no compromise on video quality or frame rate, maintaining high fidelity throughout the transmission. Offering an effective solution for video intensive applications, the MIPITM CSI2MUX-A1F reflects VLSI Plus Ltd.’s commitment to delivering reliable and high-performance multiplexer solutions. It provides a streamlined approach to handling video inputs, supporting applications where space and efficiency are paramount.
The MVH4000 series is a line of highly precise and fully calibrated humidity and temperature sensors. Utilizing a unique Silicon Carbide MEMS technology, these sensors boast outstanding long-term stability, quick response times, and low power usage. Their compact size makes them ideal for applications where space is at a premium, offering significant advantages in battery-powered and time-sensitive environments. Long-term reliability, minimal power draw, and robustness are key features of the MVH4000 sensors, making them a top choice for demanding applications with critical process controls.
The MVPM100 series represents a breakthrough in microsystem technologies by miniaturizing the precision of traditional gravimetric particle measurement into a compact form. Unlike optical sensors, it directly measures particle mass, cutting down on size while maintaining accuracy. This series is designed for applications requiring precision in air quality measurement, from industrial to commercial use, offering low power consumption and high accuracy in particle weight detection, making it ideal for modern air monitoring systems.
Pacific MicroCHIP's DIV60G is a fully differential frequency divider reaching up to 60GHz, integral to high-performance broadband test and measurement equipment. It includes an active balun and provides I/Q differential outputs, catering to the precise requirements of ultrahigh frequency applications.
The HOTLink II Product Suite from Great River Technology is tailored for high-speed data transmission in demanding aerospace environments. This solution integrates seamlessly into avionics systems, providing robust performance for data-intensive applications. Known for its efficiency and reliability, the HOTLink II suite is ideal for organizations requiring consistent and high-speed data transfer capabilities. Designed for maximum compatibility, the HOTLink II suite supports various hardware configurations and software interfaces, ensuring smooth transitions between system components. The suite offers a comprehensive array of tools that facilitate the integration and management of high-speed data links within sophisticated avionics architectures. Whether in development or deployment, the HOTLink II suite provides unparalleled support and flexibility. In addition to its core functionalities, the HOTLink II suite assists in optimizing data integrity and system robustness throughout the system's lifecycle. Its design reflects Great River Technology's expertise in data solutions, promising long-term reliability and performance in mission-critical applications.
The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY and a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) In LVDS mode, both the serial and parallel data are organized into 4 channels. The parallel data is 7 bits wide per channel. The input clock is 25MHz to 150MHz. The serializer is highly integrated and requires no external components. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
The Mixel MIPI C/D-PHY combo IP (MXL-CPHY-DPHY) is a high-frequency low-power, low cost, physical layer compliant with the MIPI® Alliance Standard for C-PHY and D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The PHY can be configured as a MIPI Master or MIPI Slave, supporting camera interface CSI-2 v1.2 or display interface DSI v1.3 applications in the D-PHY mode. It also supports camera interface CSI-2 v1.3 and display interface DSI-2 v1.0 applications in the C-PHY mode. The high-speed signals have a low voltage swing, while low-power signals have large swing. High-Speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The C-PHY is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios, operating with a symbol rate range of 80 to 4500 Msps per lane, which is the equivalent of about 182.8 to 10260 Mbps per lane. The D-PHY supports a bit rate range of 80 to 1500 Mbps per Lane without deskew calibration, and up to 4500 Mbps with deskew calibration. The low-power mode and escape mode are the same in both the D-PHY and C-PHY modes. To minimize EMI, the drivers for low-power mode are slew-rate controlled and current limited. The data rate in low-power mode is 10 Mbps. For a fixed clock frequency, the available data capacity of a PHY configuration can be increased by using more lanes. Effective data throughput can be reduced by employing burst mode communication. Mixel’s C-PHY/D-PHY combo is a complete PHY, silicon-proven at multiple foundries and multiple nodes. The C/D-PHY is fully integrated and has analog circuitry, digital, and synthesizable logic.
The JPEG Codec/CODA/BODA platform stands out in multi-standard JPEG and video encoding/decoding technologies, serving critical roles in mobile and automotive systems, as well as medical imaging. It adheres to the ISO/IEC 10918-1 JPEG standard, providing flexible image and video management through customizable encoders and decoders. The architecture is designed to manage a wide variety of colors and formats, ensuring clarity and quality across applications. The engine's speed is impressive, showing prowess in managing up to 290M pixels per second, for both encoding and decoding routines. This efficiency and comprehensive format support make it an ideal solution for high-demand imaging fields.
Advinno Technologies presents their Oscillator product, which is pivotal for frequency generation and stabilization in electronic circuits. This oscillator is finely tuned to offer precise control over frequency, making it an invaluable component for timing and synchronization tasks. Its ability to deliver stable signals is essential for maintaining performance integrity across various applications. The design emphasizes minimizing signal jitter and maximizing reliability, making Advinno's Oscillator ideal for both consumer devices and industrial systems requiring exact timing and synchronization. Through advanced development techniques, the oscillator can maintain exceptional frequency precision even under varied environmental conditions, such as temperature fluctuations, thereby ensuring consistent performance. Advinno's commitment to leveraging cutting-edge technology is evident in this oscillator's compatibility with a wide range of operating conditions and its adaptability to various electronic applications. The result is a versatile and efficient solution for developers and designers looking to enhance their system's reliability and timing accuracy.
The RIOT100 is designed for optimal energy savings and enhanced automation in lighting and security systems. Utilizing unique mmWave capabilities, it accurately senses human presence by detecting micromovements, ensuring functionality across various ambient conditions. Discreetly integrable behind different materials, RIOT100 offers privacy-focused applications ideal for both residential and commercial settings.
TimeServoPTP extends the capabilities of the TimeServo System Timer to provide a complete IEEE 1588v2 Precision Time Protocol (PTP) Ordinary Clock (OC) solution for FPGAs. This implementation supports both 1-Step and 2-Step synchronization with a network time grandmaster, ensuring accurate time alignment within a communication system. The IP is designed to interface directly with a PTP master through Ethernet, utilizing L2 EtherType frames for communication. It features flexible clocking options and independent time output domains, providing up to 32 precise timing outputs. Each output can be individually configured in various formats and includes a pulse-per-second signal for precise timing applications. TimeServoPTP employs a Gardner Type-2 digital phase-locked loop (DPLL) to maintain synchronization accuracy, leveraging FPGA resources efficiently. This solution supports Intel Agilex and Xilinx UltraScalePlus devices, demonstrating its adaptability across different hardware platforms.