All IPs > Graphic & Peripheral
Graphic & Peripheral Semiconductor IPs are critical components in the design and development of electronics that require efficient and robust control over multimedia and peripheral functions. This category of semiconductor IP encompasses a wide array of technologies used to manage and optimize graphics rendering, audio processing, data communication, and peripheral interfaces in electronic devices such as computers, smartphones, tablets, and other smart gadgets.
In this vivid category, you'll find a variety of subcategories tailored to specific functionalities. For instance, the Graphics Processing Unit (GPU) semiconductor IPs are pivotal for rendering images and video, essential in gaming, virtual reality, and professional content creation. Audio Controllers handle sound processing, ensuring crisp and seamless audio output, crucial for devices prioritizing high-quality sound delivery.
Other key components in the Graphic & Peripheral category include Peripheral Controllers, which facilitate the integration of various input/output devices, enhancing the device's interactivity and user experience. DMA Controllers are responsible for moving data efficiently between memory and peripherals, minimizing the CPU load. These IPs enhance overall system performance by ensuring that data flow is smooth and uninterrupted.
From Clock Generators that synchronize the entire system's operations to Interrupt Controllers managing priority tasks, each semiconductor IP in this category plays a unique role in ensuring that electronic devices operate at peak efficiency. By exploring these subcategories, companies and developers can find the precise semiconductors needed to support cutting-edge multimedia and peripheral technologies in their next product launch.
Overview: The UCIe IP supports multiple protocols (CXL/PCIe/Streaming) to connect chiplets, reducing overall development cycles for IPs and SOCs. With flexible application and PHY interfaces, The UCIe IP is ideal for SOCs and chiplets. Key Features:  Supports UCIe 1.0 Specification  Supports CXL 2.0 and CXL 3.0 Specifications  Supports PCIe Gen6 Specification  Supports PCIe Gen5 and older versions of PCIe specifications  Supports single and two-stack modules  Supports CXL 2.0 68Byte flit mode with Fallback mode for PCIe non-flit mode transfers  Supports CXL 3.0 256Byte flit mode  Supports PCIe Gen6 flit mode  Configurable up to 64-lane configuration for Advanced UCIe modules and 16 lanes for Standard UCIe modules  Supports sideband and Mainband signals  Supports Lane repair handling  Data to clock point training and eye width sweep support from transmitter and receiver ends  UCIe controller can work as Downstream or Upstream  Main Band Lane reversal supported  Dynamic sense of normal and redundant clock and data lines activation  UCIe enumeration through DVSEC  Error logging and reporting supported  Error injection supported through Register programming  RDI/FDI PM entry, Exit, Abort flows supported  Dynamic clock gang at adapter supported Configurable Options:  Maximum link width (x1, x2, x4, x8, x16)  MPS (128B to 4KB)  MRRS (128B to 4KB)  Transmit retry/Receive buffer size  Number of Virtual Channels  L1 PM substate support  Optional Capability Features can be Configured  Number of PF/VFDMA configurable Options  AXI MAX payload size Variations  Multiple CPI Interfaces (Configurable)  Cache/memory configurable  Type 0/1/2 device configurable
Our Expanded Serial Peripheral Interface (JESD251) Master controller features a low signal count and high data bandwidth, making it ideal for use in computing, automotive, Internet of Things, embedded systems, and mobile system processors. It connects multiple sources of Serial Peripheral Interface (xSPI) slave devices, including nonvolatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports a single master and multiple slaves per interface port. • Supports Single Data Rate and Double Data Rate. • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for writemasking. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands to read or writedata for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
Overview: The Expanded Serial Peripheral Interface (xSPI) Master/Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy SPI devices. It is designed to connect xSPI Master/Slave devices in computing, automotive, Internet of Things, embedded systems, and mobile processors to various peripherals such as non-volatile memories, graphics peripherals, networking devices, FPGAs, and sensor devices. Key Features:  Compliance with JEDEC standard JESD251 eXpanded SPI for Non-Volatile Memory Devices, Version 1.0  Support for Single master and multiple slaves per interface port  Single Data Rate (SDR) and Double Data Rate (DDR) support  Source synchronous clocking  Deep Power Down (DPD) enter and exit commands  Eight IO ports in standard, expandable based on system requirements  Optional Data Strobe (DS) for write masking  bit wide SDR transfer support  Profile 1.0 Commands for non-volatile memory device management  Profile 2.0 Commands for read or write data for various slave devices Applications:  Consumer Electronics  Defense & Aerospace  Virtual Reality  Augmented Reality  Medical  Biometrics  Automotive Devices  Sensor Devices
Overview: The Multi-Protocol Accelerator IP is a versatile technology designed to support low latency and high bandwidth accelerators for efficient CPU-to-device and CPU-to-memory communication. It also enables switching for fan-out to connect more devices, memory pooling for increased memory utilization efficiency, and provides memory capacity with support for hot-plug, security enhancements, persistent memory support, and memory error reporting. Key Features:  CXL 3.0 Support: Compliant with CXL spec V3.X/V2.X  PCIe Compatibility: Supports PCIe spec 6.0/5.0  CPI Interface: Support for CPI Interface  AXI Interface: Configurable AXI master, AXI slave  Bus Support: PIPE/FLEX bus, Lane x1,x2,x4,x8,x16  Protocol Support: Gen3, Gen4, Gen5 & Gen6, Fallback Mode  Register Checks: Configuration and Memory Mapped registers  Dual Mode: Supports Dual Mode operation  Transfer Support: HBR/PBR & LOpt Transfers, Standard Cache and Mem Transfers  CXL Support: Can function as both CXL host and device  Data Transfer: Supports Standard IO, 68Byte Flit, and 256Byte Flit Transfers  FlexBus Features: FlexBus Link Features, ARB/MUX, ARB/MUX Bypass  Optimization: Latency Optimization, Credit Return Forcing, Empty Flits (Latency Optimized)  Power Management: Supports Power Management features  Enhancements: CXL IDE, RAS Features, Poison & Viral Handling, MLD/SLD  Testing: Compliance Testing and Error Scenarios support
Our Expanded Serial Peripheral Interface (JESD251) Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface (SPI) devices. It is used to connect xSPI Master devices in computing, automotive, Internet of Things, embedded systems, and mobile system processors to non-volatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports Single Data Rate (SDR) and Double Data Rate (DDR). • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for timing reference. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands for reading or writing data for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
Overview: PCIe Gen6 is a high-speed, layered protocol interconnect interface supporting speeds up to 64GT/s, featuring multi-lanes and links. The Transport, Data Link, and Physical layers specified in the PCIe specification are implemented, along with PIPE interface logic connecting to PHY and AXI Bridging logic for application connectivity. Specifications:  Supports PCIe Gen 6 and Pipe 5.X Specifications  Core supports Flit and non-Flit Mode  Lane Configurations: X16, X8, X4, X2, X1  AXI MM and Streaming supported  Supports Gen1 to Gen6 modes  Data rate support of 2.5 GT/s, 5 GT/s, 8 GT/s, 16 GT/s, 32 GT/s, 64 GT/s  PAM support when operating at 64GT/s  Encoding/Decoding Support: 8b/10b, 128b/130b, 1b/1b  Supports SerDes and non-SerDes architecture  Optional DMA support as plugin module  Support for alternate negotiation protocol  Can operate as an endpoint or root complex  Lane polarity control through register  Lane de-skew supported  Support for L1 states and L0P  Support for SKP OS add/removal and SRIS mode  No equalization support through configuration  Deemphasis negotiation support at 5GT/s  Supports EI inferences in all modes  Supports PTM, OBFF, MSI, MSIX, Power management, and all message formats
Silicon Creations' Free Running Oscillators provide dependable timing solutions for a range of applications such as watchdog timers and core clock generators in low-power systems. These oscillators, crafted with compactness and efficiency in mind, support a gamut of processes from 65nm to the latest 3nm technologies. These oscillators excel in low power consumption, often requiring less than 30µW during operation. Their robust design ensures they deliver high precision over a temperature range from -40°C to 125°C with supply voltage variabilities factored in. The simplicity in design negates the need for external components, promoting easier integration and reduced overall system complexity. Precise tuning capabilities allow for accuracy levels up to ±1.5% after process trimming, ensuring outstanding performance in volatile environmental conditions. This level of reliability makes them ideal for integration into various consumer electronics, automotive controls, and other precision-demanding applications where space and power constraints are critical.
Silicon Creations' Analog Glue solutions provide essential analog functionalities to complete custom SoC designs seamlessly. These functional blocks, which constitute buffer and bandgap reference circuits, are vital for seamless on-chip clock distribution and ensure low-jitter operations. Analog Glue includes crucial components such as power-on reset (POR) generators and bridging circuits to support various protocols and interfaces within SoCs. These supplementary macros are crafted to complement existing PLLs and facilities like SerDes, securing reliable signal transmission under varied operating circumstances. Serving as the unsung heroes of chip integration, these Analog Glue functions mitigate the inevitable risks of complex SoC designs, supporting efficient design flows and effective population of chip real estate. Thus, by emphasizing critical system coherency, they enhance overall component functionality, providing a stable infrastructure upon which additional system insights can be leveraged.
The eSi-Connect suite provides a wide array of AMBA-compliant peripheral IP designed to simplify and standardize connectivity and integration within complex SoC environments. This suite includes versatile memory controllers and wide-ranging off-chip interfaces like USB, I2C, and UART, enabling comprehensive system integration. Each peripheral block within eSi-Connect is highly configurable, allowing tailored deployment backed by low-level software drivers to assure real-time performance. The integration is streamlined through standardized interfaces that facilitate seamless incorporation into existing systems. eSi-Connect is engineered for adaptability and efficiency, supporting communication protocols and control functions essential for a variety of real-time applications, ensuring robust and flexible peripheral connectivity in embedded environments.
The KL730 AI SoC is equipped with a state-of-the-art third-generation reconfigurable NPU architecture, delivering up to 8 TOPS of computational power. This innovative architecture enhances computational efficiency, particularly with the latest CNN networks and transformer applications, while reducing DDR bandwidth demands. The KL730 excels in video processing, offering support for 4K 60FPS output and boasts capabilities like noise reduction, wide dynamic range, and low-light imaging. It is ideal for applications such as intelligent security, autonomous driving, and video conferencing.
Silicon Creations crafts highly reliable LVDS interfaces designed to meet diverse application needs, going from bi-directional I/Os to specialized uni-directional configurations. Spanning process compatibilities from 90nm CMOS to advanced 7nm FinFET, these interfaces are a cornerstone for high-speed data communication systems, thriving particularly in video data transmission and chip-to-chip communications. Supporting robust data rates over multiple channels, the LVDS Interfaces guarantee flexible programmability and protocol compatibility with standards such as FPD-Link and Camera-Link. They capitalize on proven PLL and CDR architectures for superior signal integrity and error-free data transfers. Operating efficiently in various technology nodes, they remain highly effective across collaborative chipset environments. The interfaces are fortified with adaptable features like dynamic phase alignment to stabilize data sequences and on-die termination options for superior signal integrity. Their proven record places them as a critical enabler in applications where consistent high-speed data transfer is paramount, demonstrating Silicon Creations’ prowess in delivering industry-leading communication solutions.
Silicon Creations delivers precision LC-PLLs designed for ultra-low jitter applications requiring high-end performance. These LC-tank PLLs are equipped with advanced digital architectures supporting wide frequency tuning capabilities, primarily suited for converter and PHY applications. They ensure exceptional jitter performance, maintaining values well below 300fs RMS. The LC-PLLs from Silicon Creations are characterized by their capacity to handle fractional-N operations, with active noise cancellation features allowing for clean signal synthesis free of unwanted spurs. This architecture leads to significant power efficiencies, with some IPs consuming less than 10mW. Their low footprint and high frequency integrative capabilities enable seamless deployments across various chip designs, creating a perfect balance between performance and size. Particular strength lies in these PLLs' ability to meet stringent PCIe6 reference clocking requirements. With programmable loop bandwidth and an impressive tuning range, they offer designers a powerful toolset for achieving precise signal control within cramped system on chip environments. These products highlight Silicon Creations’ commitment to providing industry-leading performance and reliability in semiconductor design.
The Aries fgOTN processor family is engineered according to the ITU-T G.709.20 fgOTN standard. This line of processors handles a variety of signals, including E1/T1, FE/GE, and STM1/STM4, effectively monitoring and managing alarms and performance metrics. Aries processors excel at fine-grain traffic aggregation, efficiently channeling fgODUflex traffic across OTN lines to support Ethernet, SDH, PDH client services. Their capacity to map signals to fgODUflex containers, which are then multiplexed into higher order OTN signals, demonstrates their versatility and efficiency. By allowing cascaded configurations with other Aries devices or Apodis processors, Aries products optimize traffic routes through OTN infrastructures, positioning them as essential components in optical networking and next-generation access scenarios.
The Origin E1 neural engines by Expedera redefine efficiency and customization for low-power AI solutions. Specially crafted for edge devices like home appliances and security cameras, these engines serve ultra-low power applications that demand continuous sensing capabilities. They minimize power consumption to as low as 10-20mW, keeping data secure and eliminating the need for external memory access. The advanced packet-based architecture enhances performance by facilitating parallel layer execution, thereby optimizing resource utilization. Designed to be a perfect fit for dedicated AI functions, Origin E1 is tailored to support specific neural networks efficiently while reducing silicon area and system costs. It supports various neural networks, from CNNs to RNNs, making it versatile for numerous applications. This engine is also one of the most power-efficient in the industry, boasting an impressive 18 TOPS per Watt. Origin E1 also offers a full TVM-based software stack for easy integration and performance optimization across customer platforms. It supports a wide array of data types and networks, ensuring flexibility and sustained power efficiency, averaging 80% utilization. This makes it a reliable choice for OEMs looking for high performance in always-sensing applications, offering a competitive edge in both power efficiency and security.
Archband Labs offers a PDM-to-PCM Converter that excels in translating Pulse Density Modulated (PDM) audio signals into Pulse Code Modulated (PCM) format. This conversion is crucial in audio signal processing where digital formats require conversions for accurate playback or further audio processing. Ideal for modern multimedia systems and portable audio devices, the PDM-to-PCM Converter provides high fidelity in signal conversion, ensuring sound quality is preserved during the process. This IP is highly efficient, making it perfect for applications where power conservation is important, such as battery-powered gadgets and smart wearables. Its compact design provides easy integration into existing systems, facilitating upgrades without significant redesigns. With reliable performance, this converter supports the growing demand for adaptable and high-efficiency audio processing solutions, aiding engineers in achieving cutting-edge audio clarity.
This timer module adheres to the RISC-V Privileged 1.9.1 specifications, ensuring accurate timing operations across embedded applications. It is an essential tool for managing task scheduling and execution timing, increasing the efficacy of time-sensitive processes. The module's customizable nature allows it to be adjusted to meet specific temporal needs of various embedded designs.
The Origin E8 NPUs represent Expedera's cutting-edge solution for environments demanding the utmost in processing power and efficiency. This high-performance core scales its TOPS capacity between 32 and 128 with single-core configurations, addressing complex AI tasks in automotive and data-centric operational settings. The E8’s architecture stands apart due to its capability to handle multiple concurrent tasks without any compromise in performance. This unit adopts Expedera's signature packet-based architecture for optimized parallel execution and resource management, removing the necessity for hardware-specific tweaks. The Origin E8 also supports high input resolutions up to 8K and integrates well across standard and custom neural networks, enhancing its utility in future-forward AI applications. Leveraging a flexible, scalable design, the E8 IP cores make use of an exhaustive software suite to augment AI deployment. Field-proven and already deployed in a multitude of consumer vehicles, Expedera's Origin E8 provides a robust, reliable choice for developers needing optimized AI inference performance, ideally suited for data centers and high-power automobile systems.
The Ring PLLs offered by Silicon Creations illustrate a versatile clocking solution, well-suited for numerous frequency generation tasks within integrated circuit designs. Known for their general-purpose and specialized applications, these PLLs are crafted to serve a massive array of industries. Their high configurability makes them applicable for diverse synthesis needs, acting as the backbone for multiple clocking strategies across different environments. Silicon Creations' Ring PLLs epitomize high integration with functions tailored for low jitter and precision clock generation, suitable for battery-operated devices and systems demanding high accuracy. Applications span from general clocking to precise Audio Codecs and SerDes configurations requiring dedicated performance metrics. The Ring PLL architecture achieves best-in-class long-term and period jitter performance with both integer and fractional modes available. Designed to support high volumes of frequencies with minimal footprint, these PLLs aid in efficient space allocation within system designs. Their use of silicon-proven architectures and modern validation methodologies assure customers of high reliability and quick integration into existing SoC designs, emphasizing low risk and high reward configurations.
A2e Technologies offers a cutting-edge H.264 FPGA Encoder and CODEC that promises the industry's smallest and fastest solution with ultra-low latency. This core is ITAR-compliant and adaptable, capable of delivering a 1080p60 video stream while retaining a minimal footprint. The H.264 core is engineered to adapt to unique pixel depths and resolutions, leveraging a modular design that allows for seamless integration into a variety of FPGA environments. Supporting both I and P frames, this encoder ensures robust video compression with customizable configurations for various applications. The core's flexibility extends to its ability to handle multiple video streams with differing sizes or compression ratios simultaneously. Its fully synchronous design supports resolutions up to 4096 x 4096, illustrating its capacity to manage high-definition sources effectively. The flexibility in design permits its application across FPGAs from numerous manufacturers, including Xilinx and AMD, making it versatile for diverse project requirements. With enhancements like an improved AXI wrapper for better integration and significant reductions in RAM needs for raster-to-macroblock transformations, A2e's H.264 Encoder is equipped for high performance. It supports a variety of encoding styles with a processing rate of 1.5 clocks per pixel and includes comprehensive deliverables such as FPGA-specific netlists and testing environments to ensure a swift and straightforward deployment.
The NoC Bus Interconnect from OPENEDGES Technology is an integral component of the ORBIT Memory Subsystem, engineered to offer high performance and efficient area use in semiconductor designs. Its design is centered around facilitating exceptional connectivity and adaptability within system-on-chip (SoC) architectures, employing an automated end-to-end interconnect generation flow. This interconnect solution excels in delivering high-speed routing with low latency, thanks to its use of HyperPath technology which enables superior throughput and flexibility in physical design. The NoC Bus Interconnect's ability to dynamically control bandwidth and latency, coupled with efficient clocking methods, supports diverse applications ranging from AI/ML to automotive technology. Incorporating advanced ActiveQoS bandwidth management, this interconnect offers significant advantages in managing traffic, reducing congestion, and enhancing overall SoC performance. It features long-distance Asynchronous Bridge (LDA) technology, optimizing connections across distant domains on a chip without the added complexity of a typical register slice scheme.
The Apodis family of Optical Transport Network processors adheres to ITU-T standards, offering a comprehensive suite for signal termination, processing, and multiplexing. Designed to handle both SONET/SDH and Ethernet client services, these processors map signals to Optical Transport Network (OTN), empowering versatile any-port, any-service configurations. Apodis processors are notable for their capacity to support up to 16 client ports and four 10G OTN line ports, delivering bandwidth scalability up to 40G, crucial for wireless backhaul and fronthaul deployments. With a robust, non-blocking OTN switching fabric, Apodis facilitates seamless client-to-line and line-to-line connections while optimally managing network bandwidth. This adaptability makes the Apodis processors an ideal choice for next-generation access networks and optical infrastructures.
The MIPITM V-NLM-01 is a Non-Local Means (NLM) image noise reduction core, designed to enhance image quality by minimizing noise while preserving detail. This core is highly configurable, allowing users to customize the search window size and the number of bits per pixel, thereby tailoring the noise reduction process to specific application demands. Specially optimized for HDMI output resolutions of 2048x1080 and frame rates from 30 to 60 fps, the V-NLM-01 utilizes an efficient algorithmic approach to deliver natural and artifact-free images. Its parameterized implementation ensures adaptability across various image processing environments, making it essential for applications where high fidelity image quality is critical. The V-NLM-01 exemplifies VLSI Plus Ltd.'s prowess in developing specialized IP cores that significantly enhance video quality. Its capacity to effectively process high-definition video data makes it suitable for integration in a wide range of digital video platforms, ensuring optimal visual output.
Origin E2 NPUs focus on delivering power and area efficiency, making them ideal for on-device AI applications in smartphones and edge nodes. These processing units support a wide range of neural networks, including video, audio, and text-based applications, all while maintaining impressive performance metrics. The unique packet-based architecture ensures effective performance with minimal latency and eliminates the need for hardware-specific optimizations. The E2 series offers customization options allowing it to fit specific application needs perfectly, with configurations supporting up to 20 TOPS. This flexibility represents significant design advancements that help increase processing efficiency without introducing latency penalties. Expedera's power-efficient design results in NPUs with industry-leading performance at 18 TOPS per Watt. Further augmenting the value of E2 NPUs is their ability to run multiple neural network types efficiently, including LLMs, CNNs, RNNs, and others. The IP is field-proven, deployed in over 10 million consumer devices, reinforcing its reliability and effectiveness in real-world applications. This makes the Origin E2 an excellent choice for companies aiming to enhance AI capabilities while managing power and area constraints effectively.
The UART Serial Communication Controller provides reliable asynchronous communication over serial interfaces, vital for a broad range of applications from embedded systems to consumer electronics. This IP core supports standard UART communication, ensuring dependable data exchange between processors and serial devices. Designed for integration with AMBA interconnects, the controller smoothly interfaces with high-performance processors, supporting versatile communication needs. It allows for effective off-loading of processing tasks, ensuring the host system can devote more resources to its core functionalities or other demanding processes. The controller's design allows it to fit snugly within systems requiring robust, serial data transmission capabilities. With support for multiple baud rates and a variety of configuration options, it lends itself well to diverse applications, from low-power devices to high-speed computing environments. By offering well-documented resources and test simulations, Digital Blocks ensures that this UART controller can be efficiently incorporated into diverse projects, providing adaptability and efficiency in handling serial communication protocols across widely varied system architectures.
The Mixed-Signal CODEC offered by Archband Labs is engineered to enhance the performance of audio and voice devices, handling conversions between analog and digital signals efficiently. Designed to cater to various digital audio interfaces such as PWM, PDM, PCM conversions, I2S, and TDM, it ensures seamless integration into complex audio systems. Well-suited for low-power and high-performance applications, this CODEC is frequently deployed in audio systems across consumer electronics, automotive, and edge computing devices. Its robust design ensures reliable operation within wearables, smart home devices, and advanced home entertainment systems, handling pressing demands for clarity and efficiency in audio signal processing. Engineers benefit from its extensive interfacing capabilities, supporting a spectrum of audio inputs and outputs. The CODEC's compact architecture ensures ease of integration, allowing manufacturers to develop innovative and enhanced audio platforms that meet diverse market needs.
The Chimera GPNPU by Quadric is a versatile processor specifically designed to enhance machine learning inference tasks on a broad range of devices. It provides a seamless blend of traditional digital signal processing (DSP) and neural processing unit (NPU) capabilities, which allow it to handle complex ML networks alongside conventional C++ code. Designed with a focus on adaptability, the Chimera GPNPU architecture enables easy porting of various models and software application programming, making it a robust solution for rapidly evolving AI technologies. A key feature of the Chimera GPNPU is its scalable design, which extends from 1 to a remarkable 864 TOPs, catering to applications from standard to advanced high-performance requirements. This scalability is coupled with its ability to support a broad range of ML networks, such as classic backbones, vision transformers, and large language models, fulfilling various computational needs across industries. The Chimera GPNPU also excels in automotive applications, including ADAS and ECU systems, due to its ASIL-ready design. The processor's hybrid architecture merges Von Neumann and 2D SIMD matrix capabilities, promoting efficient execution of scalar, vector, and matrix operations. It boasts a deterministic execution pipeline and extensive customization options, including configurable instruction caches and local register memories that optimize memory usage and power efficiency. This design effectively reduces off-chip memory accesses, ensuring high performance while minimizing power consumption.
The KL630 AI SoC embodies next-generation AI chip technology with a pioneering NPU architecture. It uniquely supports Int4 precision and transformer networks, offering superb computational efficiency combined with low power consumption. Utilizing an ARM Cortex A5 CPU, it supports a range of AI frameworks and is built to handle scenarios from smart security to automotives, providing robust capability in both high and low light conditions.
The AXI4 DMA Controller is designed to manage data transfers efficiently across multiple channels, supporting up to 16 independent streams between various sources and destinations. Capable of handling high throughput across both small and large data sets, this DMA controller provides enhanced data management and reliability in system operations focused on data-centric tasks. This controller offers configurable parameters for its channels, each possessing independent read and write controllers to optimize data handling flows. It supports scatter-gather linked-list control and can manage complex data flow patterns, thereby reducing processing overhead and enhancing overall system performance. The flexibility of AXI3 and AXI4 burst features further accentuates its versatility, providing customizable data widths ranging from 8 to 1024 bits, making it well-suited for a diverse array of applications from networking to embedded systems. Offering a sparse footprint, the controller integrates seamlessly with different system architectures, supporting various AXI configurations that allow for simpler integration with existing AMBA-connected systems. Its design emphasizes minimizing silicon usage while maintaining robust functionality to fit custom project requirements, thereby reducing implementation and operational costs. The available design options together with a comprehensive set of evaluation and test resources provide significant development advantages to teams working across platforms like RISC-V or ARM-based systems, thereby facilitating agile project development and optimization.
The Configurable I/O from SkyeChip encompasses a high-speed interface solution capable of supporting multiple I/O standards such as LVDS and POD. It enables signaling speeds up to 3.2 GT/s, accommodating a variety of voltage levels from 1.1V to 1.5V, enhancing its versatility across applications. This IP is engineered for flexibility, allowing integration with diverse system architectures, and supports various signaling standards effortlessly. Its design ensures robust data transmission capabilities, essential for high-performance computing and integrated system environments.
The xcore.ai platform by XMOS Semiconductor is a sophisticated and cost-effective solution aimed specifically at intelligent IoT applications. Harnessing a unique multi-threaded micro-architecture, xcore.ai provides superior low latency and highly predictable performance, tailored for diverse industrial needs. It is equipped with 16 logical cores divided across two multi-threaded processing tiles. These tiles come enhanced with 512 kB of SRAM and a vector unit supporting both integer and floating-point operations, allowing it to process both simple and complex computational demands efficiently. A key feature of the xcore.ai platform is its powerful interprocessor communication infrastructure, which enables seamless high-speed communication between processors, facilitating ultimate scalability across multiple systems on a chip. Within this homogeneous environment, developers can comfortably integrate DSP, AI/ML, control, and I/O functionalities, allowing the device to adapt to specific application requirements efficiently. Moreover, the software-defined architecture allows optimal configuration, reducing power consumption and achieving cost-effective intelligent solutions. The xcore.ai platform shows impressive DSP capabilities, thanks to its scalar pipeline that achieves up to 32-bit floating-point operations and peak performance rates of up to 1600 MFLOPS. AI/ML capabilities are also robust, with support for various bit vector operations, making the platform a strong contender for AI applications requiring homogeneous computing environments and exceptional operator integration.
The ADQ35 model is designed to provide flexible data acquisition with a two-channel configuration operating at a 5 GSPS sampling rate or a single-channel at 10 GSPS. Its programmable DC-offset capability makes this digitizer suitable for sampling unipolar signals. It boasts an open onboard Xilinx Kintex Ultrascale KU115 FPGA which accommodates real-time digital signal processing, ensuring that users can customize their operations seamlessly.
The DisplayPort and Embedded DisplayPort (eDP) IP offered by Silicon Library deliver advanced video interface solutions, providing high-resolution video signal transmission. Supporting the latest DisplayPort standards, this IP achieves efficient data transfer suitable for both standalone and embedded systems. Applications benefiting from this IP include monitors, laptops, and mobile devices where high-quality display performance is crucial. The DisplayPort/eDP IP supports high-definition audio and video, ensuring excellent media streaming and integration with contemporary display technologies. Its design is optimized for power efficiency, making it a suitable choice for portable devices. The IP includes support for high dynamic range video, which improves image clarity and contrast, catering to advanced multimedia applications. Moreover, its flexible design allows it to seamlessly integrate with various system architectures, providing a robust solution for next-generation display interfaces.
The Origin E6 neural engines are built to push the boundaries of what's possible in edge AI applications. Supporting the latest in AI model innovations, such as generative AI and various traditional networks, the E6 scales from 16 to 32 TOPS, aimed at balancing performance, efficiency, and flexibility. This versatility is essential for high-demand applications in next-generation devices like smartphones, digital reality setups, and consumer electronics. Expedera’s E6 employs packet-based architecture, facilitating parallel execution that leads to optimal resource usage and eliminating the need for dedicated hardware optimizations. A standout feature of this IP is its ability to maintain up to 90% processor utilization even in complex multi-network environments, thus proving its robustness and adaptability. Crafted to fit various use cases precisely, E6 offers a comprehensive TVM-based software stack and is well-suited for tasks that require simultaneous running of numerous neural networks. This has been proven through its deployment in over 10 million consumer units. Its design effectively manages power and system resources, thus minimizing latency and maximizing throughput in demanding scenarios.
The G-Series Controller from MEMTECH is conceived for graphics-heavy computing environments, balancing high bandwidth and low power demands. This controller supports GDDR6 devices at speeds reaching up to 18 Gbps. It incorporates dual-channel support, advanced scheduling, and error detection ensuring robust data throughput with minimal latency. Suitable for applications such as gaming, video processing, and AI, the G-Series Controller facilitates efficient integration and supports various power-saving features.
The MIPITM CSI2MUX-A1F stands as a formidable CSI2 Video Multiplexor, crafted to manage inputs from multiple cameras, aggregating them into a single enhanced video stream. Compatible with CSI2 rev 1.3 and DPHY rev 1.2 protocols, it boasts the ability to handle input from up to four CSI2 cameras, funneling this data into a unified, high-quality video output. This multiplexor excels in consolidating various video inputs, making it an optimal choice for systems necessitating centralized video management. With a capacity of 4 x 1.5Gbps, it ensures there is no compromise on video quality or frame rate, maintaining high fidelity throughout the transmission. Offering an effective solution for video intensive applications, the MIPITM CSI2MUX-A1F reflects VLSI Plus Ltd.’s commitment to delivering reliable and high-performance multiplexer solutions. It provides a streamlined approach to handling video inputs, supporting applications where space and efficiency are paramount.
The xT CDx is an advanced FDA-approved assay designed for tumor and normal DNA sequencing. Incorporating a comprehensive 648-gene panel, this assay provides critical insights for diagnosing and treating solid tumors, with specific functions in guiding targeted therapies in colorectal cancer patients. The test includes a thorough mutation profiling system that allows healthcare professionals to analyze substitutions, insertions, and deletions, delivering a powerful means to refine treatment options. Beyond the standard, the xT CDx offers tumor and normal matched sequencing to distinguish somatic alterations, reducing false-positive results and improving accuracy in clinical assessments. Its integration into clinical practices is supported by its compatibility with various companion diagnostic claims, making it an essential tool for aligning treatment decisions with approved therapeutic products. By utilizing next-generation sequencing technologies, the xT CDx supports the optimization of treatment pathways and enhances patient care through detailed molecular insights. With the capacity to perform detailed analyses on formalin-fixed paraffin-embedded tumor tissues and matched normal samples, this assay promises high specificity and sensitivity in tumor profiling. Leveraging Tempus' cutting-edge bioinformatics infrastructure, the xT CDx ensures healthcare providers can make informed decisions supported by rich genetic data, setting a transformative benchmark in precision oncology.
APB4 GPIO is tailored to offer a multitude of general-purpose input/output channels that are bidirectional. Its user-defined configuration capability ensures that designers can specify the number of I/O resources needed for their particular application, making it an essential component in flexible and adaptable hardware architectures.
The HOTLink II Product Suite from Great River Technology is tailored for high-speed data transmission in demanding aerospace environments. This solution integrates seamlessly into avionics systems, providing robust performance for data-intensive applications. Known for its efficiency and reliability, the HOTLink II suite is ideal for organizations requiring consistent and high-speed data transfer capabilities. Designed for maximum compatibility, the HOTLink II suite supports various hardware configurations and software interfaces, ensuring smooth transitions between system components. The suite offers a comprehensive array of tools that facilitate the integration and management of high-speed data links within sophisticated avionics architectures. Whether in development or deployment, the HOTLink II suite provides unparalleled support and flexibility. In addition to its core functionalities, the HOTLink II suite assists in optimizing data integrity and system robustness throughout the system's lifecycle. Its design reflects Great River Technology's expertise in data solutions, promising long-term reliability and performance in mission-critical applications.
The RISC-V Hardware-Assisted Verification by Bluespec is designed to expedite the verification process for RISC-V cores. This platform supports both ISA and system-level testing, adding robust features such as verifying standard and custom ISA extensions along with accelerators. Moreover, it offers scalable access through the AWS cloud, making verification available anytime and anywhere. This tool aligns with the needs of modern developers, ensuring thorough testing within a flexible and accessible framework.
The DB9000-AXI Multi-Channel DMA Controller is built to optimize data transfer efficiency within systems, capable of managing multiple data streams concurrently. Supporting up to 16 independent data channels, this DMA controller excels at enhancing throughput across diverse applications, from large data sets to intricate peripheral connections. Engineered to integrate seamlessly with AXI-based systems, it provides vital Scatter-Gather functionality to manage complex data paths and tasks, ensuring minimal overhead on CPUs. Its comprehensive control features allow users to customize data handling operations, catering to varying design needs that involve either high-speed or high-volume data transactions. This controller's architecture supports a breadth of configurations to optimize memory bandwidth usage, making it a critical asset in systems requiring rapid, reliable data exchange. By supporting both AXI3 and AXI4 protocols, it brings flexibility and adaptability to system designers who need fine-tuned integration for their specific application requirements. Offering comprehensive documentation, simulation kits, and technical support, this DMA controller aids in advancing designs in RISC-V, ARM, and other ASIC/FPGA platforms, making it invaluable to industries involved in high-performance computing, telecommunications, and beyond.
The GH310 is specialized GPU IP tailored for 2D sprite graphics with an emphasis on high pixel processing capabilities. It achieves minimal gate count, ensuring it occupies less silicon area while delivering robust graphic outputs. Designed to handle large volumes of sprite graphics efficiently, the GH310 is perfect for applications requiring rapid rendering and minimal hardware overhead. This makes it favorable for systems where space and power savings are crucial yet high-quality graphics are needed. Its architecture allows for optimized performance tailored for specific graphical needs, translating into a resource-efficient solution for developers seeking to integrate intricate graphical features in their products without excessive resource consumption.
GSHARK is a high-performance GPU IP designed to accelerate graphics on embedded devices. Known for its extreme power efficiency and seamless integration, this GPU IP significantly reduces CPU load, making it ideal for use in devices like digital cameras and automotive systems. Its remarkable track record of over one hundred million shipments underscores its reliability and performance. Engineered with TAKUMI's proprietary architecture, GSHARK integrates advanced rendering capabilities. This architecture supports real-time, on-the-fly graphics processing similar to that found in PCs, smartphones, and gaming consoles, ensuring a rich user experience and efficient graphics applications. This IP excels in environments where power consumption and performance balance are crucial. GSHARK is at the forefront of embedded graphics solutions, providing significant improvements in processing speed while maintaining low energy usage. Its architecture easily handles demanding graphics rendering tasks, adding considerable value to any embedded system it is integrated into.
The Orion MFH IP Cores are designed for optimal performance in 4G mobile fronthaul networks, compliant with the ITU-T specifications for CPRI signal multiplexing. They adeptly handle various CPRI options, ranging from 2.4576 Gbps to 12.16512 Gbps, ensuring high compatibility and performance. Featuring both muxponder and transponder configurations, Orion cores facilitate the efficient mapping and transport of CPRI signals via Optical Transport Network infrastructures, ideal for modern telecommunications frameworks. Their advanced capabilities enable telecommunications providers to enhance their network reliability and service delivery, adapting seamlessly to different fronthaul scenarios.
The Titanium Ti375 FPGA from Efinix boasts a high-density, low-power configuration, ideal for numerous advanced computing applications. Built on the well-regarded Quantum compute fabric, this FPGA integrates a robust set of features including a hardened RISC-V block, SerDes transceiver, and LPDDR4 DRAM controller, enhancing its versatility in challenging environments. The Ti375 model is designed with an intuitive I/O interface, allowing seamless communication and data handling. Its innovative architecture ensures minimal power consumption without compromising on processing speed, making it highly suitable for portable and edge devices. The inclusion of MIPI D-PHY further expands its applications in image processing and high-speed data transmission tasks. This FPGA is aligned with current market demands, emphasizing efficiency and scalability. Its architecture allows for diverse design challenges, supporting applications that transcend traditional boundaries. Efinix’s commitment to delivering sophisticated yet energy-efficient solutions is embodied in the Titanium Ti375, enabling new possibilities in the realm of computing.
The DisplayPort Transmitter from Trilinear Technologies is designed to deliver high-performance video and audio transmission for an array of display applications. It adheres to the latest standards to guarantee seamless integration with contemporary devices. Optimized for efficiency, it provides not only superior video quality but also minimizes latency to ensure a smooth user experience. Engineered with flexibility in mind, the DisplayPort Transmitter supports various resolutions and refresh rates, making it suitable for a wide range of multimedia interfaces. It is developed to handle complex signal processing while remaining energy-efficient, a critical feature for applications requiring prolonged usage without substantial power consumption. This transmitter's robust architecture ensures compatibility and reliability, standing as a testament to Trilinear's commitment to quality. It undergoes rigorous testing to meet industry standards, ensuring that each product can withstand varying operational conditions without compromising on performance or reliability, which is indispensable in today's dynamic tech environment.
The GV380 is a compact and powerful GPU IP designed to handle complex vector graphics with ease. This OpenVG 1.1 compliant GPU leverages a fourth generation architecture that minimizes CPU load while maximizing pixel performance in vector processing. The IP is ideal for embedded systems needing enhanced 2D graphics performance. It can seamlessly integrate with digital cameras and similar devices to render high-quality graphics without burdening the central processing unit. This efficiency is crucial in environments where processing capacity and battery life are valued. By offering substantial gains in pixel processing through innovative architectural improvements, the GV380 enables richer graphics and smoother interactions in embedded applications, supporting enhanced user experiences.
The Matchstiqâ„¢ X40 by Epiq Solutions is a compact, high-performance software-defined radio (SDR) system designed to harness the power of AI and machine learning at the RF edge. Its small form factor makes it suitable for payloads with size, weight, and power constraints. The unit offers RF coverage up to 18GHz with an instantaneous bandwidth up to 450MHz, making it an excellent choice for demanding environments requiring advanced signal processing and direction finding. One of the standout features of the Matchstiqâ„¢ X40 is its integration of Nvidia's Orin NX for CPU/GPU operations and an AMD Zynq Ultrascale+ FPGA, allowing for sophisticated data processing capabilities directly at the point of RF capture. This combination offers enhanced performance for real-time signal analysis and machine learning implementations, making it suited for a variety of high-tech applications. The device supports a variety of input/output configurations, including 1 GbE, USB 3.0, and GPSDO, ensuring compatibility with numerous host systems. It offers dual configurations that support up to four receivers and two transmitters, along with options for phase-coherent multi-channel operations, thereby broadening its usability across different mission-critical tasks.
Silicon Library's MIPI IP is crafted to meet the stringent requirements of modern mobile and multimedia applications. It includes D-PHY transmitter and receiver components, which are essential for high-speed data communication between components like cameras, displays, and processors within portable devices. The MIPI D-PHY IP is compliant with the latest MIPI standards, ensuring smooth data flow and reducing electromagnetic interference, critical for maintaining data integrity. Its applications span a range of sectors, from mobile phones to tablets and automotive systems, where high-performance data transmission is essential. This IP's design emphasizes low power consumption and efficient data handling, making it ideal for use in energy-sensitive devices. Furthermore, it supports a variety of video resolutions and data rates, providing flexibility in designing multimedia devices.
The RWM6050 baseband modem by Blu Wireless represents a highly efficient advancement in mmWave technology, offering an economical and energy-saving option for high bandwidth and capacity applications. Developed alongside Renesas, the modem is configured to work with mmWave RF chipsets to deliver scalable multi-gigabit throughput across access and backhaul networks. This modem is ideal for applications requiring substantial data transfer across several hundred meters.\n\nThe RWM6050 leverages flexible channelization and advanced modulation support to enhance data rates with dual modems and integrated mixed-signal front-end processing. This ensures that the modem can effectively handle diverse use cases with varying bandwidth demands. Its versatile subsystems, including PHY, MAC, ADC/DAC, and beamforming, facilitate adaptive solutions for complex networking environments.\n\nA standout feature of the RWM6050 is its integrated network synchronization, ensuring high precision in data delivery. Designed to meet the futuristic needs of communication networks, it helps end-users achieve superior performance through its programmable real-time scheduler and digital front-end processing. Additionally, the modem's highly digital design supports robust, secure connections needed for next-generation connectivity solutions.
Ventana's System IP product suite is crucial for integrating the Veyron CPUs into a cohesive RISC-V based high-performance system. This integration set ensures the smooth operation and optimization of Ventana's processors, enhancing their applicability across various computational tasks. Particularly relevant for data centers and enterprise settings, this suite includes essential components such as IOMMU and CPX interfaces to streamline multiple workloads management efficiently. These systems IP products are built with a focus on optimized communication and processing efficiency, making them integral in achieving superior data throughput and system reliability. The design encompasses the necessities for robust virtualization and resource allocation, making it ideally suited for high-demand data environments requiring meticulous coordination between system components. By leveraging Ventana's System IP, users can ensure that their processors meet and exceed the performance needs typical in today's cloud-intensive and server-heavy operations. This capability makes the System IP a foundational element in creating a performance-optimized technology stack capable of sustaining diverse, modern technological demands.