All IPs > Graphic & Peripheral
Graphic & Peripheral Semiconductor IPs are critical components in the design and development of electronics that require efficient and robust control over multimedia and peripheral functions. This category of semiconductor IP encompasses a wide array of technologies used to manage and optimize graphics rendering, audio processing, data communication, and peripheral interfaces in electronic devices such as computers, smartphones, tablets, and other smart gadgets.
In this vivid category, you'll find a variety of subcategories tailored to specific functionalities. For instance, the Graphics Processing Unit (GPU) semiconductor IPs are pivotal for rendering images and video, essential in gaming, virtual reality, and professional content creation. Audio Controllers handle sound processing, ensuring crisp and seamless audio output, crucial for devices prioritizing high-quality sound delivery.
Other key components in the Graphic & Peripheral category include Peripheral Controllers, which facilitate the integration of various input/output devices, enhancing the device's interactivity and user experience. DMA Controllers are responsible for moving data efficiently between memory and peripherals, minimizing the CPU load. These IPs enhance overall system performance by ensuring that data flow is smooth and uninterrupted.
From Clock Generators that synchronize the entire system's operations to Interrupt Controllers managing priority tasks, each semiconductor IP in this category plays a unique role in ensuring that electronic devices operate at peak efficiency. By exploring these subcategories, companies and developers can find the precise semiconductors needed to support cutting-edge multimedia and peripheral technologies in their next product launch.
Overview: The UCIe IP supports multiple protocols (CXL/PCIe/Streaming) to connect chiplets, reducing overall development cycles for IPs and SOCs. With flexible application and PHY interfaces, The UCIe IP is ideal for SOCs and chiplets. Key Features:  Supports UCIe 1.0 Specification  Supports CXL 2.0 and CXL 3.0 Specifications  Supports PCIe Gen6 Specification  Supports PCIe Gen5 and older versions of PCIe specifications  Supports single and two-stack modules  Supports CXL 2.0 68Byte flit mode with Fallback mode for PCIe non-flit mode transfers  Supports CXL 3.0 256Byte flit mode  Supports PCIe Gen6 flit mode  Configurable up to 64-lane configuration for Advanced UCIe modules and 16 lanes for Standard UCIe modules  Supports sideband and Mainband signals  Supports Lane repair handling  Data to clock point training and eye width sweep support from transmitter and receiver ends  UCIe controller can work as Downstream or Upstream  Main Band Lane reversal supported  Dynamic sense of normal and redundant clock and data lines activation  UCIe enumeration through DVSEC  Error logging and reporting supported  Error injection supported through Register programming  RDI/FDI PM entry, Exit, Abort flows supported  Dynamic clock gang at adapter supported Configurable Options:  Maximum link width (x1, x2, x4, x8, x16)  MPS (128B to 4KB)  MRRS (128B to 4KB)  Transmit retry/Receive buffer size  Number of Virtual Channels  L1 PM substate support  Optional Capability Features can be Configured  Number of PF/VFDMA configurable Options  AXI MAX payload size Variations  Multiple CPI Interfaces (Configurable)  Cache/memory configurable  Type 0/1/2 device configurable
Our Expanded Serial Peripheral Interface (JESD251) Master controller features a low signal count and high data bandwidth, making it ideal for use in computing, automotive, Internet of Things, embedded systems, and mobile system processors. It connects multiple sources of Serial Peripheral Interface (xSPI) slave devices, including nonvolatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports a single master and multiple slaves per interface port. • Supports Single Data Rate and Double Data Rate. • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for writemasking. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands to read or writedata for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
Overview: The Expanded Serial Peripheral Interface (xSPI) Master/Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy SPI devices. It is designed to connect xSPI Master/Slave devices in computing, automotive, Internet of Things, embedded systems, and mobile processors to various peripherals such as non-volatile memories, graphics peripherals, networking devices, FPGAs, and sensor devices. Key Features:  Compliance with JEDEC standard JESD251 eXpanded SPI for Non-Volatile Memory Devices, Version 1.0  Support for Single master and multiple slaves per interface port  Single Data Rate (SDR) and Double Data Rate (DDR) support  Source synchronous clocking  Deep Power Down (DPD) enter and exit commands  Eight IO ports in standard, expandable based on system requirements  Optional Data Strobe (DS) for write masking  bit wide SDR transfer support  Profile 1.0 Commands for non-volatile memory device management  Profile 2.0 Commands for read or write data for various slave devices Applications:  Consumer Electronics  Defense & Aerospace  Virtual Reality  Augmented Reality  Medical  Biometrics  Automotive Devices  Sensor Devices
The KL730 AI SoC is powered by Kneron's innovative third-generation reconfigurable NPU architecture, delivering up to 8 TOPS of computing power. This architecture offers enhanced efficiency for the latest CNNnetwork architectures and serves transformer applications by reducing DDR bandwidth requirements significantly. The chip excels in video processing, supporting 4K 60FPS output and excelling in areas such as noise reduction and low-light imaging. It's ideal for applications in intelligent security, autonomous driving, and video conferencing, among others.
The ADQ35 offers a dual-channel, 12-bit configuration with a sampling rate of up to 10 GSPS. This digitizer is designed for high-performance applications, featuring up to 2.5 GHz input bandwidth and a programmable DC-offset. With 8 Gbyte onboard memory and an open FPGA, it allows custom real-time digital signal processing. It supports peer-to-peer streaming at rates up to 14 Gbyte/s, making it ideal for scientific and industrial applications.
Overview: The Multi-Protocol Accelerator IP is a versatile technology designed to support low latency and high bandwidth accelerators for efficient CPU-to-device and CPU-to-memory communication. It also enables switching for fan-out to connect more devices, memory pooling for increased memory utilization efficiency, and provides memory capacity with support for hot-plug, security enhancements, persistent memory support, and memory error reporting. Key Features:  CXL 3.0 Support: Compliant with CXL spec V3.X/V2.X  PCIe Compatibility: Supports PCIe spec 6.0/5.0  CPI Interface: Support for CPI Interface  AXI Interface: Configurable AXI master, AXI slave  Bus Support: PIPE/FLEX bus, Lane x1,x2,x4,x8,x16  Protocol Support: Gen3, Gen4, Gen5 & Gen6, Fallback Mode  Register Checks: Configuration and Memory Mapped registers  Dual Mode: Supports Dual Mode operation  Transfer Support: HBR/PBR & LOpt Transfers, Standard Cache and Mem Transfers  CXL Support: Can function as both CXL host and device  Data Transfer: Supports Standard IO, 68Byte Flit, and 256Byte Flit Transfers  FlexBus Features: FlexBus Link Features, ARB/MUX, ARB/MUX Bypass  Optimization: Latency Optimization, Credit Return Forcing, Empty Flits (Latency Optimized)  Power Management: Supports Power Management features  Enhancements: CXL IDE, RAS Features, Poison & Viral Handling, MLD/SLD  Testing: Compliance Testing and Error Scenarios support
Overview: PCIe Gen6 is a high-speed, layered protocol interconnect interface supporting speeds up to 64GT/s, featuring multi-lanes and links. The Transport, Data Link, and Physical layers specified in the PCIe specification are implemented, along with PIPE interface logic connecting to PHY and AXI Bridging logic for application connectivity. Specifications:  Supports PCIe Gen 6 and Pipe 5.X Specifications  Core supports Flit and non-Flit Mode  Lane Configurations: X16, X8, X4, X2, X1  AXI MM and Streaming supported  Supports Gen1 to Gen6 modes  Data rate support of 2.5 GT/s, 5 GT/s, 8 GT/s, 16 GT/s, 32 GT/s, 64 GT/s  PAM support when operating at 64GT/s  Encoding/Decoding Support: 8b/10b, 128b/130b, 1b/1b  Supports SerDes and non-SerDes architecture  Optional DMA support as plugin module  Support for alternate negotiation protocol  Can operate as an endpoint or root complex  Lane polarity control through register  Lane de-skew supported  Support for L1 states and L0P  Support for SKP OS add/removal and SRIS mode  No equalization support through configuration  Deemphasis negotiation support at 5GT/s  Supports EI inferences in all modes  Supports PTM, OBFF, MSI, MSIX, Power management, and all message formats
Our Expanded Serial Peripheral Interface (JESD251) Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface (SPI) devices. It is used to connect xSPI Master devices in computing, automotive, Internet of Things, embedded systems, and mobile system processors to non-volatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports Single Data Rate (SDR) and Double Data Rate (DDR). • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for timing reference. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands for reading or writing data for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
Silicon Creations' Free Running Oscillators provide dependable timing solutions for a range of applications such as watchdog timers and core clock generators in low-power systems. These oscillators, crafted with compactness and efficiency in mind, support a gamut of processes from 65nm to the latest 3nm technologies. These oscillators excel in low power consumption, often requiring less than 30µW during operation. Their robust design ensures they deliver high precision over a temperature range from -40°C to 125°C with supply voltage variabilities factored in. The simplicity in design negates the need for external components, promoting easier integration and reduced overall system complexity. Precise tuning capabilities allow for accuracy levels up to ±1.5% after process trimming, ensuring outstanding performance in volatile environmental conditions. This level of reliability makes them ideal for integration into various consumer electronics, automotive controls, and other precision-demanding applications where space and power constraints are critical.
Silicon Creations delivers precision LC-PLLs designed for ultra-low jitter applications requiring high-end performance. These LC-tank PLLs are equipped with advanced digital architectures supporting wide frequency tuning capabilities, primarily suited for converter and PHY applications. They ensure exceptional jitter performance, maintaining values well below 300fs RMS. The LC-PLLs from Silicon Creations are characterized by their capacity to handle fractional-N operations, with active noise cancellation features allowing for clean signal synthesis free of unwanted spurs. This architecture leads to significant power efficiencies, with some IPs consuming less than 10mW. Their low footprint and high frequency integrative capabilities enable seamless deployments across various chip designs, creating a perfect balance between performance and size. Particular strength lies in these PLLs' ability to meet stringent PCIe6 reference clocking requirements. With programmable loop bandwidth and an impressive tuning range, they offer designers a powerful toolset for achieving precise signal control within cramped system on chip environments. These products highlight Silicon Creations’ commitment to providing industry-leading performance and reliability in semiconductor design.
The Origin E1 is an optimized neural processing unit (NPU) targeting always-on applications in devices like home appliances, smartphones, and security cameras. It provides a compact, energy-efficient solution with performance tailored to 1 TOPS, making it ideal for systems needing low-power and minimal area. The architecture is built on Expedera's unique packet-based approach, which enables enhanced resource utilization and deterministic performance, significantly boosting efficiency while avoiding the pitfalls of traditional layer-based architectures. The architecture is fine-tuned to support standard and custom neural networks without requiring external memory, preserving privacy and ensuring fast processing. Its ability to process data in parallel across multiple layers results in predictive performance with low power and latency. Always-sensing cameras leveraging the Origin E1 can continuously analyze visual data, facilitating smoother and more intuitive user interactions. Successful field deployment in over 10 million devices highlights the Origin E1's reliability and effectiveness. Its flexible design allows for adjustments to meet the specific PPA requirements of diverse applications. Offered as Soft IP (RTL) or GDS, this engine is a blend of efficiency and capability, capitalizing on the full scope of Expedera's software tools and custom support features.
The eSi-Connect is a suite of AMBA peripheral IP cores designed to enhance connectivity and integration in Systems on Chip (SoCs). Directed towards simplifying the development process, eSi-Connect supports standard interfaces like AXI, AHB, and APB, making it a comprehensive toolset for various system integrations. This suite includes multiple memory controllers, off-chip interfaces, and utility functions such as timer and watchdogs, enabling developers to customize and scale solutions efficiently. The peripherals within the eSi-Connect ensure compatibility with a broad range of embedded systems while maintaining high performance and power efficiency. With an array of functionalities like GPIO, Ethernet MAC, and various serial interfaces, it provides low-level software drivers optimizing for real-time SoC deployment. Leveraging eSi-Connect, design teams can accelerate time-to-market with builds tailored to specific application needs, ensuring robustness and scalability.
Silicon Creations' Analog Glue solutions provide essential analog functionalities to complete custom SoC designs seamlessly. These functional blocks, which constitute buffer and bandgap reference circuits, are vital for seamless on-chip clock distribution and ensure low-jitter operations. Analog Glue includes crucial components such as power-on reset (POR) generators and bridging circuits to support various protocols and interfaces within SoCs. These supplementary macros are crafted to complement existing PLLs and facilities like SerDes, securing reliable signal transmission under varied operating circumstances. Serving as the unsung heroes of chip integration, these Analog Glue functions mitigate the inevitable risks of complex SoC designs, supporting efficient design flows and effective population of chip real estate. Thus, by emphasizing critical system coherency, they enhance overall component functionality, providing a stable infrastructure upon which additional system insights can be leveraged.
Silicon Creations crafts highly reliable LVDS interfaces designed to meet diverse application needs, going from bi-directional I/Os to specialized uni-directional configurations. Spanning process compatibilities from 90nm CMOS to advanced 7nm FinFET, these interfaces are a cornerstone for high-speed data communication systems, thriving particularly in video data transmission and chip-to-chip communications. Supporting robust data rates over multiple channels, the LVDS Interfaces guarantee flexible programmability and protocol compatibility with standards such as FPD-Link and Camera-Link. They capitalize on proven PLL and CDR architectures for superior signal integrity and error-free data transfers. Operating efficiently in various technology nodes, they remain highly effective across collaborative chipset environments. The interfaces are fortified with adaptable features like dynamic phase alignment to stabilize data sequences and on-die termination options for superior signal integrity. Their proven record places them as a critical enabler in applications where consistent high-speed data transfer is paramount, demonstrating Silicon Creations’ prowess in delivering industry-leading communication solutions.
This IP offers a high-performance mixed-signal CODEC solution perfect for advanced audio applications. It seamlessly integrates analog-to-digital and digital-to-analog conversion capabilities, ensuring an immersive audio experience with minimal latency and superior sound fidelity. The CODEC is specifically designed to handle multiple audio interface formats, providing adaptability across various platforms and devices. One of the strengths of this CODEC is its optimized power consumption. It is crafted to deliver top-tier performance while maintaining efficient energy use, which is essential for battery-powered and portable devices. The versatility of the CODEC makes it an ideal choice for a wide range of applications, from automotive audio systems to consumer electronics. Additionally, this solution is engineered with robust support for different process nodes, enhancing its compatibility with a multitude of manufacturing technologies. This makes it not only efficient but also versatile, allowing for straightforward integration into diverse product lines.
Altek's AI Camera Module stands as a testament to the company's prowess in integrating artificial intelligence with advanced imaging technology. This module is designed for a spectrum of applications that demand rapid and precise image processing, such as surveillance, automated inspection, and smart devices. By leveraging sophisticated AI algorithms, the module can perform real-time image analysis, enabling enhanced decision-making processes in demanding scenarios. The AI Camera Module is engineered to deliver high-resolution imagery, coupled with robust data processing capabilities that ensure seamless performance in dynamic environments. Its architecture supports a variety of AI-driven functions like facial recognition, object tracking, and behavioral pattern analysis, thereby elevating the module’s versatility across different sectors. Compatibility with IoT systems enhances its appeal, as the module facilitates sophisticated integration with broader networked environments. With a focus on reducing latency and boosting computational efficiency, Altek's AI Camera Module is poised to be a vital component in the future of smart cities and connected solutions.
The KL520 AI SoC is a groundbreaking chip that initiated Kneron's journey in edge AI. It is characterized by its compact size, energy efficiency, and robust performance, suitable for a host or companion AI co-processor role. Compatible with multiple 3D sensor technologies, the KL520 excels in smart home applications like smart locks and cameras. Its small power footprint allows operations on simple power supplies like AA batteries, setting it apart in the market.
The AHB-Lite Timer from Roa Logic is designed to conform to the RISC-V Privileged Specification, offering a precise timing module crucial for various interrupt and timing-related functions within digital systems. It is constructed to provide reliable time-based operations, ensuring accurate synchronization of activities within embedded environments. This timer is fully compliant with modern RISC-V standards, simplifying its integration into systems built around these architectures. Fully parameterized, it supports custom configurations, enabling designers to optimize its functionality to suit the precise needs of their applications. Available for non-commercial use, this timer module empowers developers to integrate precision timing capabilities into their designs, promoting advanced functionality and system performance where strict timing is crucial. Its accessibility aligns with Roa Logic's commitment to innovation and flexibility in digital design solutions.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
The Ring PLLs offered by Silicon Creations illustrate a versatile clocking solution, well-suited for numerous frequency generation tasks within integrated circuit designs. Known for their general-purpose and specialized applications, these PLLs are crafted to serve a massive array of industries. Their high configurability makes them applicable for diverse synthesis needs, acting as the backbone for multiple clocking strategies across different environments. Silicon Creations' Ring PLLs epitomize high integration with functions tailored for low jitter and precision clock generation, suitable for battery-operated devices and systems demanding high accuracy. Applications span from general clocking to precise Audio Codecs and SerDes configurations requiring dedicated performance metrics. The Ring PLL architecture achieves best-in-class long-term and period jitter performance with both integer and fractional modes available. Designed to support high volumes of frequencies with minimal footprint, these PLLs aid in efficient space allocation within system designs. Their use of silicon-proven architectures and modern validation methodologies assure customers of high reliability and quick integration into existing SoC designs, emphasizing low risk and high reward configurations.
The Aries fgOTN processor family is engineered according to the ITU-T G.709.20 fgOTN standard. This line of processors handles a variety of signals, including E1/T1, FE/GE, and STM1/STM4, effectively monitoring and managing alarms and performance metrics. Aries processors excel at fine-grain traffic aggregation, efficiently channeling fgODUflex traffic across OTN lines to support Ethernet, SDH, PDH client services. Their capacity to map signals to fgODUflex containers, which are then multiplexed into higher order OTN signals, demonstrates their versatility and efficiency. By allowing cascaded configurations with other Aries devices or Apodis processors, Aries products optimize traffic routes through OTN infrastructures, positioning them as essential components in optical networking and next-generation access scenarios.
The Ethernet Real-Time Publish-Subscribe (RTPS) Core is designed to deliver complete hardware solutions for the Ethernet RTPS protocol. It stands out by providing reliable networking capabilities needed in environments that demand stringent real-time data exchanges. This core enhances data communication efficiencies by facilitating rapid publish-subscribe interactions within complex network ecosystems. Optimized for environments that require high data throughput and consistency, it ensures that data exchanges are executed with precision and timeliness. Its architectural elegance supports seamless integration into existing networks, promoting a resilient exchange of information crucial for operational continuity. This core is pivotal for ensuring robust communication frameworks in mission-critical systems where delays and data losses are unacceptable.
The PDM-to-PCM Converter offers an innovative solution for converting pulse-density modulation signals into pulse-code modulation formats, supporting the growing demand in modern audio processing systems. This converter is indispensable for applications where maintaining audio integrity is paramount, such as digital microphones and audio streaming devices. Engineered for efficiency, the converter handles high-definition audio with minimal distortion, ensuring the audio signal remains true to the source. The design incorporates various filters that minimize unwanted artifacts, a crucial feature for any high-end audio system requiring pristine sound quality. This converter supports a wide array of audio interfaces, facilitating its integration into diverse audio frameworks—from IoT devices to advanced multi-channel audio systems. Moreover, its low-power design makes it ideal for use in portable devices, enabling manufacturers to develop products that meet both performance and power consumption metrics.
The H.264 FPGA Encoder and CODEC Micro Footprint Cores from A2e Technologies are industry-leading solutions optimized for high-speed video encoding with minimal latency. Specially tailored for FPGA applications, this core ensures compliance with the H.264 Baseline and offers configurations to suit varying performance needs, such as low-cost evaluation licenses for flexibility. These cores are noted for their exceptionally compact size and rapid processing capabilities, enabling them to achieve 1080p at 60 frames per second with remarkable efficiency. One of the project's standout features is the 1ms latency at 1080p30, which is among the fastest in the industry. This core also supports custom configurations, allowing adjustments to pixel depth, resolution, and more, making it a versatile choice for developers looking to integrate video encoding in their systems. Moreover, these cores are ITAR compliant, offering a secure and adaptable solution for high-performance FPGA design. The scalability and customization options, including support for various pixel depths and resolutions, make these H.264 cores suitable for a wide array of applications, from real-time video streaming to embedded systems in industrial automation. By leveraging this advanced technology, A2e Technologies provides a robust solution that meets stringent industry standards and addresses specific customer needs effectively.
The GV380 is a compact and powerful GPU IP designed to handle complex vector graphics with ease. This OpenVG 1.1 compliant GPU leverages a fourth generation architecture that minimizes CPU load while maximizing pixel performance in vector processing. The IP is ideal for embedded systems needing enhanced 2D graphics performance. It can seamlessly integrate with digital cameras and similar devices to render high-quality graphics without burdening the central processing unit. This efficiency is crucial in environments where processing capacity and battery life are valued. By offering substantial gains in pixel processing through innovative architectural improvements, the GV380 enables richer graphics and smoother interactions in embedded applications, supporting enhanced user experiences.
The Origin E8 NPU by Expedera is engineered for the most demanding AI deployments such as automotive systems and data centers. Capable of delivering up to 128 TOPS per core and scalable to PetaOps with multiple cores, the E8 stands out for its high performance and efficient processing. Expedera's packet-based architecture allows for parallel execution across varying layers, optimizing resource utilization, and minimizing latency, even under strenuous conditions. The E8 handles complex AI models, including large language models (LLMs) and standard machine learning frameworks, without requiring significant hardware-specific changes. Its support extends to 8K resolutions and beyond, ensuring coverage for advanced visualization and high-resolution tasks. With its low deterministic latency and minimized DRAM bandwidth needs, the Origin E8 is especially suitable for high-performance, real-time applications. The high-speed processing and flexible deployment benefits make the Origin E8 a compelling choice for companies seeking robust and scalable AI infrastructure. Through customized architecture, it efficiently addresses the power, performance, and area considerations vital for next-generation AI technologies.
Silicon Library's DisplayPort/eDP is engineered to enhance visual display performance, supporting seamless data transfer for high-definition content. This module adheres to DisplayPort standards, promising superb visual quality across a range of display devices. Designed for versatility, the DisplayPort/eDP is suitable for integration into a myriad of devices, from laptops to computer monitors. It supports high-resolution display outputs, ensuring crisp and vivid visuals, crucial for gaming and graphic design applications. This product is equipped to handle high data rates, facilitating smooth media playback without any lag, making it suitable for high-performance multimedia applications. Integrated with advanced features, it also ensures compatibility with various system architectures, providing a reliable solution for modern digital requirements.
The GH310 is specialized GPU IP tailored for 2D sprite graphics with an emphasis on high pixel processing capabilities. It achieves minimal gate count, ensuring it occupies less silicon area while delivering robust graphic outputs. Designed to handle large volumes of sprite graphics efficiently, the GH310 is perfect for applications requiring rapid rendering and minimal hardware overhead. This makes it favorable for systems where space and power savings are crucial yet high-quality graphics are needed. Its architecture allows for optimized performance tailored for specific graphical needs, translating into a resource-efficient solution for developers seeking to integrate intricate graphical features in their products without excessive resource consumption.
The HOTLink II Product Suite is a powerful video transmission solution that enables secure and rapid data exchange for avionics applications. This suite by Great River Technology is designed to facilitate seamless high-speed digital communications, minimizing latency while enhancing the system's reliability in demanding environments. The suite encompasses a range of tools that streamline the development and deployment of HOTLink II systems, which are crucial for managing high-bandwidth data flows. It offers extensive support mechanisms through well-crafted documentation and robust simulation tools, aiding engineers in achieving optimized system performance and regulatory compliance. By leveraging the HOTLink II Product Suite, users can achieve improved data integrity and support for multiple video interfaces, ensuring the readiness of systems for various missions. This makes the suite a vital component for both military and civilian aerospace projects, offering extensive scalability and customization to suit specific operational needs.
The pPLL03F-GF22FDX is a state-of-the-art, all-digital Fractional-N PLL crafted specifically for performance computing environments, offering low jitter and compact design. This advanced PLL is optimized for clocking applications that demand precise timing, functioning at frequencies of up to 4GHz. Its architecture makes it an excellent choice for driving performance computers and ADC/DAC systems where moderate SNR is essential. Constructed utilizing Perceptia's robust second-gen all-digital PLL technology, it delivers consistent results across a broad spectrum of process variations and conditions. Noteworthy for its tiny area, the pPLL03F enables system designers to efficiently manage complex multi-domain clock systems utilizing shared power supplies. Each instance includes a built-in power regulator, facilitating seamless sharing of power across various blocks relying on its clock outputs. Featuring dual PLL outputs through distinct postscalers, it's designed for easy integration into SOC systems while being highly testable, supporting industry-standard flows. It is usable in both integer-N and fractional-N modes, offering substantial flexibility in synchronizing input-output clock frequencies at the system level. The design encompasses compactness and effectiveness, ensuring low consumption while maintaining superior performance.
The KL630 AI SoC introduces state-of-the-art NPU architecture, being the first to support both Int4 precision and transformer neural networks. It offers notable energy efficiency and is built on the ARM Cortex A5 CPU, providing up to 1eTOPS@int4. The KL630 supports various AI frameworks, making it suitable for a wide array of edge AI devices and applications that require advanced ISP capabilities and 5M@30FPS HDR imaging.
The Apodis family of Optical Transport Network processors adheres to ITU-T standards, offering a comprehensive suite for signal termination, processing, and multiplexing. Designed to handle both SONET/SDH and Ethernet client services, these processors map signals to Optical Transport Network (OTN), empowering versatile any-port, any-service configurations. Apodis processors are notable for their capacity to support up to 16 client ports and four 10G OTN line ports, delivering bandwidth scalability up to 40G, crucial for wireless backhaul and fronthaul deployments. With a robust, non-blocking OTN switching fabric, Apodis facilitates seamless client-to-line and line-to-line connections while optimally managing network bandwidth. This adaptability makes the Apodis processors an ideal choice for next-generation access networks and optical infrastructures.
The Chimera GPNPU is a general-purpose neural processing unit designed to address key challenges faced by system on chip (SoC) developers when deploying machine learning (ML) inference solutions. It boasts a unified processor architecture capable of executing matrix, vector, and scalar operations within a single pipeline. This architecture integrates the functions of a neural processing unit (NPU), digital signal processor (DSP), and other processors, which significantly simplifies code development and hardware integration. The Chimera GPNPU can manage various ML networks, including classical frameworks, vision transformers, and large language models, all within a single processor framework. Its flexibility allows developers to optimize performance across different applications, from mobile devices to automotive systems. The GPNPU family is fully synthesizable, making it adaptable to a range of performance requirements and process technologies, ensuring long-term viability and adaptability to changing ML workloads. The Cortex's sophisticated design includes a hybrid Von Neumann and 2D SIMD matrix architecture, predictive power management, and sophisticated memory optimization techniques, including an L2 cache. These features help reduce power usage and enhance performance by enabling the processor to efficiently handle complex neural network computations and DSP algorithms. By merging the best qualities of NPUs and DSPs, the Chimera GPNPU establishes a new benchmark for performance in AI processing.
The DB9000AXI Display Controller from Digital Blocks is engineered for high-performance display applications, supporting various display resolutions from 320x240 QVGA up to 1920x1080 Full HD. It enhances image quality through features like overlay windows and hardware cursor support, which facilitate sophisticated composition processes such as alpha blending and color space conversion. Advanced versions scale up to meet the demands of 4K and 8K displays, making it suitable for a range of industries including medical and automotive sectors. The controller efficiently manages the flow of video data between frame buffer memory and the display through an AMBA AXI protocol interface.
The AXI4 DMA Controller by Digital Blocks is tailored for high data throughput in varied data set sizes across multiple channels, ranging from a single up to 16 in standard releases. It includes features such as independent read and write controllers for each channel and scatter-gather linked-list management for data transfers, ensuring efficient handling of memory and peripheral data. This controller supports customizable interfaces like AMBA AXI and offers numerous data width options, which aid in optimizing performance and minimizing hardware footprints. User configurable parameters and a robust test suite make this DMA controller adaptable and easy to integrate into diverse system architectures.
The Display Driver IC for large-sized displays by Novatek is designed to drive expansive screen solutions, ideal for applications in televisions, notebook computers, and desktop monitors. Leveraging its expertise in IC technology, Novatek delivers products that enable high-performance display results, reducing electromagnetic interference while maintaining low power consumption. Their advanced fabrication and process technologies allow for a broad array of integrated features, accommodating various large panel displays. This versatile IC was initially highlighted with the release of Taiwan's first 240-channel gate driver and 288/240 channel source driver for TFT LCDs back in 1999, marking a step forward in display technology. By focusing research and development efforts on these components, Novatek continues to deliver products that meet the increasing demands for quality and efficiency in large-scale displays. Novatek's large-sized display driver ICs are central to their strategy of providing best-in-class solutions for expanding digital display needs worldwide, exhibiting strong partnerships with major global display manufacturers. The comprehensive integration and advanced design features of these ICs suit varied large application displays, further diversifying the reach of their brand.
Hermes X3D excels in electromagnetic simulation of advanced electronic packages and passive interconnects, essential for high-speed digital designs. It uses a quasi-static algorithm to extract RLGC parameters and generate SPICE models, which are crucial for system analysis regarding signal and power integrity and electromagnetic compatibility. Hermes X3D facilitates parasitic parameter extraction, supporting low-frequency precision and swift processing speeds, making it ideal for designing touch screens and other electromagnetic applications that require accurate capacitance analysis.
The Vantablack S-VIS coating is specifically tailored for space applications, where it serves a crucial role in suppressing stray light in optical systems and blackbody calibration of infrared camera systems. Its exceptionally high performance and spectrally flat absorption from the UV to the near-millimeter spectral range make it indispensable for ensuring accurate readings and operations in the challenging environment of space. One of the prominent applications of the S-VIS coating is in the reduction of launch weight for instruments, thanks to its ability to absorb light efficiently from all angles. This not only enhances the operation of devices like star trackers and optical calibration systems but also minimizes the overall size and complexity of these systems, offering significant cost savings. This coating has proven its reliability in harsh space conditions since its first deployment in low Earth orbit in 2015. Its capabilities in outgassing management and thermal stability are well-documented, making it a trusted solution for enhancing the operational longevity and performance of space missions.
xcore.ai is a versatile platform specifically crafted for the intelligent IoT market. It hosts a unique architecture with multi-threading and multi-core capabilities, ensuring low latency and high deterministic performance in embedded AI applications. Each xcore.ai chip contains 16 logical cores organized in two multi-threaded processor 'tiles' equipped with 512kB of SRAM and a vector unit for enhanced computation, enabling both integer and floating-point operations. The design accommodates extensive communication infrastructure within and across xcore.ai systems, providing scalability for complex deployments. Integrated with embedded PHYs for MIPI, USB, and LPDDR, xcore.ai is capable of handling a diverse range of application-specific interfaces. Leveraging its flexibility in software-defined I/O, xcore.ai offers robust support for AI, DSP, and control processing tasks, making it an ideal choice for enhancing IoT device functionalities. With its support for FreeRTOS, C/C++ development environment, and capability for deterministic processing, xcore.ai guarantees precision in performance. This allows developers to partition xcore.ai threads optimally for handling I/O, control, DSP, and AI/ML tasks, aligning perfectly with the specific demands of various applications. Additionally, the platform's power optimization through scalable tile clock frequency adjustment ensures cost-effective and energy-efficient IoT solutions.
The ARINC 818 Streaming Core is designed to facilitate real-time conversion from pixel buses to ARINC 818 formatted Fibre Channel streams and vice versa. This core is optimized for aerospace applications where precise, high-speed streaming and data formatting are crucial. With this capability, it supports seamless integration into advanced aerospace systems like avionics displays. Capable of converting data efficiently, it alleviates the complexities associated with handling video streams in real-time, thereby ensuring that transmissions meet the high demands of military and aerospace objectives. By maintaining a strong focus on data integrity, the core helps achieve superior performance in data transmission, ensuring that critical systems maintain optimal operational readiness. The engineering behind this core provides an efficient bridge between different data formats, enabling robust communications across complex networks. The ARINC 818 Streaming Core reflects advanced design methodologies tailored for rigorous requirements, bringing about enhanced reliability and efficiency to the systems it serves.
SkyeChip's Configurable I/O technology offers a flexible interface capable of supporting signaling up to 3.2 GT/s. It adapts to multiple I/O standards including LVDS, HCSL, and SSTL, providing a broad range of voltage compatibility from 1.1V to 1.5V. This adaptability renders it ideal for diverse electronic systems requiring high-speed communication capabilities.
The DisplayPort Transmitter is a highly advanced solution designed to seamlessly transmit high-definition audio and video data between devices. It adheres to the latest VESA standards, ensuring it can handle DisplayPort 1.4 and 2.1 specifications with ease. The transmitter is engineered to support a plethora of audio interfaces including I2S, SPDIF, and DMA, making it highly adaptable to a wide range of consumer and professional audio-visual equipment. With features focused on AV sync and timing recovery, it ensures smooth and uninterrupted data flow even in the most demanding applications. This transmitter is particularly beneficial for those wishing to integrate top-of-the-line audio and video synchronization within their projects, offering customizable sound settings that can accommodate unique user requirements. It's robust enough to be used across industry sectors, from high-end consumer electronics like gaming consoles and home theater systems to professional equipment used in broadcast and video wall displays. Moreover, the DisplayPort Transmitter's architecture facilitates seamless integration into existing FPGA and ASIC systems without a hitch in performance. Comprehensive compliance testing ensures that it is compatible with a wide base of devices and technologies, making it a dependable choice for developers looking to provide comprehensive DisplayPort solutions. Whether it's enhancing consumer electronics or powering complex industry-specific systems, the DisplayPort Transmitter is built to deliver exemplary performance.
Roa Logic's Platform-Level Interrupt Controller (PLIC) is a highly parameterized and configurable module that adheres to the RISC-V architecture, intended to manage interrupts in various system designs comprehensively. This component is a critical part of incorporating interactivity and responsiveness in embedded systems, handling a multitude of interrupt sources efficiently. The PLIC's compliance with the RISC-V standard ensures seamless integration into systems using this architecture, enabling straightforward implementation and management of interrupt-related functionality. Its flexible design allows users to customize the number of supported interrupts according to specific needs, making it adaptable to a wide range of applications, from small embedded devices to more complex multicore systems. Overall, Roa Logic’s PLIC offers a scalable solution for systems designers, providing the necessary configurability to tailor the interrupt handling according to platform-specific requirements. Its open-access policy for non-commercial applications further encourages experimentation and innovation within the RISC-V ecosystems.
The Origin E2 from Expedera is engineered to perform AI inference with a balanced approach, excelling under power and area constraints. This IP is strategically designed for devices ranging from smartphones to edge nodes, providing up to 20 TOPS performance. It features a packet-based architecture that enables parallel execution across layers, improving resource utilization and performance consistency. The engine supports a wide variety of neural networks, including transformers and custom networks, ensuring compatibility with the latest AI advancements. Origin E2 caters to high-resolution video and audio processing up to 4K, and is renowned for its low latency and enhanced performance. Its efficient structure keeps power consumption down, helping devices run demanding AI tasks more effectively than with conventional NPUs. This architecture ensures a sustainable reduction in the dark silicon effect while maintaining high operating efficiencies and accuracy thanks to its TVM-based software support. Deployed successfully in numerous smart devices, the Origin E2 guarantees power efficiency sustained at 18 TOPS/W. Its ability to deliver exceptional quality across diverse applications makes it a preferred choice for manufacturers seeking robust, energy-conscious solutions.
Expedera's Origin E6 NPU is crafted to enhance AI processing capabilities in cutting-edge devices such as smartphones, AR/VR headsets, and automotive systems. It offers scalable performance from 16 to 32 TOPS, adaptable to various power and performance needs. The E6 leverages Expedera's packet-based architecture, known for its highly efficient execution of AI tasks, enabling parallel processing across multiple workloads. This results in better resource management and higher performance predictability. Focusing on both traditional and new AI networks, Origin E6 supports large language models as well as complex data processing tasks without requiring additional hardware optimizations. Its comprehensive software stack, based on TVM, simplifies the integration of trained models into practical applications, providing seamless support for mainstream frameworks and quantization options. Origin E6's deployment reflects meticulous engineering, optimizing memory usage and processing latency for optimal functionality. It is designed to tackle challenging AI applications in a variety of demanding environments, ensuring consistent high-performance outputs and maintaining superior energy efficiency for next-generation technologies.
SnpExpert is a specialized tool for analyzing S-parameters in high-speed and RF circuits, crucial for addressing issues such as reflections and crosstalk. Supporting a range of COM protocols, SnpExpert offers advanced analysis features like parameter extraction and margin calculations. It also facilitates the creation of broadband models using rational fitting, ensuring users can design optimized signal paths. Whether handling NRZ or PAM-4 modulations, SnpExpert provides engineers with the detailed insights needed for precise signal integrity analysis and system compliance.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
Dolphin Technology's I/O products encompass a vast selection of interface IPs known for their high-performance capabilities. These I/O components are designed to complement various process technologies, ensuring reliability and efficiency in applications ranging from core limited designs to flip-chip utilizations. The product range includes standard I/O, high-speed I/O, and specialty interface I/O that can be customized for specific design requirements. The portfolio comprises various specialized I/Os like High Voltage Tolerant GPIO, LVDS Tx/Rx, and several DDR and SD IO variations, each built to meet demanding design specifications. Dolphin Technology’s offerings are fully equipped with compilers that allow for customization, ensuring each I/O library can be tailored to address process and chip-specific needs, thereby delivering optimal performance and versatility. These I/O solutions are available in multiple forms, including inline styles and flip-chip arrangements, which assist in the efficient use of space and signal integrity in complex semiconductor designs. The capability to integrate with different technology levels further broadens the applicability of these products, making them suitable for a diverse set of industry requirements.
Clock generation solutions from Analog Circuit Works are engineered to pair seamlessly with other IP products, enhancing the functionality and performance of integrated systems. Their offerings focus on providing consistent, reliable clock signals that are essential for synchronizing complex digital circuits, thus playing a pivotal role in maintaining efficient system operation. These solutions cater to varying clock frequencies, tailored to fit a diverse set of process technologies. Analog Circuit Works capitalizes on their ability to design optimized clock circuits that cater to both high-frequency and optimized low-frequency operations, ensuring that they meet specific design requirements while facilitating smoother integration into diverse application environments. The clock generation IP serves as a backbone for ensuring operational timing precision within devices, providing foundational support that enhances the overall synchronization and performance of intricate electronic systems. This reliability and adaptability make these solutions vital in complex electronics where time-sensitive operations are critical.
GSHARK is a high-performance GPU IP designed to accelerate graphics on embedded devices. Known for its extreme power efficiency and seamless integration, this GPU IP significantly reduces CPU load, making it ideal for use in devices like digital cameras and automotive systems. Its remarkable track record of over one hundred million shipments underscores its reliability and performance. Engineered with TAKUMI's proprietary architecture, GSHARK integrates advanced rendering capabilities. This architecture supports real-time, on-the-fly graphics processing similar to that found in PCs, smartphones, and gaming consoles, ensuring a rich user experience and efficient graphics applications. This IP excels in environments where power consumption and performance balance are crucial. GSHARK is at the forefront of embedded graphics solutions, providing significant improvements in processing speed while maintaining low energy usage. Its architecture easily handles demanding graphics rendering tasks, adding considerable value to any embedded system it is integrated into.
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