All IPs > Interface Controller & PHY
Interface Controller & PHY semiconductor IPs are integral components in modern digital systems that facilitate communication between various parts of an electronic system, including processors, memory, and peripherals. These IPs are designed to manage data traffic efficiently, ensuring reliable and high-speed data transfer between different interfaces and devices. This catalog features a wide range of IPs that serve various standard and custom interface protocols, making them indispensable for semiconductor companies developing complex SoCs (System on Chips) and digital systems.
In this category, you will find a selection of IPs tailored for popular interface protocols such as AMBA (AHB, APB, AXI), HDMI, PCI, USB, and MIPI, among others. Each IP solution is optimized for performance, supporting high-speed data transfer and reduced latency to meet the demanding needs of today's applications. These IPs not only provide seamless integration capabilities into your design but also ensure compliance with industry standards, which is crucial for interoperability in multi-vendor environments.
The embedded controllers within these IPs handle the logical functions necessary for device communication, while the PHY (physical layer) IPs manage the actual transmission and reception of data across physical media. Together, they enable efficient bridging between different communication protocols, making them critical components in a vast array of devices ranging from consumer electronics like smartphones and gaming consoles to industrial systems and automotive applications.
Our catalog also offers specialized solutions such as Multi-Protocol PHYs that support multiple standards within a single IP, providing flexibility and reducing the footprint for designs that require versatile connectivity options. By selecting the right Interface Controller & PHY IP from our catalog, developers can significantly enhance the functionality and overall performance of their products, leveraging the latest advancements in data interface technology. Explore our offerings and find the precise IP solutions needed to bring your innovative designs to life.
The LVDS IP is designed to provide Low Voltage Differential Signaling interfaces, a method known for reducing electromagnetic interference while enabling high-speed data transfer across circuits. Suitable for applications in displays and telecommunications, this IP supports robust signal integrity, adhering to strict technical and operational standards. Engineered for versatility, the LVDS IP operates efficiently over long distances, making it ideal for complex electronic environments where signal fidelity is paramount. Its adaptability allows for seamless integration into various system architectures. This IP focuses on minimizing power consumption without sacrificing performance, addressing the energy efficiency needs of modern electronic systems. Its compatibility and advanced design ensure that it meets diverse application requirements where high-speed, low-noise data communication is critical.
Primesoc's PCIE GEn7 IP is dual mode controller , supporting upto 128Gbps per lane data rate , which can work as root complex or as an endpoint. This is a soft IP which can support serdes and non serdes architectures and PIPE interface of 64bit and lanes configurable from 1/2/4/8/16.
Advanced Peripheral Bus (APB) is one of the Advanced Microcontroller Bus Architecture (AMBA) family protocols. It is a low-cost interface that is designed for low power consumption and interface simplicity. Unlike AHB, it is a non-pipelined protocol for connecting low-bandwidth peripherals. Mostly used to link external peripherals to the SOC. Every APB transfer requires at least two clock cycles (SETUP Cycle and ACCESS Cycle) to finish. The APB interface is designed for accessing the programmable control registers of peripheral devices. The APB protocol has two independent data buses, one for read data and one for write data. The buses can be 8, 16, or 32 bits wide. The read and write data buses must have the same width. Data transfers cannot occur concurrently because the read data and write data buses do not have their own individual handshake signals.
Silicon Creations' SerDes Interfaces are crafted to handle high-speed data transmission challenges over varied processes, ranging from 12nm to 180nm. Addressing multiple protocols such as CPRI, PCIe, and SATA, these interfaces demonstrate flexibility by supporting data transmission speeds from 100 Mbps to beyond 32 Gbps. The architecture incorporates a host of advanced features including adaptive equalization techniques and programmable de-serialization widths, making it stand out in terms of performance and signal integrity even under challenging conditions. With ultra-low latency PMAs, they sustain excellent operational speed and efficiency, imperative for sophisticated communication applications. Moreover, Silicon Creations partners with leading entities to provide comprehensive solutions, including complete PCIe PHY integrations. This synergy ensures that SerDes Interfaces are fully optimized for operational excellence, delivering stable and reliable communication signals. With an emphasis on low power and minimized area requirements, they cater to burgeoning industry needs for power-efficient and space-conservative designs.
The KL730 AI SoC is powered by Kneron's innovative third-generation reconfigurable NPU architecture, delivering up to 8 TOPS of computing power. This architecture offers enhanced efficiency for the latest CNNnetwork architectures and serves transformer applications by reducing DDR bandwidth requirements significantly. The chip excels in video processing, supporting 4K 60FPS output and excelling in areas such as noise reduction and low-light imaging. It's ideal for applications in intelligent security, autonomous driving, and video conferencing, among others.
AMBA AHB is a bus interface designed for high-performance synthesizable applications. It specifies the interface between components such as initiator , interconnects, and targets. AMBA AHB incorporates the features needed for high-performance, high clock frequency systems. The most common AHB targets are internal memory devices, external memory interfaces, and high-bandwidth peripherals.
The bus converter module transforms wide initiator data buses to smaller target data buses or vice-versa. A narrow target on a wide bus, only requires external logic and no internal design changes. * APB: 32-bit wide initiator data buses to 16-bit target data buses. * AHB: 64-bit wide initiator data buses to 32-bit target data buses. * AXI: 256-bit wide initiator data buses to 64-bit target data buses A wide target on a narrow bus, only requires external logic and no internal design changes. * APB: 16-bit wide initiator data buses to 32-bit target data buses. * AHB: 32-bit wide initiator data buses to 64-bit target data buses. * AXI: 64-bit wide initiator data buses to 256-bit target data buses.
Panmnesia's CXL 3.1 Switch is a pivotal component in networking a vast array of CXL-enabled devices, setting the bar with its exceptional scalability and diverse connectivity. The switch supports seamless integration of hundreds of devices including memory, CPUs, and accelerators, facilitating flexible, high-performance configurations suited to demanding applications in data centers and beyond. Panmnesia's design enables easy scalability and efficient memory node expansion, reflecting their dedication to resource-efficient memory management. The CXL 3.1 Switch features a robust architecture that supports a wide array of network topologies, allowing for multi-level switching and complex node configurations. Its design addresses the unique challenges of composable server architecture, enabling fine-grained resource allocation. The switch leverages Panmnesia's proprietary CXL technology, underpinning its ability to perform management tasks across integrated memory spaces with minimal overhead, crucial for achieving high-speed, low-latency data exchange. Incorporating CXL standards, it is fully compatible with both legacy and next-generation devices, ensuring broad interoperability. The architecture allows servers to tailor resource availability by employing type-specific CXL features, such as port-based routing and multi-level switching. These features empower operators with the tools to configure extensive networks of diverse devices efficiently, thereby maximizing data center performance while minimizing costs.
The Advanced eXtensible Interface(AXI) bus is a high-performance parallel bus that connects on-chip peripheral circuits (or IP blocks) to processor cores. The AXI bus employs "channels" to divide read and write transactions into semi-independent activities that can run at their own pace. The Read Address and Read Data channels send data from the target to the initiator, whereas the Write Address, Write Data, and Write Response channels transfer data from the initiator to the target.
Exostiv offers comprehensive functionality for in-depth monitoring and capturing of internal FPGA signals at operational speeds. It enables engineers to conduct precise and cost-effective analysis of their FPGA designs in realistic environments, overcoming the limitations of traditional simulation approaches. By providing extensive data capture abilities, Exostiv is an essential tool for minimizing engineering costs and ensuring the highest levels of design integrity. At the core of Exostiv is its versatility in compatibility, supporting a wide range of FPGA devices and ensuring adaptability to various prototyping boards. Its integration is bolstered by a range of connector options—including QSFP28 and Samtec ARF-6—providing small-footprint solutions ideal for space-tight configurations. With impressive data rates and bandwidth options, Exostiv propels performance analysis to new heights by allowing accurate trace capture and design visualization at speed. Engineers benefit from Exostiv’s ability to perform real-time signal monitoring directly on FPGA prototypes. This leads to substantial reductions in potential bugs reaching production, as the tool highlights discrepancies that might not be visible during simulations. Whether used for debugging or for SoC pre-production testing, Exostiv plays a vital role in streamlining engineering workflows, offering a blend of ease-of-use and powerful capabilities to address the most demanding validation scenarios.
Overview: The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features:  Compliance with MIPI-CSI-2 version 3.0  Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0  Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0  Compatibility with I2C and I3C (SDR, DDR) for CCI interface  Support for C-PHY 2.0, D-PHY 2.5, A-PHY, M-PHY with configurable PHY layer  Processor Interfaces: AHB Lite/APB/AXI for configuration  Lane Merging Function for consolidating packet data in CSI-2 Receiver  De-skew detection in D-PHY and sync word detection in C-PHY  Pixel Formats Supported: YUV, RGB, and RAW data  Virtual Channels: 16 for D-PHY, 32 for C-PHY  Error detection, interleaving, scrambling, and descrambling support  Byte to pixel conversion in LLP layer Applications:  Imaging  Surveillance  Gaming  Sensor devices  Internet of Things (IoT)  Wearable devices  Virtual Reality  Augmented Reality  Automotive Systems
Overview: The MIPI I3C Controller IP Core is fully compliant with the latest I3C specification, offering high bandwidth and scalability for integrating multiple sensors into mobile, automotive, and IoT system-on-chips (SoCs). This controller support in-band interrupts within the 2-wire interface, reducing pin count, simplifying board design, and lowering power and system costs. Backward compatibility with I2C ensures future-proof designs, and the controller's operating modes enable efficient connectivity for systems with multiple ICs and sensors on a single I3C bus. The ARM® AMBA® Advanced High-Performance Bus (AHB) facilitates seamless integration of the IP into the SoC. Key Features:  Compliance with MIPI-I3C Basic v1.0  Backward compatibility with I2C  Two-wire serial interface up to 12.5MHz using Push-Pull  Dynamic and Static Addressing support  Single Data Rate messaging (SDR)  Broadcast and Direct Common Command Code (CCC) Messages support  In-Band Interrupt capability  Hot-Join Support Applications:  Consumer Electronics  Defense  Aerospace  Virtual Reality  Augmented Reality  Medical  Biometrics (Fingerprints, etc.)  Automotive Devices  Sensor Devices
The Origin E1 is an optimized neural processing unit (NPU) targeting always-on applications in devices like home appliances, smartphones, and security cameras. It provides a compact, energy-efficient solution with performance tailored to 1 TOPS, making it ideal for systems needing low-power and minimal area. The architecture is built on Expedera's unique packet-based approach, which enables enhanced resource utilization and deterministic performance, significantly boosting efficiency while avoiding the pitfalls of traditional layer-based architectures. The architecture is fine-tuned to support standard and custom neural networks without requiring external memory, preserving privacy and ensuring fast processing. Its ability to process data in parallel across multiple layers results in predictive performance with low power and latency. Always-sensing cameras leveraging the Origin E1 can continuously analyze visual data, facilitating smoother and more intuitive user interactions. Successful field deployment in over 10 million devices highlights the Origin E1's reliability and effectiveness. Its flexible design allows for adjustments to meet the specific PPA requirements of diverse applications. Offered as Soft IP (RTL) or GDS, this engine is a blend of efficiency and capability, capitalizing on the full scope of Expedera's software tools and custom support features.
The Multi-Protocol SERDES offered by Pico Semiconductor is a versatile solution capable of handling a variety of communication protocols. This series of SERDES includes a 4-channel configuration that supports data rates up to 32Gbps, designed for integration with XAUI, RXAUI, and SGMII. It is compatible with multiple process nodes provided by foundries like TSMC and GF, offering robust performance across different semiconductor environments. These SERDES are crafted to meet high-performance metrics, capturing speeds up to 16Gbps and 6.5Gbps across various models, with advanced versions reaching up to 32Gbps. This exceptional range not only ensures compatibility with current technologies but also prepares systems for future updates, sustaining high data throughput. By delivering reliable high-speed data transmission capabilities, the Multi-Protocol SERDES from Pico Semiconductor is integral for networking, high-speed computing, and data storage applications, where efficient and speedy data transfer is paramount.
The eSi-Connect is a suite of AMBA peripheral IP cores designed to enhance connectivity and integration in Systems on Chip (SoCs). Directed towards simplifying the development process, eSi-Connect supports standard interfaces like AXI, AHB, and APB, making it a comprehensive toolset for various system integrations. This suite includes multiple memory controllers, off-chip interfaces, and utility functions such as timer and watchdogs, enabling developers to customize and scale solutions efficiently. The peripherals within the eSi-Connect ensure compatibility with a broad range of embedded systems while maintaining high performance and power efficiency. With an array of functionalities like GPIO, Ethernet MAC, and various serial interfaces, it provides low-level software drivers optimizing for real-time SoC deployment. Leveraging eSi-Connect, design teams can accelerate time-to-market with builds tailored to specific application needs, ensuring robustness and scalability.
The PCIe AI Accelerator Card powered by Metis AIPU offers unparalleled AI inference performance suitable for intensive vision applications. Incorporating a single quad-core Metis AIPU, it provides up to 214 TOPS, efficiently managing high-volume workloads with low latency. The card is further enhanced by the Voyager SDK, which streamlines application deployment, offering an intuitive development experience and ensuring simple integration across various platforms. Whether for real-time video analytics or other demanding AI tasks, the PCIe Accelerator Card is designed to deliver exceptional speed and precision.
The Metis AIPU M.2 accelerator module by Axelera AI is engineered for AI inference on edge devices with power and budget constraints. It leverages the quad-core Metis AIPU, delivering exceptional AI processing in a compact form factor. This solution is ideal for a range of applications, including computer vision in constrained environments, providing robust support for multiple camera feeds and parallel neural networks. With its easy integration and the comprehensive Voyager SDK, it simplifies the deployment of advanced AI models, ensuring high prediction accuracy and efficiency. This module is optimized for NGFF (Next Generation Form Factor) M.2 sockets, boosting the capability of any processing system with modest space and power requirements.
An interconnect component connects multi initiators and multi targets in a system. A single initiator system simply requires a decoder and multiplexor.
The AHB-Lite APB4 Bridge by Roa Logic represents a pivotal element in connecting different bus standards, essentially acting as a bridge between the AMBA 3 AHB-Lite v1.0 and the AMBA APB v2.0 protocols. This interconnect component is designed to facilitate data transfer and communication between various system components, ensuring efficiency and compatibility across multiple architectures. As a parameterized soft IP core, the bridge allows for extensive customization, tailoring bandwidth and performance requirements to suit specific application demands in both FPGA and ASIC designs. This versatility makes it ideal for use in diverse environments where protocol conversion is necessary. Supporting an array of peripherals, the bridge enables seamless integration and operation within larger, complex architectures. Its design reduces latency and power consumption, making it a preferred choice for creating energy-efficient and high-performance systems. Available for non-commercial licensing, this bridge epitomizes Roa Logic’s commitment to innovation through practical, user-focused IP solutions.
The CT25205 is a sophisticated digital controller designed for 10BASE-T1S Ethernet communications. Compatible with IEEE 802.3cg, it integrates the PMA, PCS, and PLCA Reconciliation sublayers, making it highly suitable for standard cells and FPGA systems. This synthesizable IP core supports seamless integration into any standard IEEE CSMA/CD Clause 4 Ethernet MAC via MII, which enhances its versatility for a multitude of applications. Its embedded PLCA RS uniquely allows existing MAC implementations to adopt advanced PLCA capabilities effortlessly, ensuring an increase in functionality without hardware overhauls. In conjunction with other Canova Tech IPs, such as the CT25208 MAC controller and CT25210 topology discovery IP, it provides a complete solution for implementing 10BASE-T1S within Zonal Gateways System on Chips (SoCs) and microcontrollers. The amalgamation of these components offers a streamlined approach to developing efficient network communication protocols, paving the way for innovative uses in industrial and automotive sectors where reliable data transmission is critical. This IP is especially adept at working alongside standard OPEN Alliance 10BASE-T1S PMD interfaces, reinforcing its compatibility with established industry protocols. For those developing multi-drop Ethernet solutions, the CT25205 stands as a premier choice. Its design, which ensures adherence to IEEE standards while promoting enhanced reliability and performance, makes it an attractive option for a range of applications, from simplifying connectivity in industrial setups to fortifying communications in vehicular networks, underscoring Canova Tech’s commitment to technological advancement and innovation.
Overview: The SPD5 Hub controller IP is designed to interface with the I3C/I2C Host Bus, allowing for the isolation of local devices such as Temperature Sensors (TS) from the master host bus. It features a Two-wire serial interface with SCL and SDA busses. Key Features:  Compliance with JEDEC's JESD300-5  Support for speeds up to 12.5MHz  Bus Reset functionality  SDA arbitration support  Enabled Parity Check  Support for Packet Error Check (PEC)  Switch between I2C and I3C Basic Mode  Default Read address pointer Mode  Write and read operations for SPD5 Hub with or without PEC  In-band Interrupt (IBI) support  Write Protection for NVM memory blocks  Arbitration for Interrupts  Clearing of Device Status and IBI Status Registers  Error handling for Packet Error Check and Parity Errors  Common Command Codes (CCC) for I3C Basic Mode  Dynamic IO Operation Mode Switching  Bus Clear and Bus Reset capabilities  SPD5 Command features for NVM memory and Register Space  Read and Write access to NVM memory  Support for Offline Tester operation Applications:  DDR5 DIMM Application Environment  DDR5 NVDIMM Application Environment  Automotive Devices  Memory Devices  Power Management Devices  Defense/Aerospace/Customer Electronics
The secondary or slave PHY interface, specifically designed for LPDDR4/4X/5, serves as a pivotal element for AI processors and alternative ASICs seeking the latest in high-speed, low-power LPDDR interface protocols. This IP facilitates seamless data interchange across various devices, compliant with established JEDEC standards. While initially crafted for the 7nm TSMC node, this PHY can be adapted for other logical processes, making it suitable for a diverse array of memory types ranging from traditional DRAM and SRAM to innovative non-volatile memories. This adaptability illustrates its robust application scope within modern technological frameworks.
Overview: The MIPI DSI Transmitter IP is designed to transmit data to the host processor, providing the mobile industry with a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features:  Compliance with MIPI-DSI-2 version 2.0  Compliance with C-PHY version 2.0 for DSI-2 Version-2  Compliance with D-PHY version 1.2 for DSI-2 Version-2.0  Compliance with D-PHY version 2.0 for DSI-2 Version-2.0  Compliance with D-PHY version 3.0 for DSI-2 Version-2.0  Compliance with MIPI SDF specification  Compliance with DBI-2 and DPI-2  Pixel to Byte conversion support from Application layer to LLP layer  Support for Command Mode and Video Mode  Continuous clock behavior in clock lane for D-PHY physical layer  De-skew sequence pattern for video mode support  Lane Distribution Function for distributing packet bytes across N-Lanes  Connectivity with two, three, or four DSI Receivers  HS mode and Escape mode support for transmission of Packets in both C-PHY and D-PHY  Symbol slip detection code and sync symbol insertion in C-PHY physical layer Target Applications:  Imaging  Surveillance  Gaming  Sensor devices  Internet of Things (IoT)  Wearable devices  Virtual Reality  Augmented Reality  Automotive Systems
MAXVY UCIe VIP , a state-of-the-art solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of your UCIe designs. MAXVY UCIe VIP is fully compliant with UCIe Specification version 1.0 and supports all the layers of the UCIe stack, such as FDI, RDI, LogPHY, PCIe, and CXL protocols. MAXVY UCIe VIP is also very user-friendly and flexible, with simple APIs, easy integrations, and configurable parameters. You can easily customize and control the UCIe functionality according to your needs. MAXVY UCIe VIP also provides a rich set of verification capabilities, such as protocol checks, functional coverage, traffic generation, error injection, and debug tools. You can easily monitor, detect, and report any issues or violations in your UCIe designs. MAXVY UCIe VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and supports all leading simulators. With MAXVY UCIe VIP, very flexible for unit level testing, you can achieve faster verification closure and higher quality of your UCIe designs.
Silicon Creations crafts highly reliable LVDS interfaces designed to meet diverse application needs, going from bi-directional I/Os to specialized uni-directional configurations. Spanning process compatibilities from 90nm CMOS to advanced 7nm FinFET, these interfaces are a cornerstone for high-speed data communication systems, thriving particularly in video data transmission and chip-to-chip communications. Supporting robust data rates over multiple channels, the LVDS Interfaces guarantee flexible programmability and protocol compatibility with standards such as FPD-Link and Camera-Link. They capitalize on proven PLL and CDR architectures for superior signal integrity and error-free data transfers. Operating efficiently in various technology nodes, they remain highly effective across collaborative chipset environments. The interfaces are fortified with adaptable features like dynamic phase alignment to stabilize data sequences and on-die termination options for superior signal integrity. Their proven record places them as a critical enabler in applications where consistent high-speed data transfer is paramount, demonstrating Silicon Creations’ prowess in delivering industry-leading communication solutions.
Eliyan's NuLink Die-to-Die PHY technology represents a significant advancement in chiplet interconnect solutions. Designed for standard packaging, this innovative PHY IP delivers robust high-performance with low power consumption, a balance that is crucial for modern semiconductor designs. The NuLink PHY supports multiple industry standards, including the Universal Chiplet Interface Express (UCIe) and Bunch of Wires (BoW), ensuring it can cater to a wide range of applications. A standout feature of the NuLink PHY is its simultaneous bidirectional (SBD) signaling capability, which allows data to be sent and received over the same wire at the same time, effectively doubling bandwidth. This makes it an ideal solution for data-intensive applications such as AI training and inference, particularly those requiring ultra-low latency and high reliability. The technology is also adaptable for different substrates, including both silicon and organic, offering designers flexibility in their packaging approaches. NuLink's architecture stems from extensive industry insights and is informed by Eliyan’s commitment to innovation. The platform provides a power-efficient and cost-effective alternative to traditional advanced packaging solutions. It achieves interposer-like performance metrics without the complexity and cost associated with such methods, enabling operational efficiency and reduced time-to-market for new semiconductor products.
This high-powered TCP Offload Engine aims to deliver superior efficiency by offloading TCP processing from the CPU. By integrating a MAC interface, it reduces processing latencies and broadens throughput, thereby optimizing network operations substantially. This IP suite maintains rapid data processing speeds and addresses a broad array of network optimization needs for today's high-demand environments. Optimized for high-speed networking environments, the TOE offers unprecedented latency reduction through its hardware-accelerated design. The integration of a refined MAC interface plays a crucial role in translating packet data into usable formats swiftly, a crucial factor in enhancing overall system performance, particularly in data-intensive industries. This technology’s edge lies in its ability to seamlessly deliver full data transfer acceleration. Its design caters to enterprises that prioritize low-processing overheads and need to maximize network efficiency without the traditional constraints of higher CPU usage. Thus, Intilop's 10G TCP Offload Engine represents a benchmark in high-performance data handling systems.
The AHB-Lite Multilayer Switch from Roa Logic is engineered for high-efficiency performance, serving as an interconnect fabric that supports numerous bus masters and slaves. This architecture is crucial in systems that require low latency data processing and robust bandwidth capacities to handle heavy data traffic between multiple modules. Designed to handle a virtually unlimited number of masters and slaves, this switch enhances system scalability, allowing the seamless expansion of functionalities in complex SOC configurations. Its low latency characteristics ensure data is transmitted with minimal delay, optimizing system performance and stability. Developed for both ASIC and FPGA implementations, this product aligns with AMBA interconnect specifications, ensuring compatibility and simplifying integration into existing designs. Its free non-commercial licensing promotes broader accessibility, encouraging experimentation and adoption in various technological projects.
KPIT's Connected Vehicle Solutions enable OEMs to harness the power of integrated vehicle-to-cloud connectivity and data analytics. By leveraging cloud-native infrastructure and edge analytics, these solutions facilitate innovative data management, enhance cybersecurity, and ensure regulatory compliance. KPIT helps automakers streamline data flows from connected vehicles, optimizing operational efficiency while creating new revenue streams through advanced analytics and connectivity services.
MIPI I3C Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs). The MIPI I3C Controller supports in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost of the system. The MIPI I3C Controller IP is fully backward compatible with I2C, allowing designers to future proof their design, and the I3C controller IP operating modes enable systems with several ICs to efficiently connect to all sensors on a single I3C bus. The standard-based ARM® AMBA® Advanced High Performance Bus (AHB) connects the IP to the rest of the SoC offering easy IP integration. MIPI I3C Controller IP is designed to easily integrate into any SoC offering lowest gate count and quickly fit into any Chip development flow.
This IP offers a high-performance mixed-signal CODEC solution perfect for advanced audio applications. It seamlessly integrates analog-to-digital and digital-to-analog conversion capabilities, ensuring an immersive audio experience with minimal latency and superior sound fidelity. The CODEC is specifically designed to handle multiple audio interface formats, providing adaptability across various platforms and devices. One of the strengths of this CODEC is its optimized power consumption. It is crafted to deliver top-tier performance while maintaining efficient energy use, which is essential for battery-powered and portable devices. The versatility of the CODEC makes it an ideal choice for a wide range of applications, from automotive audio systems to consumer electronics. Additionally, this solution is engineered with robust support for different process nodes, enhancing its compatibility with a multitude of manufacturing technologies. This makes it not only efficient but also versatile, allowing for straightforward integration into diverse product lines.
The Ethernet Real-Time Publish-Subscribe (RTPS) Core is designed to deliver complete hardware solutions for the Ethernet RTPS protocol. It stands out by providing reliable networking capabilities needed in environments that demand stringent real-time data exchanges. This core enhances data communication efficiencies by facilitating rapid publish-subscribe interactions within complex network ecosystems. Optimized for environments that require high data throughput and consistency, it ensures that data exchanges are executed with precision and timeliness. Its architectural elegance supports seamless integration into existing networks, promoting a resilient exchange of information crucial for operational continuity. This core is pivotal for ensuring robust communication frameworks in mission-critical systems where delays and data losses are unacceptable.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 128Gbps and multi lanes and links. The layers speci_ied in PCIE speci_ication Transport, Datalink, Physical layers (digital packet) are implemented in PRIMEXPRESS IP along with PIPE interface logic connecting to PHY and AXI Bridging logic to connect to applications. Features: • Supports PCIE Gen 7 draft Spec. • Supports Pipe 6.X Spec. • PCIE Gen 7.0 Core supports Flit and non – Flit Mode. • Supports X16, X8, X4, X2, X1 Lane Configuration. • AXI MM and Streaming supported. • Supports Gen 1, Gen 2, Gen 3, Gen 4, Gen 5, Gen 6, Gen 7 modes. • Data rate support of 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps, 32 Gbps, 64 Gbps, 128 Gbps. • PAM support when operating at 64Gbps/ 128Gbps. • 8b/10b,128b/130b,1b/1b encoding , decoding support. • Supports serdes and non – serdes architecture. • Optional DMA support as plugin module. • Support for alternate negotiation protocol. • Lane polarity thru register control. • Lane deskew supported. • Support for L1 states. • L0P Supported. • SKP OS add/removal. • SRIS mode supported. • No equalization support thru configuration. • Deemphasis negotiation support at 5GT/s. • EI inferences in all modes. • PTM, OBFF, MSI, MSIX, Power management and all message format supports.
Overview: The MIPI CSI-2 (Camera Serial Interface) Transmitter IP establishes an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that caters to a wide range of imaging solutions for mobile devices. Key Features:  Compliance with MIPI-CSI-2 version 3.0  Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0  Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0  Compatibility with I2C and I3C (SDR, DDR) for CCI interface  Pixel to Byte conversion support from Application layer to LLP layer  Continuous clock behavior in clock lane for D-PHY physical layer  De-skew sequence pattern in Data Lane Module  Lane Distribution Function for distributing packet bytes across N-Lanes  Sync word insertion through PPI command in C-PHY physical layer  Insertion of Filler bytes in LLP layer for packet footer alignment  Setting specific bits in packet header  Defining frame blanking period  Seed selection in scrambler and de-scrambler by Sync word  Support for C-PHY/D-PHY/A-PHY/M-PHY with one PHY layer configuration Target Applications:  Imaging  Surveillance  Gaming  Sensor devices  Internet of Things (IoT)  Wearable devices  Virtual Reality  Augmented Reality  Automotive Systems
The Aries fgOTN processor family is engineered according to the ITU-T G.709.20 fgOTN standard. This line of processors handles a variety of signals, including E1/T1, FE/GE, and STM1/STM4, effectively monitoring and managing alarms and performance metrics. Aries processors excel at fine-grain traffic aggregation, efficiently channeling fgODUflex traffic across OTN lines to support Ethernet, SDH, PDH client services. Their capacity to map signals to fgODUflex containers, which are then multiplexed into higher order OTN signals, demonstrates their versatility and efficiency. By allowing cascaded configurations with other Aries devices or Apodis processors, Aries products optimize traffic routes through OTN infrastructures, positioning them as essential components in optical networking and next-generation access scenarios.
The PDM-to-PCM Converter offers an innovative solution for converting pulse-density modulation signals into pulse-code modulation formats, supporting the growing demand in modern audio processing systems. This converter is indispensable for applications where maintaining audio integrity is paramount, such as digital microphones and audio streaming devices. Engineered for efficiency, the converter handles high-definition audio with minimal distortion, ensuring the audio signal remains true to the source. The design incorporates various filters that minimize unwanted artifacts, a crucial feature for any high-end audio system requiring pristine sound quality. This converter supports a wide array of audio interfaces, facilitating its integration into diverse audio frameworks—from IoT devices to advanced multi-channel audio systems. Moreover, its low-power design makes it ideal for use in portable devices, enabling manufacturers to develop products that meet both performance and power consumption metrics.
The Origin E8 NPU by Expedera is engineered for the most demanding AI deployments such as automotive systems and data centers. Capable of delivering up to 128 TOPS per core and scalable to PetaOps with multiple cores, the E8 stands out for its high performance and efficient processing. Expedera's packet-based architecture allows for parallel execution across varying layers, optimizing resource utilization, and minimizing latency, even under strenuous conditions. The E8 handles complex AI models, including large language models (LLMs) and standard machine learning frameworks, without requiring significant hardware-specific changes. Its support extends to 8K resolutions and beyond, ensuring coverage for advanced visualization and high-resolution tasks. With its low deterministic latency and minimized DRAM bandwidth needs, the Origin E8 is especially suitable for high-performance, real-time applications. The high-speed processing and flexible deployment benefits make the Origin E8 a compelling choice for companies seeking robust and scalable AI infrastructure. Through customized architecture, it efficiently addresses the power, performance, and area considerations vital for next-generation AI technologies.
The H.264 FPGA Encoder and CODEC Micro Footprint Cores from A2e Technologies are industry-leading solutions optimized for high-speed video encoding with minimal latency. Specially tailored for FPGA applications, this core ensures compliance with the H.264 Baseline and offers configurations to suit varying performance needs, such as low-cost evaluation licenses for flexibility. These cores are noted for their exceptionally compact size and rapid processing capabilities, enabling them to achieve 1080p at 60 frames per second with remarkable efficiency. One of the project's standout features is the 1ms latency at 1080p30, which is among the fastest in the industry. This core also supports custom configurations, allowing adjustments to pixel depth, resolution, and more, making it a versatile choice for developers looking to integrate video encoding in their systems. Moreover, these cores are ITAR compliant, offering a secure and adaptable solution for high-performance FPGA design. The scalability and customization options, including support for various pixel depths and resolutions, make these H.264 cores suitable for a wide array of applications, from real-time video streaming to embedded systems in industrial automation. By leveraging this advanced technology, A2e Technologies provides a robust solution that meets stringent industry standards and addresses specific customer needs effectively.
The ORC3990 SoC is a state-of-the-art solution designed for satellite IoT applications within Totum's DMSSâ„¢ network. This low-power sensor-to-satellite system integrates an RF transceiver, ARM CPUs, memories, and PA to offer seamless IoT connectivity via LEO satellite networks. It boasts an optimized link budget for effective indoor signal coverage, eliminating the need for additional GNSS components. This compact SoC supports industrial temperature ranges and is engineered for a 10+ year battery life using advanced power management.
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 128Gbps and multi lanes and links. The layers speci_ied in PCIE speci_ication Transport, Datalink, Physical layers (digital packet) are implemented in PRIMEXPRESS IP along with PIPE interface logic connecting to PHY and AXI Bridging logic to connect to applications. Features: • Supports PCIE Gen 7 Spec. • Supports Pipe 6.X Spec. • PCIE Gen 7.0 Core supports Flit and non – Flit Mode. • Supports X16, X8, X4, X2, X1 Lane Configura􀆟on. • AXI MM and Streaming supported. • Supports Gen 1, Gen 2, Gen 3, Gen 4, Gen 5, Gen 6, Gen 7 modes. • Data rate support of 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps, 32 Gbps, 64 Gbps, 128 Gbps. • PAM support when operating at 64Gbps/ 128Gbps. • 8b/10b,128b/130b,1b/1b encoding , decoding support. • Supports serdes and non – serdes architecture. • Op􀆟onal DMA support as plugin module. • Support for alternate nego􀆟a􀆟on protocol. • Lane polarity thru register control. • Lane deskew supported. • Support for L1 states. • L0P Supported. • SKP OS add/removal. • SRIS mode supported. • No equalization support thru configura􀆟on. • Deemphasis negotiation support at 5GT/s. • EI inferences in all modes. • PTM, OBFF, MSI, MSIX, Power management and all message format supports.
Silicon Library's DisplayPort/eDP is engineered to enhance visual display performance, supporting seamless data transfer for high-definition content. This module adheres to DisplayPort standards, promising superb visual quality across a range of display devices. Designed for versatility, the DisplayPort/eDP is suitable for integration into a myriad of devices, from laptops to computer monitors. It supports high-resolution display outputs, ensuring crisp and vivid visuals, crucial for gaming and graphic design applications. This product is equipped to handle high data rates, facilitating smooth media playback without any lag, making it suitable for high-performance multimedia applications. Integrated with advanced features, it also ensures compatibility with various system architectures, providing a reliable solution for modern digital requirements.
The ePHY-5616 is a high-performance SerDes solution from eTopus, designed for versatile use across enterprise, data center, and 5G applications. Operating efficiently at data rates from 1 to 56 Gbps, this product exploits advanced DSP techniques for superior signal integrity and robustness. It accommodates wide insertion loss ranges of 10dB to over 35dB, thus ensuring reliable performance in challenging communication environments. Its architecture supports direct optical drives and quad/octal configurations, making it ideal for network interface cards, routers, and high-speed switches in a data center setup. The embedded DSP architecture is developed with eTopus's proprietary algorithms, which enable rapid SerDes tuning and performance optimization. The ePHY-5616 is also characterized by its low Bit Error Rate (BER), ensuring data reliability and integrity. Moreover, it supports multiple protocols, including Ethernet and PCIe, enhancing its integration potential in modern broadband networks.
The Ultra-Low Latency 10G Ethernet MAC IP core is engineered to optimize network performance by reducing latency and increasing data throughput. It provides an essential solution for applications requiring high-speed, reliable network connectivity through the use of FPGA technologies. Designed to fit efficiently within FPGA architectures, this MAC core consumes fewer resources while maintaining performance. It achieves this by offering a streamlined all-RTL solution that minimizes complexity, reliance on CPUs, and power consumption. Available in both cut-through and store-and-forward modes, this MAC allows for adaptable network configurations to suit project-specific requirements. The Ultra-Low Latency Ethernet MAC IP features advanced capabilities such as Deficit Idle Control, which optimizes throughput by controlling the inter-frame gap, ensuring smooth data streaming. The integration of a robust error-checking and correction mechanism further supports reliable, high-performance data transfer, making it ideal for demanding applications.
The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI). The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
Overview: The Power Management IC (PMIC) is specifically designed for DDR5 RDIMM, DDR5 LRDIMM, and DDR5 NVDIMM applications. It includes switching and LDO regulators to efficiently manage power distribution. The PMIC utilizes a MIPI-I3C Interface to select appropriate power settings for various application environments and is capable of operating at speeds up to 12.5MHz. Key Features:  Maximum Operating speed of 12.5MHz  Flexible Open-Drain IO (I2C) and Push-Pull (I3C) IO Support  Multi-Time Programmable Non-Volatile Memory Interface  Programmable and DIMM-specific registers for customization  Error log registers for tracking  Packet Error Check (PEC) and Parity Error Check functions  Bus Reset function  Support I3C Basic mode  In-Band Interrupt (IBI) support  Write, read, and default read operations in I2C mode  Error handling for PEC, Parity errors, and CCC errors  I3C Basic Common Command Codes (CCC) support Applications:  DDR5 DIMM Application Environment  DDR5 NVDIMM Application Environment  Automotive Devices  Memory Devices  Power Management Devices  Defense/Aerospace/Customer Electronics
The 10G Ethernet MAC and PCS from Chevin Technology is designed to offer high-speed Ethernet connectivity for FPGAs. This IP core maximizes throughput with low latency and fits within a compact architecture that utilizes minimal FPGA resources. It adheres to IEEE 802.3by standards, making it ideal for seamless integration in various FPGA designs, including those with a focus on ultra-fast duplex Ethernet. Chevin Technology’s 10G MAC simplifies synthesis by offering a user-friendly guide and expert support, ensuring minimal disruption to your existing design. It is compatible with both Intel and Xilinx FPGA families, and features an all-logic architecture which lowers energy consumption and reduces latency by not requiring additional CPU or software overheads. The design offers both cut-through and store-and-forward operational modes, along with a powerful CRC32 engine for error detection and correction during data transmission. Reference designs for boards such as Bittware IA-840F and Alpha Data ADM-PCIE-8V3 are available to aid in rapid deployment and integration.
The HOTLink II Product Suite is a powerful video transmission solution that enables secure and rapid data exchange for avionics applications. This suite by Great River Technology is designed to facilitate seamless high-speed digital communications, minimizing latency while enhancing the system's reliability in demanding environments. The suite encompasses a range of tools that streamline the development and deployment of HOTLink II systems, which are crucial for managing high-bandwidth data flows. It offers extensive support mechanisms through well-crafted documentation and robust simulation tools, aiding engineers in achieving optimized system performance and regulatory compliance. By leveraging the HOTLink II Product Suite, users can achieve improved data integrity and support for multiple video interfaces, ensuring the readiness of systems for various missions. This makes the suite a vital component for both military and civilian aerospace projects, offering extensive scalability and customization to suit specific operational needs.
The pPLL03F-GF22FDX is a state-of-the-art, all-digital Fractional-N PLL crafted specifically for performance computing environments, offering low jitter and compact design. This advanced PLL is optimized for clocking applications that demand precise timing, functioning at frequencies of up to 4GHz. Its architecture makes it an excellent choice for driving performance computers and ADC/DAC systems where moderate SNR is essential. Constructed utilizing Perceptia's robust second-gen all-digital PLL technology, it delivers consistent results across a broad spectrum of process variations and conditions. Noteworthy for its tiny area, the pPLL03F enables system designers to efficiently manage complex multi-domain clock systems utilizing shared power supplies. Each instance includes a built-in power regulator, facilitating seamless sharing of power across various blocks relying on its clock outputs. Featuring dual PLL outputs through distinct postscalers, it's designed for easy integration into SOC systems while being highly testable, supporting industry-standard flows. It is usable in both integer-N and fractional-N modes, offering substantial flexibility in synchronizing input-output clock frequencies at the system level. The design encompasses compactness and effectiveness, ensuring low consumption while maintaining superior performance.
The CT25203 serves as an analog front-end module for implementing 10BASE-T1S PHY solutions, conforming to IEEE 802.3cg standards. It is an essential component for engineers and researchers focused on creating efficient Ethernet networks within industrial and automotive ecosystems. This IP core facilitates seamless communication via standard pins, ensuring optimal interaction between the physical layer and digital control counterparts. Featuring high EMC performance, it is implemented on high-voltage process technology, underscoring its reliability for robust communication solutions. The CT25203 allows the development of devices that communicate effectively over standard OPEN Alliance TC14 interfaces, bridging connections between the MAC and PHY layers while supporting various configurations that enhance data integrity and transmission efficiency across the network. This analog front-end represents a critical building block within Canova Tech’s suite of Ethernet solutions. By enabling sturdy and efficient connections in Ethernet-based systems, it directly contributes to easing the path toward modern industrial and vehicular network implementations. Whether for facilitating data flow or ensuring system stability, the CT25203 highlights Canova Tech’s dedication to delivering high-performance IP solutions tailored to complex real-world demands.
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