All IPs > Interface Controller & PHY
Interface Controller & PHY semiconductor IPs are integral components in modern digital systems that facilitate communication between various parts of an electronic system, including processors, memory, and peripherals. These IPs are designed to manage data traffic efficiently, ensuring reliable and high-speed data transfer between different interfaces and devices. This catalog features a wide range of IPs that serve various standard and custom interface protocols, making them indispensable for semiconductor companies developing complex SoCs (System on Chips) and digital systems.
In this category, you will find a selection of IPs tailored for popular interface protocols such as AMBA (AHB, APB, AXI), HDMI, PCI, USB, and MIPI, among others. Each IP solution is optimized for performance, supporting high-speed data transfer and reduced latency to meet the demanding needs of today's applications. These IPs not only provide seamless integration capabilities into your design but also ensure compliance with industry standards, which is crucial for interoperability in multi-vendor environments.
The embedded controllers within these IPs handle the logical functions necessary for device communication, while the PHY (physical layer) IPs manage the actual transmission and reception of data across physical media. Together, they enable efficient bridging between different communication protocols, making them critical components in a vast array of devices ranging from consumer electronics like smartphones and gaming consoles to industrial systems and automotive applications.
Our catalog also offers specialized solutions such as Multi-Protocol PHYs that support multiple standards within a single IP, providing flexibility and reducing the footprint for designs that require versatile connectivity options. By selecting the right Interface Controller & PHY IP from our catalog, developers can significantly enhance the functionality and overall performance of their products, leveraging the latest advancements in data interface technology. Explore our offerings and find the precise IP solutions needed to bring your innovative designs to life.
Advanced Peripheral Bus (APB) is one of the Advanced Microcontroller Bus Architecture (AMBA) family protocols. It is a low-cost interface that is designed for low power consumption and interface simplicity. Unlike AHB, it is a non-pipelined protocol for connecting low-bandwidth peripherals. Mostly used to link external peripherals to the SOC. Every APB transfer requires at least two clock cycles (SETUP Cycle and ACCESS Cycle) to finish. The APB interface is designed for accessing the programmable control registers of peripheral devices. The APB protocol has two independent data buses, one for read data and one for write data. The buses can be 8, 16, or 32 bits wide. The read and write data buses must have the same width. Data transfers cannot occur concurrently because the read data and write data buses do not have their own individual handshake signals.
Primesoc's PCIE GEn7 IP is dual mode controller , supporting upto 128Gbps per lane data rate , which can work as root complex or as an endpoint. This is a soft IP which can support serdes and non serdes architectures and PIPE interface of 64bit and lanes configurable from 1/2/4/8/16.
The bus converter module transforms wide initiator data buses to smaller target data buses or vice-versa. A narrow target on a wide bus, only requires external logic and no internal design changes. * APB: 32-bit wide initiator data buses to 16-bit target data buses. * AHB: 64-bit wide initiator data buses to 32-bit target data buses. * AXI: 256-bit wide initiator data buses to 64-bit target data buses A wide target on a narrow bus, only requires external logic and no internal design changes. * APB: 16-bit wide initiator data buses to 32-bit target data buses. * AHB: 32-bit wide initiator data buses to 64-bit target data buses. * AXI: 64-bit wide initiator data buses to 256-bit target data buses.
AMBA AHB is a bus interface designed for high-performance synthesizable applications. It specifies the interface between components such as initiator , interconnects, and targets. AMBA AHB incorporates the features needed for high-performance, high clock frequency systems. The most common AHB targets are internal memory devices, external memory interfaces, and high-bandwidth peripherals.
Silicon Creations' SerDes Interfaces are crafted to handle high-speed data transmission challenges over varied processes, ranging from 12nm to 180nm. Addressing multiple protocols such as CPRI, PCIe, and SATA, these interfaces demonstrate flexibility by supporting data transmission speeds from 100 Mbps to beyond 32 Gbps. The architecture incorporates a host of advanced features including adaptive equalization techniques and programmable de-serialization widths, making it stand out in terms of performance and signal integrity even under challenging conditions. With ultra-low latency PMAs, they sustain excellent operational speed and efficiency, imperative for sophisticated communication applications. Moreover, Silicon Creations partners with leading entities to provide comprehensive solutions, including complete PCIe PHY integrations. This synergy ensures that SerDes Interfaces are fully optimized for operational excellence, delivering stable and reliable communication signals. With an emphasis on low power and minimized area requirements, they cater to burgeoning industry needs for power-efficient and space-conservative designs.
The Advanced eXtensible Interface(AXI) bus is a high-performance parallel bus that connects on-chip peripheral circuits (or IP blocks) to processor cores. The AXI bus employs "channels" to divide read and write transactions into semi-independent activities that can run at their own pace. The Read Address and Read Data channels send data from the target to the initiator, whereas the Write Address, Write Data, and Write Response channels transfer data from the initiator to the target.
Overview: The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features:  Compliance with MIPI-CSI-2 version 3.0  Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0  Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0  Compatibility with I2C and I3C (SDR, DDR) for CCI interface  Support for C-PHY 2.0, D-PHY 2.5, A-PHY, M-PHY with configurable PHY layer  Processor Interfaces: AHB Lite/APB/AXI for configuration  Lane Merging Function for consolidating packet data in CSI-2 Receiver  De-skew detection in D-PHY and sync word detection in C-PHY  Pixel Formats Supported: YUV, RGB, and RAW data  Virtual Channels: 16 for D-PHY, 32 for C-PHY  Error detection, interleaving, scrambling, and descrambling support  Byte to pixel conversion in LLP layer Applications:  Imaging  Surveillance  Gaming  Sensor devices  Internet of Things (IoT)  Wearable devices  Virtual Reality  Augmented Reality  Automotive Systems
Overview: The MIPI I3C Controller IP Core is fully compliant with the latest I3C specification, offering high bandwidth and scalability for integrating multiple sensors into mobile, automotive, and IoT system-on-chips (SoCs). This controller support in-band interrupts within the 2-wire interface, reducing pin count, simplifying board design, and lowering power and system costs. Backward compatibility with I2C ensures future-proof designs, and the controller's operating modes enable efficient connectivity for systems with multiple ICs and sensors on a single I3C bus. The ARM® AMBA® Advanced High-Performance Bus (AHB) facilitates seamless integration of the IP into the SoC. Key Features:  Compliance with MIPI-I3C Basic v1.0  Backward compatibility with I2C  Two-wire serial interface up to 12.5MHz using Push-Pull  Dynamic and Static Addressing support  Single Data Rate messaging (SDR)  Broadcast and Direct Common Command Code (CCC) Messages support  In-Band Interrupt capability  Hot-Join Support Applications:  Consumer Electronics  Defense  Aerospace  Virtual Reality  Augmented Reality  Medical  Biometrics (Fingerprints, etc.)  Automotive Devices  Sensor Devices
Overview: The SPD5 Hub controller IP is designed to interface with the I3C/I2C Host Bus, allowing for the isolation of local devices such as Temperature Sensors (TS) from the master host bus. It features a Two-wire serial interface with SCL and SDA busses. Key Features:  Compliance with JEDEC's JESD300-5  Support for speeds up to 12.5MHz  Bus Reset functionality  SDA arbitration support  Enabled Parity Check  Support for Packet Error Check (PEC)  Switch between I2C and I3C Basic Mode  Default Read address pointer Mode  Write and read operations for SPD5 Hub with or without PEC  In-band Interrupt (IBI) support  Write Protection for NVM memory blocks  Arbitration for Interrupts  Clearing of Device Status and IBI Status Registers  Error handling for Packet Error Check and Parity Errors  Common Command Codes (CCC) for I3C Basic Mode  Dynamic IO Operation Mode Switching  Bus Clear and Bus Reset capabilities  SPD5 Command features for NVM memory and Register Space  Read and Write access to NVM memory  Support for Offline Tester operation Applications:  DDR5 DIMM Application Environment  DDR5 NVDIMM Application Environment  Automotive Devices  Memory Devices  Power Management Devices  Defense/Aerospace/Customer Electronics
Overview: The MIPI DSI Transmitter IP is designed to transmit data to the host processor, providing the mobile industry with a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features:  Compliance with MIPI-DSI-2 version 2.0  Compliance with C-PHY version 2.0 for DSI-2 Version-2  Compliance with D-PHY version 1.2 for DSI-2 Version-2.0  Compliance with D-PHY version 2.0 for DSI-2 Version-2.0  Compliance with D-PHY version 3.0 for DSI-2 Version-2.0  Compliance with MIPI SDF specification  Compliance with DBI-2 and DPI-2  Pixel to Byte conversion support from Application layer to LLP layer  Support for Command Mode and Video Mode  Continuous clock behavior in clock lane for D-PHY physical layer  De-skew sequence pattern for video mode support  Lane Distribution Function for distributing packet bytes across N-Lanes  Connectivity with two, three, or four DSI Receivers  HS mode and Escape mode support for transmission of Packets in both C-PHY and D-PHY  Symbol slip detection code and sync symbol insertion in C-PHY physical layer Target Applications:  Imaging  Surveillance  Gaming  Sensor devices  Internet of Things (IoT)  Wearable devices  Virtual Reality  Augmented Reality  Automotive Systems
The LPDDR4/4X/5 Secondary/Slave PHY is engineered to complement main PHY systems by enhancing their capacity for data management and processing simultaneously. This component maintains the effective data transfer rates characteristic of the LPDDR series, ensuring that secondary systems can manage alternative data streams without bottlenecking. Optimized for parallel processing, it supports additional pathways for data, ensuring that extensive data sets and complex calculations do not impede system performance. The design adheres to JEDEC standards, promising seamless compatibility with master PHY systems.
An interconnect component connects multi initiators and multi targets in a system. A single initiator system simply requires a decoder and multiplexor.
The eSi-Connect suite provides a wide array of AMBA-compliant peripheral IP designed to simplify and standardize connectivity and integration within complex SoC environments. This suite includes versatile memory controllers and wide-ranging off-chip interfaces like USB, I2C, and UART, enabling comprehensive system integration. Each peripheral block within eSi-Connect is highly configurable, allowing tailored deployment backed by low-level software drivers to assure real-time performance. The integration is streamlined through standardized interfaces that facilitate seamless incorporation into existing systems. eSi-Connect is engineered for adaptability and efficiency, supporting communication protocols and control functions essential for a variety of real-time applications, ensuring robust and flexible peripheral connectivity in embedded environments.
Silicon Creations crafts highly reliable LVDS interfaces designed to meet diverse application needs, going from bi-directional I/Os to specialized uni-directional configurations. Spanning process compatibilities from 90nm CMOS to advanced 7nm FinFET, these interfaces are a cornerstone for high-speed data communication systems, thriving particularly in video data transmission and chip-to-chip communications. Supporting robust data rates over multiple channels, the LVDS Interfaces guarantee flexible programmability and protocol compatibility with standards such as FPD-Link and Camera-Link. They capitalize on proven PLL and CDR architectures for superior signal integrity and error-free data transfers. Operating efficiently in various technology nodes, they remain highly effective across collaborative chipset environments. The interfaces are fortified with adaptable features like dynamic phase alignment to stabilize data sequences and on-die termination options for superior signal integrity. Their proven record places them as a critical enabler in applications where consistent high-speed data transfer is paramount, demonstrating Silicon Creations’ prowess in delivering industry-leading communication solutions.
Overview: The Power Management IC (PMIC) is specifically designed for DDR5 RDIMM, DDR5 LRDIMM, and DDR5 NVDIMM applications. It includes switching and LDO regulators to efficiently manage power distribution. The PMIC utilizes a MIPI-I3C Interface to select appropriate power settings for various application environments and is capable of operating at speeds up to 12.5MHz. Key Features:  Maximum Operating speed of 12.5MHz  Flexible Open-Drain IO (I2C) and Push-Pull (I3C) IO Support  Multi-Time Programmable Non-Volatile Memory Interface  Programmable and DIMM-specific registers for customization  Error log registers for tracking  Packet Error Check (PEC) and Parity Error Check functions  Bus Reset function  Support I3C Basic mode  In-Band Interrupt (IBI) support  Write, read, and default read operations in I2C mode  Error handling for PEC, Parity errors, and CCC errors  I3C Basic Common Command Codes (CCC) support Applications:  DDR5 DIMM Application Environment  DDR5 NVDIMM Application Environment  Automotive Devices  Memory Devices  Power Management Devices  Defense/Aerospace/Customer Electronics
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 128Gbps and multi lanes and links. The layers speci_ied in PCIE speci_ication Transport, Datalink, Physical layers (digital packet) are implemented in PRIMEXPRESS IP along with PIPE interface logic connecting to PHY and AXI Bridging logic to connect to applications. Features: • Supports PCIE Gen 7 draft Spec. • Supports Pipe 6.X Spec. • PCIE Gen 7.0 Core supports Flit and non – Flit Mode. • Supports X16, X8, X4, X2, X1 Lane Configuration. • AXI MM and Streaming supported. • Supports Gen 1, Gen 2, Gen 3, Gen 4, Gen 5, Gen 6, Gen 7 modes. • Data rate support of 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps, 32 Gbps, 64 Gbps, 128 Gbps. • PAM support when operating at 64Gbps/ 128Gbps. • 8b/10b,128b/130b,1b/1b encoding , decoding support. • Supports serdes and non – serdes architecture. • Optional DMA support as plugin module. • Support for alternate negotiation protocol. • Lane polarity thru register control. • Lane deskew supported. • Support for L1 states. • L0P Supported. • SKP OS add/removal. • SRIS mode supported. • No equalization support thru configuration. • Deemphasis negotiation support at 5GT/s. • EI inferences in all modes. • PTM, OBFF, MSI, MSIX, Power management and all message format supports.
Designed for high-performance applications, the Metis AIPU PCIe AI Accelerator Card employs four Metis AI Processing Units to deliver exceptional computational power. With its ability to reach up to 856 TOPS, this card is tailored for demanding vision applications, making it suitable for real-time processing of multi-channel video data. The PCIe form factor ensures easy integration into existing systems, while the customized software platform simplifies the deployment of neural networks for tasks like YOLO object detection. This accelerator card ensures scalability and efficiency, allowing developers to implement AI applications that are both powerful and cost-effective. The card’s architecture also takes advantage of RISC-V and Digital-In-Memory Computing technologies, bringing substantial improvements in speed and power efficiency.
WAVE6 represents the pinnacle of multi-standard video coding. It supports AV1 encoding, known for its efficient use of bandwidth and high compression quality. Featuring a simple architecture, it boasts a single-clock domain that synchronizes the entropy and video codec engines on the fly. The efficiency of WAVE6 is further enhanced by its power-efficient design, which minimizes consumer energy requirements through effective clock gating. It serves various sectors, including data centers and surveillance systems, operating with a remarkable performance of up to 8K60fps @ 1GHz. The integration of advanced coding techniques ensures a reduced need for external memory, thanks to the proprietary CFrame lossless compression.
The pPLL03F-GF22FDX is an advanced all-digital PLL optimized for low-jitter clocking requirements as seen in performance computing domains. Capable of handling frequencies up to 4GHz, it serves as a reliable clock source for sophisticated computing architectures needing precise timing for ADCs and DACs. Its design emphasizes small size and power efficiency, positioning it as a practical solution for dense and power-conscious SoC designs. This PLL leverages Perceptia's refined second-generation digital technology to deliver uniform performance that remains unaffected by variations in temperature, voltage, or process (PVT) conditions. With capabilities for both integer-N and fractional-N operations, it provides the flexibility needed to meet diverse application requirements and synchronization needs. Its ultra-compact footprint and low power requirements support efficient integration in systems where space and power are constrained. Integrated power regulation allows the pPLL03F to operate with either shared or dedicated power supplies, aligning with the necessities of systems with multiple clock domains. The package includes a comprehensive set of views and design models facilitating seamless incorporation into existing SoC environments, ensuring minimal design disruption and maximizing operational efficiency.
Overview: The MIPI CSI-2 (Camera Serial Interface) Transmitter IP establishes an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that caters to a wide range of imaging solutions for mobile devices. Key Features:  Compliance with MIPI-CSI-2 version 3.0  Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0  Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0  Compatibility with I2C and I3C (SDR, DDR) for CCI interface  Pixel to Byte conversion support from Application layer to LLP layer  Continuous clock behavior in clock lane for D-PHY physical layer  De-skew sequence pattern in Data Lane Module  Lane Distribution Function for distributing packet bytes across N-Lanes  Sync word insertion through PPI command in C-PHY physical layer  Insertion of Filler bytes in LLP layer for packet footer alignment  Setting specific bits in packet header  Defining frame blanking period  Seed selection in scrambler and de-scrambler by Sync word  Support for C-PHY/D-PHY/A-PHY/M-PHY with one PHY layer configuration Target Applications:  Imaging  Surveillance  Gaming  Sensor devices  Internet of Things (IoT)  Wearable devices  Virtual Reality  Augmented Reality  Automotive Systems
The Aries fgOTN processor family is engineered according to the ITU-T G.709.20 fgOTN standard. This line of processors handles a variety of signals, including E1/T1, FE/GE, and STM1/STM4, effectively monitoring and managing alarms and performance metrics. Aries processors excel at fine-grain traffic aggregation, efficiently channeling fgODUflex traffic across OTN lines to support Ethernet, SDH, PDH client services. Their capacity to map signals to fgODUflex containers, which are then multiplexed into higher order OTN signals, demonstrates their versatility and efficiency. By allowing cascaded configurations with other Aries devices or Apodis processors, Aries products optimize traffic routes through OTN infrastructures, positioning them as essential components in optical networking and next-generation access scenarios.
The HDMI Receiver IP from Silicon Library ensures high-quality video and audio input for a range of electronic devices. It supports both HDMI 1.4 and 2.0 standards, allowing for the reception of high-definition video and audio content. This IP is tailored for use in televisions, monitors, and other display systems that require seamless video stream processing. The HDMI Rx IP is equipped with advanced error correction features, ensuring that video and audio signals are accurately received and rendered without loss of quality. It is designed to handle high data rates, making it capable of supporting modern high-resolution video content, including 4K and HDR. Incorporating power-efficient designs, the HDMI Rx takes up minimal space, making it suitable for integration into compact devices. Its compatibility with a wide range of HDMI sources increases its applicability in various consumer and industrial electronics.
The Origin E1 neural engines by Expedera redefine efficiency and customization for low-power AI solutions. Specially crafted for edge devices like home appliances and security cameras, these engines serve ultra-low power applications that demand continuous sensing capabilities. They minimize power consumption to as low as 10-20mW, keeping data secure and eliminating the need for external memory access. The advanced packet-based architecture enhances performance by facilitating parallel layer execution, thereby optimizing resource utilization. Designed to be a perfect fit for dedicated AI functions, Origin E1 is tailored to support specific neural networks efficiently while reducing silicon area and system costs. It supports various neural networks, from CNNs to RNNs, making it versatile for numerous applications. This engine is also one of the most power-efficient in the industry, boasting an impressive 18 TOPS per Watt. Origin E1 also offers a full TVM-based software stack for easy integration and performance optimization across customer platforms. It supports a wide array of data types and networks, ensuring flexibility and sustained power efficiency, averaging 80% utilization. This makes it a reliable choice for OEMs looking for high performance in always-sensing applications, offering a competitive edge in both power efficiency and security.
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 128Gbps and multi lanes and links. The layers speci_ied in PCIE speci_ication Transport, Datalink, Physical layers (digital packet) are implemented in PRIMEXPRESS IP along with PIPE interface logic connecting to PHY and AXI Bridging logic to connect to applications. Features: • Supports PCIE Gen 7 draft Spec. • Supports Pipe 6.X Spec. • PCIE Gen 7.0 Core supports Flit and non – Flit Mode. • Supports X16, X8, X4, X2, X1 Lane Configuration. • AXI MM and Streaming supported. • Supports Gen 1, Gen 2, Gen 3, Gen 4, Gen 5, Gen 6, Gen 7 modes. • Data rate support of 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps, 32 Gbps, 64 Gbps, 128 Gbps. • PAM support when operating at 64Gbps/ 128Gbps. • 8b/10b,128b/130b,1b/1b encoding , decoding support. • Supports EP & RC. • Supports serdes and non – serdes architecture. • Optional DMA support as plugin module. • Support for alternate negotiation protocol. • Lane polarity thru register control. • Lane deskew supported. • Support for L1 states. • L0P Supported. • SKP OS add/removal. • SRIS mode supported. • No equalization support thru configuration. • Deemphasis negotiation support at 5GT/s. • EI inferences in all modes. • PTM, OBFF, MSI, MSIX, Power management and all message format supports.
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 128Gbps and multi lanes and links. The layers speci_ied in PCIE speci_ication Transport, Datalink, Physical layers (digital packet) are implemented in PRIMEXPRESS IP along with PIPE interface logic connecting to PHY and AXI Bridging logic to connect to applications. Features: • Supports PCIE Gen 7 Spec. • Supports Pipe 6.X Spec. • PCIE Gen 7.0 Core supports Flit and non – Flit Mode. • Supports X16, X8, X4, X2, X1 Lane Configura􀆟on. • AXI MM and Streaming supported. • Supports Gen 1, Gen 2, Gen 3, Gen 4, Gen 5, Gen 6, Gen 7 modes. • Data rate support of 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps, 32 Gbps, 64 Gbps, 128 Gbps. • PAM support when operating at 64Gbps/ 128Gbps. • 8b/10b,128b/130b,1b/1b encoding , decoding support. • Supports serdes and non – serdes architecture. • Op􀆟onal DMA support as plugin module. • Support for alternate nego􀆟a􀆟on protocol. • Lane polarity thru register control. • Lane deskew supported. • Support for L1 states. • L0P Supported. • SKP OS add/removal. • SRIS mode supported. • No equalization support thru configura􀆟on. • Deemphasis negotiation support at 5GT/s. • EI inferences in all modes. • PTM, OBFF, MSI, MSIX, Power management and all message format supports.
The ORC3990 SoC is a state-of-the-art solution designed for satellite IoT applications within Totum's DMSSâ„¢ network. This low-power sensor-to-satellite system integrates an RF transceiver, ARM CPUs, memories, and PA to offer seamless IoT connectivity via LEO satellite networks. It boasts an optimized link budget for effective indoor signal coverage, eliminating the need for additional GNSS components. This compact SoC supports industrial temperature ranges and is engineered for a 10+ year battery life using advanced power management.
Archband Labs offers a PDM-to-PCM Converter that excels in translating Pulse Density Modulated (PDM) audio signals into Pulse Code Modulated (PCM) format. This conversion is crucial in audio signal processing where digital formats require conversions for accurate playback or further audio processing. Ideal for modern multimedia systems and portable audio devices, the PDM-to-PCM Converter provides high fidelity in signal conversion, ensuring sound quality is preserved during the process. This IP is highly efficient, making it perfect for applications where power conservation is important, such as battery-powered gadgets and smart wearables. Its compact design provides easy integration into existing systems, facilitating upgrades without significant redesigns. With reliable performance, this converter supports the growing demand for adaptable and high-efficiency audio processing solutions, aiding engineers in achieving cutting-edge audio clarity.
Spec-TRACER is a robust requirements lifecycle management platform tailored for FPGA and ASIC projects. Focusing on facilitating seamless requirements capture, management, and traceability, it ensures that every stage of the design process is aligned with the initial specifications. Its analytical features further enable a comprehensive evaluation of design progress, promoting efficiency and thoroughness throughout the development lifecycle.
MIPI I3C Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs). The MIPI I3C Controller supports in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost of the system. The MIPI I3C Controller IP is fully backward compatible with I2C, allowing designers to future proof their design, and the I3C controller IP operating modes enable systems with several ICs to efficiently connect to all sensors on a single I3C bus. The standard-based ARM® AMBA® Advanced High Performance Bus (AHB) connects the IP to the rest of the SoC offering easy IP integration. MIPI I3C Controller IP is designed to easily integrate into any SoC offering lowest gate count and quickly fit into any Chip development flow.
The PCIe Gen 5 Chiplet from YorChip is designed to meet the demands of high-speed data transfer applications. Aimed at supporting next-generation PCI Express technology, this chiplet offers enhanced bandwidth to satisfy the increasing data rate requirements of modern computing environments. Its architecture supports the integration into larger chiplet systems, facilitating the creation of high-performance, scalable semiconductor solutions. By leveraging cutting-edge technology, the PCIe Gen 5 Chiplet ensures low latency and high efficiency, making it ideal for applications requiring fast and reliable data throughput. Its design is optimized for compatibility with various process nodes, ensuring its adaptability to different manufacturing needs. This flexibility and performance make it a vital component for reducing costs and improving performance in complex electronic systems. Additional technical specifications and unique features enhance its robustness and reliability, ensuring it meets the high standards expected in enterprise-grade computing environments. Overall, this chiplet represents a significant step forward in PCI Express technology, providing a scalable and efficient solution suitable for a wide range of applications.
The Metis AIPU M.2 Accelerator Module is a cutting-edge AI processing unit designed to boost the performance of edge computing tasks. This module integrates seamlessly with innovative applications, offering a robust solution for inference at the edge. It excels in vision AI tasks with its dedicated 512MB LPDDR4x memory, providing the necessary storage for complex tasks. Offering unmatched energy efficiency, the Metis AIPU M.2 module is capable of delivering significant performance gains while maintaining minimal power consumption. At an accessible price point, this module opens up AI processing capabilities for a variety of applications. As an essential component of next-generation vision processing systems, it is ideal for industries seeking to implement AI technologies swiftly and effectively.
The Origin E8 NPUs represent Expedera's cutting-edge solution for environments demanding the utmost in processing power and efficiency. This high-performance core scales its TOPS capacity between 32 and 128 with single-core configurations, addressing complex AI tasks in automotive and data-centric operational settings. The E8’s architecture stands apart due to its capability to handle multiple concurrent tasks without any compromise in performance. This unit adopts Expedera's signature packet-based architecture for optimized parallel execution and resource management, removing the necessity for hardware-specific tweaks. The Origin E8 also supports high input resolutions up to 8K and integrates well across standard and custom neural networks, enhancing its utility in future-forward AI applications. Leveraging a flexible, scalable design, the E8 IP cores make use of an exhaustive software suite to augment AI deployment. Field-proven and already deployed in a multitude of consumer vehicles, Expedera's Origin E8 provides a robust, reliable choice for developers needing optimized AI inference performance, ideally suited for data centers and high-power automobile systems.
The AHB-Lite APB4 Bridge operates as a versatile interconnect bridge that facilitates communication between the AMBA 3 AHB-Lite and AMBA APB protocols. As a soft IP, it is fully parameterized, offering adaptability in various system designs. This bridge enhances the flexibility of integrating peripherals into main system architectures while maintaining low latency and high throughput operations.
The CT25205 Digital IP core is engineered to provide the core building blocks for 10BASE-T1S Ethernet applications, including PMA, PCS, and PLCA Reconciliation Sublayer adherence. Written in Verilog 2005 HDL, it is fully synthesizable with standard cells and FPGA, working cohesively with standard IEEE CSMA/CD Ethernet MAC via MII. The unit supports advanced PLCA features, enabling seamless communication with existing MAC devices. Connectivity is ensured through a standard OPEN Alliance 10BASE-T1S PMD Interface, creating an optimal solution for Zonal Gateway SoCs and MCUs adopting innovative 10BASE-T1S communication.
Panmnesia's CXL 3.1 Switch represents a pivotal innovation in memory expansion and connectivity solutions, bridging the gap between diverse computing resources. This cutting-edge device utilizes CXL 3.1 technology to create a seamless communication link between different system components, such as GPUs, CPUs, and memory expanders. By leveraging such advanced interconnect technology, the switch enables a more flexible and scalable infrastructure, capable of supporting a wide range of devices within a data center environment. The switch's architecture is designed for high scalability, allowing for sophisticated multi-level switching and port-based routing. This flexibility not only enhances scalability across multiple servers but also ensures that various types of computing devices can be easily integrated into a unified system framework. The switch's support for CXL mem, cache, and I/O protocols ensures broad compatibility and optimal performance across a multitude of applications. As part of its development, the switch incorporates advanced features that facilitate memory sharing and resource pooling. This positions it as a key component in the construction of high-performance data centers, enabling significant reductions in operational costs while improving overall system efficiency. With its robust connectivity capabilities, the CXL 3.1 Switch is central to creating AI clusters and accelerating modern AI applications, establishing Panmnesia as a leader in cutting-edge technological solutions for tomorrow's data infrastructure.
A2e Technologies offers a cutting-edge H.264 FPGA Encoder and CODEC that promises the industry's smallest and fastest solution with ultra-low latency. This core is ITAR-compliant and adaptable, capable of delivering a 1080p60 video stream while retaining a minimal footprint. The H.264 core is engineered to adapt to unique pixel depths and resolutions, leveraging a modular design that allows for seamless integration into a variety of FPGA environments. Supporting both I and P frames, this encoder ensures robust video compression with customizable configurations for various applications. The core's flexibility extends to its ability to handle multiple video streams with differing sizes or compression ratios simultaneously. Its fully synchronous design supports resolutions up to 4096 x 4096, illustrating its capacity to manage high-definition sources effectively. The flexibility in design permits its application across FPGAs from numerous manufacturers, including Xilinx and AMD, making it versatile for diverse project requirements. With enhancements like an improved AXI wrapper for better integration and significant reductions in RAM needs for raster-to-macroblock transformations, A2e's H.264 Encoder is equipped for high performance. It supports a variety of encoding styles with a processing rate of 1.5 clocks per pixel and includes comprehensive deliverables such as FPGA-specific netlists and testing environments to ensure a swift and straightforward deployment.
The NaviSoC, a flagship product of ChipCraft, combines a GNSS receiver with an on-chip application processor, providing an all-in-one solution for high-precision navigation and timing applications. This product is designed to meet the rigorous demands of industries such as automotive, UAVs, and smart agriculture. One of its standout features is the ability to support all major global navigation satellite systems, offering versatile functionality for various professional uses. The NaviSoC is tailored for high efficiency, delivering performance that incorporates low power consumption with robust computational capabilities. Specifically tailored for next-generation applications, NaviSoC offers flexibility through its ability to be adapted for different tasks, making it a preferred choice for many industries. It integrates seamlessly into systems requiring precision and reliability, providing developers with a wide array of programmable peripherals and interfaces. The foundational design ethos of the NaviSoC revolves around minimizing power usage while ensuring high precision and accuracy, making it an ideal component for battery-powered and portable devices. Additionally, ChipCraft provides integrated software development tools and navigation firmware, ensuring that clients can capitalize on fast time-to-market for their products. The design of the NaviSoC takes a comprehensive approach, factoring in real-world application requirements such as temperature variation and environmental challenges, thus providing a resilient and adaptable product for diverse uses.
The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI). The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
MAXVY UCIe VIP , a state-of-the-art solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of your UCIe designs. MAXVY UCIe VIP is fully compliant with UCIe Specification version 1.0 and supports all the layers of the UCIe stack, such as FDI, RDI, LogPHY, PCIe, and CXL protocols. MAXVY UCIe VIP is also very user-friendly and flexible, with simple APIs, easy integrations, and configurable parameters. You can easily customize and control the UCIe functionality according to your needs. MAXVY UCIe VIP also provides a rich set of verification capabilities, such as protocol checks, functional coverage, traffic generation, error injection, and debug tools. You can easily monitor, detect, and report any issues or violations in your UCIe designs. MAXVY UCIe VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and supports all leading simulators. With MAXVY UCIe VIP, very flexible for unit level testing, you can achieve faster verification closure and higher quality of your UCIe designs.
The Apodis family of Optical Transport Network processors adheres to ITU-T standards, offering a comprehensive suite for signal termination, processing, and multiplexing. Designed to handle both SONET/SDH and Ethernet client services, these processors map signals to Optical Transport Network (OTN), empowering versatile any-port, any-service configurations. Apodis processors are notable for their capacity to support up to 16 client ports and four 10G OTN line ports, delivering bandwidth scalability up to 40G, crucial for wireless backhaul and fronthaul deployments. With a robust, non-blocking OTN switching fabric, Apodis facilitates seamless client-to-line and line-to-line connections while optimally managing network bandwidth. This adaptability makes the Apodis processors an ideal choice for next-generation access networks and optical infrastructures.
Decoder logic controls numerous targets based on input from the initiator. It determines/decodes which target component will handle the current bus transaction. It also produces error messages for empty addresses in the hierarchy.
The USB PHY offered by Silicon Library Inc. is designed to enable high-speed data transfer and connectivity in various electronic devices. It supports the USB 2.0 protocol, providing seamless integration into existing systems while maintaining compatibility with a wide range of USB-enabled devices. This PHY is crucial for devices requiring reliable and efficient communication with USB peripherals. The USB PHY ensures low-power consumption and high performance, meeting the stringent demands of modern electronic applications. Its design is optimized for space efficiency, making it suitable for integration into compact devices without compromising functionality. With robust error detection and correction capabilities, the USB PHY ensures data integrity and minimizes the risk of data loss during transmission. Its versatility allows it to be utilized across various platforms, enhancing the overall system architecture in consumer electronics, computing devices, and industrial applications.
The Die-to-Die (D2D) Interconnect solution by SkyeChip is a comprehensive technology facilitating high-speed data transfer between dies. Compliant with the UCIe 2.0 specification, it provides high bandwidth and minimal power overhead making it ideal for chiplet-based architectures. This lightweight interconnect supports diverse protocols such as PCIe and CXL, allowing adaptability to numerous communication requirements. It is designed to support major packaging technologies, ensuring flexibility and robustness in post-package yields and supporting loopback tests for integrity assurance.
The MIPITM V-NLM-01 is a Non-Local Means (NLM) image noise reduction core, designed to enhance image quality by minimizing noise while preserving detail. This core is highly configurable, allowing users to customize the search window size and the number of bits per pixel, thereby tailoring the noise reduction process to specific application demands. Specially optimized for HDMI output resolutions of 2048x1080 and frame rates from 30 to 60 fps, the V-NLM-01 utilizes an efficient algorithmic approach to deliver natural and artifact-free images. Its parameterized implementation ensures adaptability across various image processing environments, making it essential for applications where high fidelity image quality is critical. The V-NLM-01 exemplifies VLSI Plus Ltd.'s prowess in developing specialized IP cores that significantly enhance video quality. Its capacity to effectively process high-definition video data makes it suitable for integration in a wide range of digital video platforms, ensuring optimal visual output.
Origin E2 NPUs focus on delivering power and area efficiency, making them ideal for on-device AI applications in smartphones and edge nodes. These processing units support a wide range of neural networks, including video, audio, and text-based applications, all while maintaining impressive performance metrics. The unique packet-based architecture ensures effective performance with minimal latency and eliminates the need for hardware-specific optimizations. The E2 series offers customization options allowing it to fit specific application needs perfectly, with configurations supporting up to 20 TOPS. This flexibility represents significant design advancements that help increase processing efficiency without introducing latency penalties. Expedera's power-efficient design results in NPUs with industry-leading performance at 18 TOPS per Watt. Further augmenting the value of E2 NPUs is their ability to run multiple neural network types efficiently, including LLMs, CNNs, RNNs, and others. The IP is field-proven, deployed in over 10 million consumer devices, reinforcing its reliability and effectiveness in real-world applications. This makes the Origin E2 an excellent choice for companies aiming to enhance AI capabilities while managing power and area constraints effectively.
The UART Serial Communication Controller provides reliable asynchronous communication over serial interfaces, vital for a broad range of applications from embedded systems to consumer electronics. This IP core supports standard UART communication, ensuring dependable data exchange between processors and serial devices. Designed for integration with AMBA interconnects, the controller smoothly interfaces with high-performance processors, supporting versatile communication needs. It allows for effective off-loading of processing tasks, ensuring the host system can devote more resources to its core functionalities or other demanding processes. The controller's design allows it to fit snugly within systems requiring robust, serial data transmission capabilities. With support for multiple baud rates and a variety of configuration options, it lends itself well to diverse applications, from low-power devices to high-speed computing environments. By offering well-documented resources and test simulations, Digital Blocks ensures that this UART controller can be efficiently incorporated into diverse projects, providing adaptability and efficiency in handling serial communication protocols across widely varied system architectures.
The Mixed-Signal CODEC offered by Archband Labs is engineered to enhance the performance of audio and voice devices, handling conversions between analog and digital signals efficiently. Designed to cater to various digital audio interfaces such as PWM, PDM, PCM conversions, I2S, and TDM, it ensures seamless integration into complex audio systems. Well-suited for low-power and high-performance applications, this CODEC is frequently deployed in audio systems across consumer electronics, automotive, and edge computing devices. Its robust design ensures reliable operation within wearables, smart home devices, and advanced home entertainment systems, handling pressing demands for clarity and efficiency in audio signal processing. Engineers benefit from its extensive interfacing capabilities, supporting a spectrum of audio inputs and outputs. The CODEC's compact architecture ensures ease of integration, allowing manufacturers to develop innovative and enhanced audio platforms that meet diverse market needs.
Intilop’s UDP Offload Engine (UOE) is engineered to process UDP packets efficiently, reducing CPU overhead and improving data transfer speeds. This ultra-low latency engine is crucial for applications where rapid data transmission is key, such as multimedia streaming, VoIP, and real-time gaming. The UOE provides robust functionality with its capability of supporting high-throughput processing and multiple concurrent sessions, which is vital for maintaining quality service in data-heavy environments. Its integration into networking systems ensures minimal latency while maximizing data integrity and reliability. Leveraging the UOE contributes to significant performance improvements in network devices, allowing for the handling of vast data volumes without compromising speed or reliability. This IP exemplifies Intilop’s commitment to delivering superior networking solutions that meet modern demands for speed and efficiency.
This high-performance interconnect fabric provides a low-latency connection between numerous bus masters and slaves within AHB-Lite architectures. The switch supports an unlimited number of connections, facilitating scalable and efficient data flow across complex systems. Its ability to handle various data paths concurrently makes it an invaluable asset in high-speed applications.
The Chimera GPNPU by Quadric is a versatile processor specifically designed to enhance machine learning inference tasks on a broad range of devices. It provides a seamless blend of traditional digital signal processing (DSP) and neural processing unit (NPU) capabilities, which allow it to handle complex ML networks alongside conventional C++ code. Designed with a focus on adaptability, the Chimera GPNPU architecture enables easy porting of various models and software application programming, making it a robust solution for rapidly evolving AI technologies. A key feature of the Chimera GPNPU is its scalable design, which extends from 1 to a remarkable 864 TOPs, catering to applications from standard to advanced high-performance requirements. This scalability is coupled with its ability to support a broad range of ML networks, such as classic backbones, vision transformers, and large language models, fulfilling various computational needs across industries. The Chimera GPNPU also excels in automotive applications, including ADAS and ECU systems, due to its ASIL-ready design. The processor's hybrid architecture merges Von Neumann and 2D SIMD matrix capabilities, promoting efficient execution of scalar, vector, and matrix operations. It boasts a deterministic execution pipeline and extensive customization options, including configurable instruction caches and local register memories that optimize memory usage and power efficiency. This design effectively reduces off-chip memory accesses, ensuring high performance while minimizing power consumption.