All IPs > Multimedia
In the rapidly evolving world of semiconductors, multimedia semiconductor IPs play a crucial role in enabling and enhancing digital media experiences across various electronic devices. This category encompasses a broad range of intellectual properties tailored for multimedia processing, from audio and video codecs to graphical interfaces, essential for consumer electronics, mobile devices, broadcasting equipment, and more. As technology advances, so too do the demands for higher performance, better quality, and increased efficiency in multimedia signal processing.
This category is home to subcategories that feature cutting-edge technologies and industry standards in multimedia processing. 2D and 3D rendering IPs lead the visual innovation charge, offering essential tools for developing immersive user interfaces and gaming experiences. Advanced audio interfaces, including ADPCM and WMA IPs, provide high-quality sound reproduction and compression, essential for both professional audio systems and consumer devices.
One of the highlights of the multimedia IP category is video compression technology. Standards like H.264, H.265, and the new H.266 are crucial for streaming services, broadcasting, and digital video recorders, offering solutions that reduce data rates while maintaining video quality. Image processing IPs including JPEG, JPEG 2000, and MPEG standards, ensure efficient image storage and retrieval, vital for digital cameras and web applications.
Additionally, interface IPs such as HDMI, Camera Interface, and MHL provide seamless connectivity, enabling efficient data transfer between devices. With innovations such as AV1 for open-source video coding, and emerging technologies like TICO and MPEG 5 LCEVC, our catalog covers both established and avant-garde solutions for multimedia applications. These semiconductor IPs empower developers and manufacturers to deliver next-generation multimedia experiences, ensuring devices meet the modern consumer's expectations for quality and performance.
Overview: CMOS Image Sensors (CIS) often suffer from base noise, such as Additive White Gaussian Noise (AWGN), which deteriorates image quality in low-light environments. Traditional noise reduction methods include mask filters for still images and temporal noise data accumulation for video streams. However, these methods can lead to ghosting artifacts in sequential images due to inconsistent signal processing. To address this, this IP offers advanced noise reduction techniques and features a specific Anti-ghost Block to minimize ghosting effects. Specifications: ļ¼ Maximum Resolution o Image : 13MP o Video : 13MP@30fps ļ¼ -Input formats : YUV422ā8 bits ļ¼ -Output formats o DVP : YUV422-8 bits o AXI : YUV420, YUV422 ļ¼ -8 bits-Interface o ARMĀ® AMBA APB BUS interface for ISP system control o ARMĀ® AMBA AXI interface for data o Direct connection to sensor stream data (DVP) Features: ļ¼ Base Noise Correction: AWGN reduction for improved image quality ļ¼ Mask Filter: Convolution-based noise reduction for still images ļ¼ Temporal Noise Data Accumulation: Gaussian Distribution-based noise reduction for video streams using 2 frames of images ļ¼ 3D Noise Reduction (3DNR): Sequential image noise reduction with Anti-ghost Block ļ¼ Motion Estimation and Adaptive: Suppresses ghosting artifacts during noise reduction ļ¼ Real-Time Processing: Supports Digital Video Port (DVP) and AXI interfaces for seamless integration ļ¼ Anti-Ghost ļ¼ Real time De-noising output
Overview: Lens distortion is a common issue in cameras, especially with wide-angle or fisheye lenses, causing straight lines to appear curved. Radial distortion, where the image is expanded or reduced radially from the center, is the most prominent type. Failure to correct distortion can lead to issues in digital image analysis. The solution involves mathematically modeling and correcting distortion by estimating parameters that determine the degree of distortion and applying inverse transformations. Automotive systems often require additional image processing features, such as de-warping, for front/rear view cameras. The Lens Distortion Correction H/W IP comprises 3 blocks for coordinate generation, data caching, and interpolation, providing de-warping capabilities for accurate image correction. Specifications: ļ¼ Maximum Resolution: o Image: 8MP (3840x2160) o Video: 8MP @ 60fps ļ¼ Input Formats: YUV422 - 8 bits ļ¼ Output Formats: o AXI: YUV420, YUV422, RGB888 - 8 bits ļ¼ Interface: o ARMĀ® AMBA APB BUS interface for system control o ARMĀ® AMBA AXI interface for data Features: ļ¼ Programmable Window Size and Position ļ¼ Barrel Distortion Correction Support ļ¼ Wide Angle Correction up to 192Ā° ļ¼ De-warping Modes: o Zoom o Tilt o Pan o Rotate o Side-view ļ¼ Programmable Parameters: o Zoom Factor: controls Distance from the Image Plane to the Camera (Sensor)
Overview: The Camera ISP IP is an Image Signal Processing (ISP) IP developed for low-light environments in surveillance and automotive applications, supporting a maximum processing resolution of 13 Mega or 8Mega Pixels (MP) at 60 frames per second (FPS). It offers a configurable ISP pipeline with features such as 18x18 2D/8x6 2D Color Shading Correction, 19-Point Bayer Gamma Correction, Region Color Saturation, Hue, and Delta L Control functions. The ISP IP enhances image quality with optimal low-light Noise/Sharp filters and offers benefits such as low gate size and memory usage through algorithm optimization. The IP is also ARMĀ® AMBA 3 AXI protocol compliant for easy control via an AMBA 3 APB bus interface. Specifications: ļ¼ Maximum Resolution: o Image: 13MP/8MP o Video: 13MP @ 60fps / 8MP @ 60fps ļ¼ Input Formats: Bayer-8, 10, 12, 14 bits ļ¼ Output Formats: o DVP: YUV422, YUV444, RGB888 - 8, 10, 12 bits o AXI: YUV422, YUV444, YUV420, RGB888 - 8, 10, 12 bits ļ¼ Interface: o ARMĀ® AMBA APB BUS interface for ISP system control o ARMĀ® AMBA AXI interface for data o Direct connection to sensor stream data (DVP) o Features: ļ¼ Defective Pixel Correction: On-The-Fly Defective Pixel Correction ļ¼ 14-Bit Bayer Channel Gain Support: Up to x4 / x7.99 with Linear Algebra for Input Pixel Level Adjustment ļ¼ Gb/Gr Unbalance Correction: Maximum Correction Tolerance Gb/Gr Rate of 12.5% ļ¼ 2D Lens-Shading Correction: Supports 18x18 / 8x6 with Normal R/Gb/Gr/B Channel Shading Correction and Color Stain Correction ļ¼ High-Resolution RGB Interpolation: Utilizes ES/Hue-Med/Average/Non-Directional Based Hybrid Type Algorithm ļ¼ Color Correction Matrix: 3x3 Matrix ļ¼ Bayer Gamma Correction: 19 points ļ¼ RGB Gamma Correction: 19 points ļ¼ Color Enhancement: Hue/Sat/ā-L Control for R/G/B/C/M/Y Channels ļ¼ High-Performance Noise Reduction: For Bayer/RGB/YC Domain Noise Reduction ļ¼ High-Resolution Sharpness Control: Multi-Sharp Filter with Individual Sharp Gain Control ļ¼ Auto Exposure: Utilizes 16x16 Luminance Weight Window & Pixel Weighting ļ¼ Auto White Balance: Based on R/G/B Feed-Forward Method ļ¼ Auto Focus: 2-Type 6-Region AF Value Return
Overview: RCCC and RCCB in ISP refer to Red and Blue Color Correction Coefficients, respectively. These coefficients are utilized in Image Signal Processing to enhance red and blue color components for accurate color reproduction and balance. They are essential for color correction and calibration to ensure optimal image quality and color accuracy in photography, video recording, and visual displays. The IP is designed to process RCCC pattern data from sensors, where green and blue pixels are substituted by Clear pixel, resulting in Red or Clear (Monochrome) format after demosaicing. It supports real-time processing with Digital Video Port (DVP) format similar to CIS output. RCCB sensors use Clear pixels instead of Green pixels, enhancing sensitivity and image quality in low-light conditions compared to traditional RGB Bayer sensors. LOTUS converts input from RCCB sensors to a pattern resembling RGB Bayer sensors, providing DVP format interface for real-time processing. Features: ļ¼ Maximum Resolution: 8MP (3840h x 2160v) ļ¼ Maximum Input Frame Rate: 30fps ļ¼ Low Power Consumption ļ¼ RCCC/RCCB Pattern demosaicing
Overview: Human eyes have a wider dynamic range than CMOS image sensors (CIS), leading to differences in how objects are perceived in images or videos. To address this, CIS and IP algorithms have been developed to express a higher range of brightness. High Dynamic Range (HDR) based on Single Exposure has limitations in recreating the Saturation Region, prompting the development of Wide Dynamic Range (WDR) using Multi Exposure images. The IP supports PWL companding mode or Linear mode to perform WDR. It analyzes the full-image histogram for global tone mapping and maximizes visible contrast in local areas for enhanced dynamic range. Specifications: ļ¼ Maximum Resolution: o Image: 13MP o Video: 13MP @ 60fps (Input/Output) ļ¼ Input Formats (Bayer): o HDR Linear Mode: Max raw 28 bits o Companding Mode: Max PWL compressed raw 24 bits ļ¼ Output Formats (Bayer): 14 bits ļ¼ Interface: o ARMĀ® AMBA APB BUS interface for ISP system control o ARMĀ® AMBA AXI interface for data o Video data stream interface Features: ļ¼ Global Tone Mapping based on histogram analysis o Adaptive global tone mapping per Input Images ļ¼ Local Tone Mapping for adaptive contrast enhancement ļ¼ Real-Time WDR Output ļ¼ Low Power Consumption and Small Gate Count ļ¼ 28-bit Sensor Data Interface
Overview: RGB-IR features in ISP enable the capture and processing of Red, Green, Blue, and Infrared (IR) light data in an Image Signal Processing (ISP) system. This functionality enhances image quality by extracting additional information not visible to the human eye in standard RGB images. By integrating IR and RGB data into the demosaic processing pipeline, the ISP can enhance scene analysis, object detection, and image clarity in applications such as surveillance, automotive, and security systems. Features: ļ¼ IR Core - 4Kx1EA: ļ¼ 4K Maximum Resolution: 3840h x 2160v @ 30fps ļ¼ IR Color Correction 3.99x support ļ¼ IR data Full-size output / 1/4x subsample support (Pure IR Pixel data) ļ¼ Only RGB-IR 4x4 pattern support ļ¼ IR data Crop support
The KL730 AI SoC is equipped with a state-of-the-art third-generation reconfigurable NPU architecture, delivering up to 8 TOPS of computational power. This innovative architecture enhances computational efficiency, particularly with the latest CNN networks and transformer applications, while reducing DDR bandwidth demands. The KL730 excels in video processing, offering support for 4K 60FPS output and boasts capabilities like noise reduction, wide dynamic range, and low-light imaging. It is ideal for applications such as intelligent security, autonomous driving, and video conferencing.
Designed for high-performance applications, the Metis AIPU PCIe AI Accelerator Card employs four Metis AI Processing Units to deliver exceptional computational power. With its ability to reach up to 856 TOPS, this card is tailored for demanding vision applications, making it suitable for real-time processing of multi-channel video data. The PCIe form factor ensures easy integration into existing systems, while the customized software platform simplifies the deployment of neural networks for tasks like YOLO object detection. This accelerator card ensures scalability and efficiency, allowing developers to implement AI applications that are both powerful and cost-effective. The cardās architecture also takes advantage of RISC-V and Digital-In-Memory Computing technologies, bringing substantial improvements in speed and power efficiency.
WAVE6 represents the pinnacle of multi-standard video coding. It supports AV1 encoding, known for its efficient use of bandwidth and high compression quality. Featuring a simple architecture, it boasts a single-clock domain that synchronizes the entropy and video codec engines on the fly. The efficiency of WAVE6 is further enhanced by its power-efficient design, which minimizes consumer energy requirements through effective clock gating. It serves various sectors, including data centers and surveillance systems, operating with a remarkable performance of up to 8K60fps @ 1GHz. The integration of advanced coding techniques ensures a reduced need for external memory, thanks to the proprietary CFrame lossless compression.
The HDMI Receiver IP from Silicon Library ensures high-quality video and audio input for a range of electronic devices. It supports both HDMI 1.4 and 2.0 standards, allowing for the reception of high-definition video and audio content. This IP is tailored for use in televisions, monitors, and other display systems that require seamless video stream processing. The HDMI Rx IP is equipped with advanced error correction features, ensuring that video and audio signals are accurately received and rendered without loss of quality. It is designed to handle high data rates, making it capable of supporting modern high-resolution video content, including 4K and HDR. Incorporating power-efficient designs, the HDMI Rx takes up minimal space, making it suitable for integration into compact devices. Its compatibility with a wide range of HDMI sources increases its applicability in various consumer and industrial electronics.
Archband Labs offers a PDM-to-PCM Converter that excels in translating Pulse Density Modulated (PDM) audio signals into Pulse Code Modulated (PCM) format. This conversion is crucial in audio signal processing where digital formats require conversions for accurate playback or further audio processing. Ideal for modern multimedia systems and portable audio devices, the PDM-to-PCM Converter provides high fidelity in signal conversion, ensuring sound quality is preserved during the process. This IP is highly efficient, making it perfect for applications where power conservation is important, such as battery-powered gadgets and smart wearables. Its compact design provides easy integration into existing systems, facilitating upgrades without significant redesigns. With reliable performance, this converter supports the growing demand for adaptable and high-efficiency audio processing solutions, aiding engineers in achieving cutting-edge audio clarity.
The Metis AIPU M.2 Accelerator Module is a cutting-edge AI processing unit designed to boost the performance of edge computing tasks. This module integrates seamlessly with innovative applications, offering a robust solution for inference at the edge. It excels in vision AI tasks with its dedicated 512MB LPDDR4x memory, providing the necessary storage for complex tasks. Offering unmatched energy efficiency, the Metis AIPU M.2 module is capable of delivering significant performance gains while maintaining minimal power consumption. At an accessible price point, this module opens up AI processing capabilities for a variety of applications. As an essential component of next-generation vision processing systems, it is ideal for industries seeking to implement AI technologies swiftly and effectively.
A2e Technologies offers a cutting-edge H.264 FPGA Encoder and CODEC that promises the industry's smallest and fastest solution with ultra-low latency. This core is ITAR-compliant and adaptable, capable of delivering a 1080p60 video stream while retaining a minimal footprint. The H.264 core is engineered to adapt to unique pixel depths and resolutions, leveraging a modular design that allows for seamless integration into a variety of FPGA environments. Supporting both I and P frames, this encoder ensures robust video compression with customizable configurations for various applications. The core's flexibility extends to its ability to handle multiple video streams with differing sizes or compression ratios simultaneously. Its fully synchronous design supports resolutions up to 4096 x 4096, illustrating its capacity to manage high-definition sources effectively. The flexibility in design permits its application across FPGAs from numerous manufacturers, including Xilinx and AMD, making it versatile for diverse project requirements. With enhancements like an improved AXI wrapper for better integration and significant reductions in RAM needs for raster-to-macroblock transformations, A2e's H.264 Encoder is equipped for high performance. It supports a variety of encoding styles with a processing rate of 1.5 clocks per pixel and includes comprehensive deliverables such as FPGA-specific netlists and testing environments to ensure a swift and straightforward deployment.
The AX45MP is engineered as a high-performance processor that supports multicore architecture and advanced data processing capabilities, particularly suitable for applications requiring extensive computational efficiency. Powered by the AndesCore processor line, it capitalizes on a multicore symmetric multiprocessing framework, integrating up to eight cores with robust L2 cache management. The AX45MP incorporates advanced features such as vector processing capabilities and support for MemBoost technology to maximize data throughput. It caters to high-demand applications including machine learning, digital signal processing, and complex algorithmic computations, ensuring data coherence and efficient power usage.
The RT990 TIA is uniquely tailored for optical Cable Television (CATV) applications, where high performance in signal amplification is required. Integrated with a wide dynamic range, the RT990 handles input signals proficiently, converting them efficiently with minimal noise. This feature makes it ideal for maintaining signal clarity over long distances, essential in the delivery of high-quality television content. With its high linear gain and advanced automatic gain control, the RT990 ensures broadcast reliability even in fluctuating signal environments.
Silicon Library provides the LVDS/OpenLDI solution to cater to the needs of systems requiring reliable data communication. LVDS, or Low Voltage Differential Signaling, is a standardized method for transmitting high-speed digital data with minimum power consumption and radiation. This technology is utilized in a broad range of applications like LCD screens and point-to-point links because of its fast data transmission capabilities and ability to support significant distances without compromising signal integrity. The OpenLDI variant extends these benefits further, supporting broader implementation such as industrial and consumer displays. With power-efficient designs, this LVDS/OpenLDI IP ensures enhanced performance with minimal power usage. Its design facilitates integration into systems where compact form factors and robust performance are vital, making it a staple in many high-performance display environments and communications systems.
The MIPITM V-NLM-01 is a Non-Local Means (NLM) image noise reduction core, designed to enhance image quality by minimizing noise while preserving detail. This core is highly configurable, allowing users to customize the search window size and the number of bits per pixel, thereby tailoring the noise reduction process to specific application demands. Specially optimized for HDMI output resolutions of 2048x1080 and frame rates from 30 to 60 fps, the V-NLM-01 utilizes an efficient algorithmic approach to deliver natural and artifact-free images. Its parameterized implementation ensures adaptability across various image processing environments, making it essential for applications where high fidelity image quality is critical. The V-NLM-01 exemplifies VLSI Plus Ltd.'s prowess in developing specialized IP cores that significantly enhance video quality. Its capacity to effectively process high-definition video data makes it suitable for integration in a wide range of digital video platforms, ensuring optimal visual output.
The V-By-One HS technology from Silicon Library is aimed at providing a robust solution for high-speed video signal transmission over extended distances. It is used primarily in display technologies where the need for high data rates and minimal cabling is essential. V-By-One HS supports ultra-high-definition video and is designed to reduce the complexity of cabling in large displays and panels, making it a preferred choice in industries that manufacture televisions and digital signage displays. This technology enhances the quality of video signaling by ensuring smooth and uninterrupted data flow, which is vital for premium screen displays. The compact design of V-By-One HS lowers the overall system cost and footprint, while also cutting down on power consumption, essential for meeting the latest environmental and performance standards. This makes it an ideal solution for advanced display technologies requiring efficient data transmission with minimal hardware.
The Chimera GPNPU by Quadric is a versatile processor specifically designed to enhance machine learning inference tasks on a broad range of devices. It provides a seamless blend of traditional digital signal processing (DSP) and neural processing unit (NPU) capabilities, which allow it to handle complex ML networks alongside conventional C++ code. Designed with a focus on adaptability, the Chimera GPNPU architecture enables easy porting of various models and software application programming, making it a robust solution for rapidly evolving AI technologies. A key feature of the Chimera GPNPU is its scalable design, which extends from 1 to a remarkable 864 TOPs, catering to applications from standard to advanced high-performance requirements. This scalability is coupled with its ability to support a broad range of ML networks, such as classic backbones, vision transformers, and large language models, fulfilling various computational needs across industries. The Chimera GPNPU also excels in automotive applications, including ADAS and ECU systems, due to its ASIL-ready design. The processor's hybrid architecture merges Von Neumann and 2D SIMD matrix capabilities, promoting efficient execution of scalar, vector, and matrix operations. It boasts a deterministic execution pipeline and extensive customization options, including configurable instruction caches and local register memories that optimize memory usage and power efficiency. This design effectively reduces off-chip memory accesses, ensuring high performance while minimizing power consumption.
The KL630 AI SoC embodies next-generation AI chip technology with a pioneering NPU architecture. It uniquely supports Int4 precision and transformer networks, offering superb computational efficiency combined with low power consumption. Utilizing an ARM Cortex A5 CPU, it supports a range of AI frameworks and is built to handle scenarios from smart security to automotives, providing robust capability in both high and low light conditions.
The xcore.ai platform by XMOS Semiconductor is a sophisticated and cost-effective solution aimed specifically at intelligent IoT applications. Harnessing a unique multi-threaded micro-architecture, xcore.ai provides superior low latency and highly predictable performance, tailored for diverse industrial needs. It is equipped with 16 logical cores divided across two multi-threaded processing tiles. These tiles come enhanced with 512 kB of SRAM and a vector unit supporting both integer and floating-point operations, allowing it to process both simple and complex computational demands efficiently. A key feature of the xcore.ai platform is its powerful interprocessor communication infrastructure, which enables seamless high-speed communication between processors, facilitating ultimate scalability across multiple systems on a chip. Within this homogeneous environment, developers can comfortably integrate DSP, AI/ML, control, and I/O functionalities, allowing the device to adapt to specific application requirements efficiently. Moreover, the software-defined architecture allows optimal configuration, reducing power consumption and achieving cost-effective intelligent solutions. The xcore.ai platform shows impressive DSP capabilities, thanks to its scalar pipeline that achieves up to 32-bit floating-point operations and peak performance rates of up to 1600 MFLOPS. AI/ML capabilities are also robust, with support for various bit vector operations, making the platform a strong contender for AI applications requiring homogeneous computing environments and exceptional operator integration.
The DisplayPort and Embedded DisplayPort (eDP) IP offered by Silicon Library deliver advanced video interface solutions, providing high-resolution video signal transmission. Supporting the latest DisplayPort standards, this IP achieves efficient data transfer suitable for both standalone and embedded systems. Applications benefiting from this IP include monitors, laptops, and mobile devices where high-quality display performance is crucial. The DisplayPort/eDP IP supports high-definition audio and video, ensuring excellent media streaming and integration with contemporary display technologies. Its design is optimized for power efficiency, making it a suitable choice for portable devices. The IP includes support for high dynamic range video, which improves image clarity and contrast, catering to advanced multimedia applications. Moreover, its flexible design allows it to seamlessly integrate with various system architectures, providing a robust solution for next-generation display interfaces.
The eSi-Comms solution provides a highly parameterisable and configurable suite for communication ASIC designs. This comprehensive collection includes OFDM-based modem and DFE IPs supporting a vast array of contemporary air interface standards such as 4G, 5G, Wi-Fi, and DVB among others. It offers robust and efficient solutions for modulation, equalization, and error correction using advanced digital signal processing algorithms. With its capabilities specific to synchronization and demodulation across multiple standards, it equips systems for optimal data flow management. The adaptable DFE features support precision in digital frequency conversion and other enhancements, fortifying both the transmitting and receiving ends of communication systems. This IP empowers wireless sensors, remote metering, and cellular devices, ensuring seamless integration into a diverse range of communication applications.
Building on its predecessor, the WAVE5 series offers robust multi-standard video encoding capabilities with an established reputation within media and entertainment sectors. WAVE5 is versatile, boasting formats like HEVC and AVC, and delivers outstanding performance, with outputs like 4K240fps at 1GHz. It has been fine-tuned to handle complex multi-instance operations by efficiently managing data transfer and conversion tasks. Its ability to maintain high visual fidelity while offering low installation costs makes it a strategic choice for multiple application fields such as automotive and mobile entertainment. The use of secondary AXI ports and a fully integrated rotation and scaling mechanic add to its versatility.
The G-Series Controller from MEMTECH is conceived for graphics-heavy computing environments, balancing high bandwidth and low power demands. This controller supports GDDR6 devices at speeds reaching up to 18 Gbps. It incorporates dual-channel support, advanced scheduling, and error detection ensuring robust data throughput with minimal latency. Suitable for applications such as gaming, video processing, and AI, the G-Series Controller facilitates efficient integration and supports various power-saving features.
The DSC Decoder by Trilinear Technologies decodes Display Stream Compression data to allow for efficient and high-fidelity display output. It represents state-of-the-art technology in handling compressed video streams, ensuring that the data is accurately rendered for high-end applications. Specially designed to cater to modern digital displays, the DSC Decoder supports varying data rates and formats, thus enhancing the versatility of any multimedia framework it is integrated into. It achieves superior performance with minimal resource usage, providing an optimal balance between power and processing capabilities. Innovation and meticulous engineering converge in this decoder, evidencing Trilinear's commitment to delivering robust solutions. Parameters such as signal accuracy and systemic reliability are prioritized, making it well-suited for high-definition broadcasting and real-time video applications where performance and quality are critical benchmarks.
Engineered for high-efficiency data compression, the DSC Encoder from Trilinear Technologies enables the effective encoding of Display Stream Compression data, critical for optimal video output without sacrificing quality. This encoder's design focuses on achieving maximal compression while preserving the integrity of the source material, making it ideal for cutting-edge display technologies. Efficiency is its standout feature, allowing it to effectively handle a wide range of encoding tasks without significant power draw, which is increasingly important in portable and battery-powered devices. The DSC Encoder supports numerous formats and resolutions, offering excellent flexibility for integration into existing digital video systems. With a focus on precision and performance, this encoder meets the high demands of present-day display environments. Trilinear Technologies ensures that each encoder maintains consistency and reliability, adhering to industry standards that keep it competitive. It is an exemplary product for various high-definition multimedia roles, from consumer electronics to professional AV installations.
Silicon Library's HDMI Transmitter IP is engineered to provide clear and uninterrupted video and audio transmission. It supports both HDMI 1.4 and 2.0 versions, ensuring high-definition video quality and advanced audio formats. This transmitter IP is suitable for a wide range of applications, from consumer electronics to professional audiovisual equipment. The HDMI Tx IP features robust protection against interference and ensures compatibility across different HDMI devices. It incorporates advanced features such as support for 4K video resolution and high dynamic range (HDR), enhancing the viewing experience with vibrant colors and sharp images. Designed with power efficiency in mind, this HDMI Tx IP minimizes power consumption while delivering superior performance. Its compact design allows for integration into various devices, making it ideal for space-constrained applications in modern smart devices.
The Titanium Ti375 FPGA from Efinix boasts a high-density, low-power configuration, ideal for numerous advanced computing applications. Built on the well-regarded Quantum compute fabric, this FPGA integrates a robust set of features including a hardened RISC-V block, SerDes transceiver, and LPDDR4 DRAM controller, enhancing its versatility in challenging environments. The Ti375 model is designed with an intuitive I/O interface, allowing seamless communication and data handling. Its innovative architecture ensures minimal power consumption without compromising on processing speed, making it highly suitable for portable and edge devices. The inclusion of MIPI D-PHY further expands its applications in image processing and high-speed data transmission tasks. This FPGA is aligned with current market demands, emphasizing efficiency and scalability. Its architecture allows for diverse design challenges, supporting applications that transcend traditional boundaries. Efinixās commitment to delivering sophisticated yet energy-efficient solutions is embodied in the Titanium Ti375, enabling new possibilities in the realm of computing.
The JPEG Codec/CODA/BODA platform stands out in multi-standard JPEG and video encoding/decoding technologies, serving critical roles in mobile and automotive systems, as well as medical imaging. It adheres to the ISO/IEC 10918-1 JPEG standard, providing flexible image and video management through customizable encoders and decoders. The architecture is designed to manage a wide variety of colors and formats, ensuring clarity and quality across applications. The engine's speed is impressive, showing prowess in managing up to 290M pixels per second, for both encoding and decoding routines. This efficiency and comprehensive format support make it an ideal solution for high-demand imaging fields.
Silicon Library's MIPI IP is crafted to meet the stringent requirements of modern mobile and multimedia applications. It includes D-PHY transmitter and receiver components, which are essential for high-speed data communication between components like cameras, displays, and processors within portable devices. The MIPI D-PHY IP is compliant with the latest MIPI standards, ensuring smooth data flow and reducing electromagnetic interference, critical for maintaining data integrity. Its applications span a range of sectors, from mobile phones to tablets and automotive systems, where high-performance data transmission is essential. This IP's design emphasizes low power consumption and efficient data handling, making it ideal for use in energy-sensitive devices. Furthermore, it supports a variety of video resolutions and data rates, providing flexibility in designing multimedia devices.
With its ability to encode data streams to comply with the VESA DSC 1.2b standard, the Ultra-High Throughput VESA DSC 1.2b Encoder IP core delivers high quality video compression with visually lossless performance. This core's standalone functionality enables swift integration into systems, whether for FPGA or ASIC designs, with support for 4:4:4, 4:2:2, and 4:2:0 chroma formats. Adaptability across varying bit depths from 8 to 16 bits ensures comprehensive color support for sophisticated video applications. This encoder uses internal memory for efficient data handling, avoiding the need for external resources, which simplifies system design and reduces latency. Its scalable architecture supports a parallel processing model allowing configurations that match specific throughput requirements, further optimizing both the device's speed and memory footprint. Designed for ease-of-use and high efficiency, the UHT-DSC-E IP provides visually lossless compression suitable for an array of applications such as mobile displays, tablets, and high-definition televisions. Its robust design ensures seamless operation without data bottlenecks, maintaining smooth integration within complex systems for enhanced user experiences.
The JPEG Encoder from section5 is engineered to cater to real-time image compression demands, adhering to the baseline JPEG standard (ITU T.81) and supports Motion JPEG. This IP is capable of handling up to 12 bits of depth, although it defaults to 8 bits, which ensures high-quality image processing with super low latency, critical for applications in rolling shutter cameras. The encoder is designed to be fully bit and cycle accurate, with available simulation models to aid in verifying compliance. One highlight of this JPEG Encoder IP is its minimal hardware requirements, needing no external RAM beyond an FPGA and an Ethernet PHY. This low power consumption IP benefits from clock synchronous, distributed operations. Available in two versions ā the L1 variant for monochrome or YUV420 multiplexed pipelines and the L2 variant supporting simultaneous high-quality YUV422 encodings, it's optimized for varying standards such as MJPEG. The IP supports seamless integration into existing systems, making use of real-time streaming solutions over UDP/Ethernet, aligning with RFC2435 standards. The encoder can be applied across a variety of performance needs, adapted to different FPGA families, all the while maintaining energy efficiency and high-performance throughput for applications like machine vision and video transmission.
The Trion FPGA family by Efinix addresses the dynamic needs of edge computing and IoT applications. These devices range from 4K to 120K logic elements, balancing computational capability with efficient power usage for a wide range of general-purpose applications. Trion FPGAs are designed to empower edge devices with rapid processing capabilities and flexible interfacing. They support a diverse array of use-cases, from industrial automation systems to consumable electronics requiring enhanced connectivity and real-time data processing. Offering a pragmatic solution for designers, Trion FPGAs integrate seamlessly into existing systems, facilitating swift development and deployment. They provide unparalleled adaptability to meet the intricate demands of modern technological environments, thereby enabling innovative edge and IoT solutions to flourish.
ASRC-Lite is a streamlined audio sample rate converter designed for applications requiring efficient and precise audio data conversion. This versatile solution is engineered to handle multiple audio sample rates, effectively converting audio signals with minimal latency and high sound quality. The ASRC-Lite is ideal for systems where performance and resource efficiency are paramount, embodying Coreworks' commitment to delivering high-quality audio processing capabilities. With a focus on flexibility and integration, the ASRC-Lite can be seamlessly incorporated into a variety of audio applications, ranging from consumer electronics to professional audio equipment. The module is equipped with dynamic features that ensure precise sample rate conversion across different audio formats, supporting optimal performance in real-time environments. As audio systems become increasingly complex, the ASRC-Lite provides a reliable and scalable solution that addresses the evolving needs of audio signal processing. Building on Coreworks' extensive expertise in digital audio processing, the ASRC-Lite exemplifies the marriage of cutting-edge technology and user-oriented design. By offering robust support for low-latency audio conversion, it enables developers to create sophisticated audio solutions that maintain the integrity and clarity of the original sound. This audio sample rate converter is a testament to Coreworksā innovation in developing functionally advanced yet resource-conscious IP solutions.
Creonic's Turbo Encoders/Decoders offer advanced error correction features for modern digital communication systems. Originating from iterative decoding theory, the turbo codes provided are known for their efficiency and performance close to Shannonās limit. These encoders and decoders come in various configurations to suit both existing and emergent network standards such as DVB-RCS2 and 4G LTE. Engineered with scalability in mind, Creonic's Turbo solutions support a wide range of data rates and frame sizes, making them a flexible choice for operators targeting satellite or terrestrial networks. Their modular design ensures easy integration and adaptability across various digital platforms and communication technologies. The products maintain high data integrity, enabling reliable data delivery even in high-noise environments. Creonic ensures that each turbo code solution is compliant with international standards, providing a seamless interoperability experience across diverse network architectures.
Creonic delivers advanced Polar Encoders/Decoders that offer high flexibility and efficiency for cutting-edge communications. The companyās Polar solutions capitalize on polar code technology, which is recognized for its channel capacity achievement capabilities in the field of communications. These encoders and decoders are particularly input for Ultra Reliable Low Latency Communications (URLLC), with applications extending to 5G networks and beyond. Creonicās solution supports various coding rates and code lengths, providing a robust framework for creating customized configurations based on customer specifications. Compatibility with major FPGA platforms allows for seamless integration into existing systems, ensuring optimal performance and scalability across numerous applications. The Polar Encoder/Decoder IP is designed to handle both short and long frames, providing enhanced reliability and ensuring data is efficiently and accurately transmitted over different communication channels.
Designed for environments that demand rapid and large-scale data processing, the Ultra-High Throughput 8/10/12-bit JPEG Decoder supports efficient decoding of high-resolution images and video streams. Handling up to 32 samples per clock cycle, this IP core accommodates 4:4:4, 4:2:2, 4:2:0, and grayscale data formats, with depths ranging from 8-bit to 12-bit per sample. The decoder is engineered for both excellence and speed, enabled through scalable architecture. The UHT-JPEG-D supports seamless integration with a variety of processors without the need for additional CPU or GPU power. This efficiency makes the core ideal for implementing standalone solutions or integrating into larger, more complex systems. It displays compatibility across standard JPEG byte streams while ensuring resilient performance in high-demand tasks such as Ultra HD video playback. The decoder utilizes a parallel processing architecture, which effectively balances data handling and processing speeds. By maintaining synchronization across decoding units, it ensures uniform performance even under a diverse set of processing conditions. This design choice not only enhances throughput but also simplifies the logic, making this IP an attractive choice for both developers and system integrators alike.
ZIA Stereo Vision (SV) represents DMP's cutting-edge depth sensing solution, engineered to offer high-precision stereo vision for various AI applications. It's designed to process stereo images for advanced depth mapping, utilizing 4K inputs to facilitate distance estimation via stereo matching algorithms like Semi-Global Matching (SGM). Through this technique, ZIA SV ensures that distance information is extracted accurately, a critical capability for applications like autonomous mobile robots or advanced imaging systems. Pre- and post-processing optimization provides the ZIA SV with the tools necessary to refine depth estimates and ensure high accuracy. It supports 8-bit greyscale inputs and outputs a disparity map with an accuracy up to 0.8%, provided by advanced filtering techniques that enhance precision while maintaining a compact form factor crucial in embedded systems. This IP core integrates smoothly into systems requiring reliable depth measurement, utilizing efficient AMBA AXI interfaces for easy integration into diverse applications. With capabilities to support a wide range of hardware platforms and favorable performance-to-size ratios, the ZIA Stereo Vision core embodies DMP's philosophy of compact, high-performance solutions for smarter decision-making in machine vision applications.
Creonic's LDPC Encoders/Decoders are engineered to deliver high throughput and low latency for communications and data applications. The exceptional performance of these encoders and decoders ensures that they are ideally suited for applications such as satellite communications, broadband wireless, and high-speed networking. Creonic provides a comprehensive range of LDPC solutions that can be customized to match various standards, including DVB-S2X, 5G NR, IEEE, and CCSDS. Each LDPC solution is robustly engineered, offering maximum flexibility to adapt to different code rates and frame sizes. These cores are implemented to ensure compatibility with diverse FPGA platforms like Xilinx and Intel. Customers benefit from a solid framework that integrates efficient encoding and decoding mechanisms, ensuring reliable data transfer across challenging communication environments. The LDPC products stand out for their superior error correction capabilities, which help in mitigating the adverse effects of signal degradation. Creonic's solutions target both existing and emerging communications standards, ensuring future-proof reliability and performance enhancement.
The Ultra-High Throughput H.264 Encoder for Intra Frames is built for high-efficiency video encoding, enabling high-quality video processing in environments focused on speed and picture fidelity. It provides Baseline, Main, and High profile support tailored for Intra frame (IDR) encoding, managing 4:2:0 and 4:2:2 chroma formats with a scalable architecture. By incorporating parallel processing engines, the encoder enhances video quality using deep sub-frame bitrate regulation without substantial silicon footprint increase. The design allows for fully autonomous operation independent of external CPU or GPU reliance, supporting seamless deployment in diverse applications ranging from professional broadcasting to medical imaging. This IP core is intuitive to integrate, with flexible interfaces for streaming video I/O. Its compact design and resource efficiency make it suitable for systems targeting real-time performance under strict bandwidth limits, paving the way for optimized multimedia experiences across industry verticals.
The HEVC/H.265 Encoder stands out in Allegro DVT's lineup for its superior performance in compressing high-quality video streams. Supporting the HEVC standard, this encoder is built to provide optimal balance between compression efficiency and video quality, making it indispensable for applications where bandwidth and storage constraints are critical. Key to its design is the ability to deliver high-resolution outputs, up to 4K and beyond, while maintaining striking visual fidelity. This is achieved through advanced encoding techniques that reduce data rates without forfeiting image quality, which is crucial for live-streaming and broadcast markets where maintaining high fidelity is a priority. Additionally, the encoder's architecture allows for real-time processing, catering to applications that demand swift frame processing and minimal latency. Beyond its exceptional encoding capabilities, the HEVC/H.265 Encoder is crafted for seamless integration into a variety of hardware solutions. Whether for digital broadcasting, video surveillance, or cloud video services, its adaptability ensures it fits diverse technical needs. Its energy-efficient design further enhances its suitability for portable and embedded platforms, ensuring prolonged operation without the penalty of excessive power consumption.
Vantablack S-VIS is a revolutionary space-qualified coating renowned for its unparalleled ability to suppress stray light. This is crucial for enhancing the performance and precision of optical instruments used in space applications. With its spectrally flat absorption capabilities extending from the UV range to the near-millimeter (THz) range, Vantablack S-VIS significantly improves light absorption, reducing interference and enhancing image quality. The coating has demonstrated exceptional performance in harsh environments, thriving under the intensity of solar, lunar, and terrestrial light in a zero-gravity context. Its deployment has resulted in lighter and smaller calibration systems and baffles, which is critical for space-bound equipment where size and weight are significant constraints. These coatings enhance emissivity across the IR spectrum, making them ideal for blackbody calibration in IR cameras and other sensitive optical systems. Since its initial deployment in low Earth orbit, the Vantablack S-VIS has amassed a significant track record of success in space missions. It possesses excellent thermal stability and is resistant to radiation and extreme vibrational forces, ensuring reliability and longevity in challenging space conditions. These attributes, coupled with its lightweight nature, make Vantablack S-VIS an optimal choice for advanced space imaging technologies.
ISPido is a robust and fully configurable Image Signal Processing (ISP) pipeline designed for high-end image processing needs. It is implemented in RTL and utilizes the AXI4-LITE protocol for flexibility. The pipeline is equipped with comprehensive features including defective pixel correction, color filter array interpolation, and color space conversion. It supports resolutions up to 7680Ć7680 and complies with AMBA AXI4 standards, addressing modern image processing challenges efficiently. This ISP handles inputs of 8, 10, or 12 bits depth, making it highly adaptable to different processing requirements. It features modules for statistics collection, auto-white balance, gamma correction, and high dynamic range (HDR) support. These enhancements enable users to achieve precise and accurate image quality with maximum efficiency. Furthermore, the ISPido pipeline supports YUV color conversion and chroma subsampling, ensuring compatibility with various output formats like 4:2:2 and 4:2:0. Its design ensures seamless integration into existing systems, optimizing resources while offering high-quality image output.
Alma Technologies' Main Profile H.264 Encoder provides advanced video encoding capabilities supporting ITU-T H.264 specifications within the main profile, including Baseline and High profiles. This versatile encoder facilitates real-time encoding for both single and multi-channel 8-bit 4:2:0 video streams, suitable for complex broadcasting and professional video applications. Not only confined to a single configuration, this IP core supports diverse formats, increasing adaptability across an array of applications requiring robust visual fidelity and compression efficiency. Its architecture supports CABAC entropy coding and motion estimation algorithms, enhancing the encoder's aptitude for dynamic video environments. Offering a blend of high throughput and simplified integration, the core suits use in FPGA and ASIC designs where operational efficiency and ease of use are paramount. The Main Profile H.264 Encoder, with its advanced feature set, addresses modern challenges of video data management with effective results, delivering crisp and consistent performance every time.
The Baseline Profile H.264 Encoder from Alma Technologies is engineered for efficient handling of high-definition video content, complying with the ITU-T H.264 Constrained Baseline Profile. This IP core offers extensive support for multiple encoding configurations, including Intra-only, Light Motion, and Full Motion Estimation prediction functions, prioritizing balanced performance and bandwidth management. This encoder is available for both FPGA and ASIC designs, adapting seamlessly to various data formats such as planar, interleaved, or macroblock scans. It outputs a standard-compliant Annex B NAL byte stream, ensuring compatibility with a broad array of H.264 compliant decoders, thus preserving video integrity and quality. By managing video data with minimal host intervention and standalone operational capabilities, it reduces system complexity and overheads, making it an ideal choice for applications that demand high video quality without extensive computational resources. Its implementation provides reliability and ease of integration, ensuring a smooth, consistent performance across diverse platform requirements.
Arasan's MIPI DSI-2 Transmitter IP provides a high-performance, scalable solution for enhancing display interfaces in mobile applications. Compliant with the latest MIPI DSI standards, this IP enables efficient data transmission between processors and display panels, suited for high-resolution, power-sensitive environments. It's geared to support the stringent demands of todayās advanced display technologies, offering flexibility across multiple DSI configurations while ensuring minimal power draw. The DSI-2 Transmitter IP supports advanced features such as multiple data lane configurations, seamless color depth adjustments, and adaptive resolution management, which are crucial for achieving stellar visual outputs in mobile and embedded devices. Built with an emphasis on signal integrity and performance, it supports a wide range of data rates, making it versatile for different display panel technologies. With a focus on compliance and interoperability, the DSI-2 Transmitter assures seamless integration with various D-PHY configurations, facilitating efficient design rollouts and reducing time to market. Its architecture supports error correction and synchronization, ensuring data integrity and reliability, a crucial aspect when dealing with high resolutions and demanding visualization requirements.
The SL-400X Mobile TV Integrated Receiver is designed for next-generation mobile digital television applications, offering a fully integrated solution that combines advanced demodulation and reception capabilities. Tailored for mobile environments, this receiver ensures seamless and reliable TV reception for portable devices under varying signal conditions. Equipped with robust software-defined processing capabilities, the SL-400X supports dynamic signal adaptation, enabling uninterrupted viewing experiences even while on the move. This makes it particularly beneficial for devices and systems that operate in fluctuating signal environments, ensuring content delivery with high quality and consistency. The compact nature of the SL-400X allows it to be embedded into various consumer electronics, providing a lightweight solution that does not compromise on performance. This integration ensures that manufacturers can offer enhanced mobile entertainment options, meeting the increasing demand for on-the-go content accessibility.
The Ultra-High Throughput 8/10/12-bit JPEG Encoder offers a high performance solution for advanced image processing tasks, ideal for high-definition demand environments. It supports Baseline and Extended profiles, providing encoding options for 8-bit, 10-bit, and 12-bit data in 4:4:4, 4:2:2, 4:2:0, and grayscale formats. Notably, it can manage up to 32 samples per clock cycle, allowing for swift and efficient processing without compromising image quality. The core is standalone, requiring no external CPU or GPU for operations, making it an efficient choice for resource-constrained designs. Its architecture supports intricate workload management, splitting input data across multiple compression engines, which optimizes throughput while maintaining a small silicon footprint. This IP core demonstrates robust compliance with the ITU-T T.81 specification, ensuring compatibility and reliability across various uses. Ideal for applications needing rapid image compression, such as video streaming or storage systems, this encoder can fit into low-cost FPGA devices while delivering levels of performance typically reserved for higher-end solutions. Its ease of integration and compatibility with various types of on-chip and off-chip memory underscore its versatility in a range of deployment scenarios.
Alma Technologies' High Profiles H.264 Encoder serves as a sophisticated toolkit for video encoding, meeting high-tier demands with support for high 10, high 4:2:2, and high 4:4:4 profiles. This encoder flexibly manages video streams in both 4:2:0 and 4:2:2 formats, delivering premium image fidelity and compression efficiency for professional-grade applications. This core is crafted for compatibility with modern digital workflows, capable of handling 8-, 10-, and 12-bit data per component. The encoder is meticulously verified to ensure it caters to both conservative and intensive encoding challenges, adjusting seamlessly across a diversity of use cases from professional media to specialized industrial systems. With independent and adaptable operational capabilities, it operates without host intervention, boasting a simplified integration process. Supporting advanced motion estimation and prediction features, the High Profiles H.264 Encoder distinctly suits tasks requiring resilient performance under demanding conditions, embodying a cornerstone of modern video encoding technology.