All IPs > Multimedia > MPEG / MPEG2
The MPEG and MPEG2 categories of semiconductor IPs are essential for managing digital video compression and playback in a variety of multimedia applications. These IPs are designed to facilitate efficient encoding, decoding, and transmission of video content, leveraging the capabilities of the well-established MPEG and MPEG2 standards. The technology serves as a backbone for many digital video products, enabling manufacturers to deliver high-quality video experiences in consumer electronics, broadcasting, and streaming services.
MPEG, which stands for Moving Picture Experts Group, encompasses a suite of standards for audio and video compression and transmission. MPEG semiconductor IPs support a wide range of functions, from basic video compression to more complex tasks like multiplexing video streams. MPEG2, an evolution of the original MPEG standard, further enhances video and audio quality and is particularly noted for its use in DVDs and digital television broadcasting. The IPs in this category are optimized for high-efficiency encoding processes, ensuring smoother playback and better bandwidth utilization.
These semiconductor IPs are crucial as they empower developers to create devices capable of handling intense video processing tasks with lower power requirements and greater speed. Companies in consumer electronics, such as TV manufacturers, set-top box designers, and digital video recorders, commonly utilize MPEG and MPEG2 IPs. Moreover, the broadcasting sector benefits significantly from their use in creating and managing content delving into formats suitable for various transmission channels.
In addition to consumer electronics and broadcasting, streaming services use MPEG and MPEG2 IPs to manage and deliver clear, sharp videos over the internet. By employing these semiconductor IPs, developers ensure compatibility with a broad range of devices and network conditions, providing flexible solutions that meet the dynamic needs of modern multimedia consumption. Whether the application demands real-time video processing or offline content delivery, MPEG and MPEG2 semiconductor IPs offer robust solutions that maintain the integrity and quality of visual content across multiple platforms.
The JPEG Encoder for Image Compression is designed to deliver efficient lossy compression for various imaging applications. This encoder is compliant with the Baseline JPEG standard (ITU T.81), ensuring a balance between compression efficiency and image quality. It supports pixel depths of up to 12 bits, although 8 bits is the default setting. The encoder provides super low latency, making it ideal for rolling shutter cameras, and is available in multiple configurations to suit different application needs. This encoder is particularly adaptable for multimedia applications requiring high-speed processing, including motion JPEG, thanks to its dual-pipe design that allows simultaneous encoding for formats like YUV422. This setup supports resolutions such as 1280x720 at 60 fps with a pixel clock of 100 MHz, although platform-specific optimizations can increase speed. The encoder operates without external RAM, relying only on FPGA and Ethernet PHY, which not only reduces power consumption but also simplifies hardware requirements. Additionally, the JPEG Encoder is verified extensively against standard compliance through detailed simulation models that ensure both bit and cycle accuracy. The encoder can be implemented in various SoCs and integrates smoothly with existing systems, thanks to its adaptable architecture that supports various network streaming standards and embedded applications.
StreamDSP's JPEG2000 Video Compression Solution provides advanced video and image compression capabilities necessary for a host of professional applications where image quality is paramount. With support for both lossy and lossless compression in a single codestream, this solution balances between achieving the highest image quality and maximizing compression efficiency. It is ideal for applications ranging from digital cinema and medical imaging to remote sensing and scientific research, where maintaining image integrity is crucial. The solution is implemented within FPGA environments, leveraging the high-performance processing capabilities without the need for external processors. This flexibility allows for substantial customization, meeting the varied demands of industries that rely on high-quality image processing. With a range of adaptable features and configurable options, the JPEG2000 Video Compression Solution offers both flexibility and robustness in meeting the needs of complex image processing tasks.
The IPMX Core from Nextera offers an open approach to AV over IP, building on the ST 2110 standard with NMOS control layers. IPMX simplifies the deployment of interoperable AV solutions by providing functionalities necessary for professional AV setups. This core supports compressed video transmission over 1G with low latency, making it apt for live and real-time video. Furthermore, it includes features like HDCP for copyright protection and EDID for display data channel communication. Offering support for diverse audio and video formats, including rapidly deployed 4K content, the IPMX Core ensures robust performance across various IP network infrastructures. This flexibility and extensive compatibility make it a prime choice for modern AV workflows.
The High Performance FPGA PCIe Accelerator Card is a compact solution designed to enhance server capabilities through efficient and rapid data processing. Featuring the Intel Arria 10 FPGA, it supports acceleration of computation-heavy tasks and can interface seamlessly with low-power systems, providing substantial throughput improvements in processing video and data. Equipped with multiple DDR3 memory banks and a PCIe x8 Gen3 interface, this card excels in applications ranging from video encoding and decoding to scientific computations and algorithmic trading. The versatility of the card makes it suitable for a variety of scenarios requiring high-density and cost-effective FPGA solutions.
The EZiD211 is a highly advanced DVB-S2X demodulator/modulator, a product of EASii IC's SATCOM division designed for high performance in satellite communication systems. It caters to LEO, MEO, and GEO satellites, providing features such as Beam Hopping, VLSNR, and Super Frame to enhance data transmission capacities. Its architecture ensures compatibility with existing satellite infrastructure while pushing forward the new standards in DVB-S2X technologies. The EZiD211 integrates seamlessly within larger communication networks, furnishing robust modulation and demodulation capabilities that connect harmoniously with other components. EASii IC's EZiD211 enables efficient data handling and real-time signal processing essential for next-generation satellite terminal applications. It comes with an evaluation board to allow developers to explore its comprehensive capabilities, making integration into existing systems smoother and more efficient.
HEVC/H.265 Main/Main10/ Main Still Picture Profile @L5.2 AVC/H.264 BP/CBP/MP/HP/HP10 @L5.2 Capable of encoding up to 8K ((8192x4096) A 32-bit AMBA3 APB bus for host CPU system control 128-bit AMBA3 AXI for data transfer (Optionally, additional secondary AXI) Latency tolerance Low power consumption Programmability Configurable IP Multi-instances Frame buffer compression (CFrame) Rotation & Mirroring Bit-depth & chroma sub-sample conversion Background detection 3DNR Lambda table QP Map Custom mode decision, etc.
HEVC/H.265 - Main/Main10 Profile @L5.1 AVC/H.264 - BP/CBP/MP/HP/HP10 Profile @ L5.2 Capable of decoding up to 4K60fps (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Secondary AXI interfaces Downscaler (on-the-fly mode)
A versatile decoder, the logiJPGD facilitates simultaneous decoding of up to four HD video channels adhering to the JPEG standard Baseline DCT. It is ideal for applications in video over IP, ensuring precise decompression across AMD's All Programmable SoC and FPGA platforms.<br><br>Its ability to manage multiple video streams efficiently makes it a preferred choice in broadcasting, surveillance, and any field requiring robust video data handling. With its emphasis on maintaining video integrity across multiple channels, the logiJPGD supports detailed and accurate video reproduction.<br><br>This IP core positions itself as a cornerstone for multi-stream video processing, offering exceptional decompression capabilities tailored to modern digital video applications. Its integration into existing systems facilitates enhanced functionality without compromising system performance.
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
MPEG-H Audio System is a cutting-edge audio technology designed for the immersive experiences of modern television and virtual reality platforms. Recognized as a groundbreaking audio system, Fraunhofer IIS developed it to provide an interactive and enveloping audio environment, transforming the way viewers and gamers experience sound in multimedia contexts. Tailored for the demands of both VR and broadcast TV, the system supports a comprehensive 3D sound experience that makes use of state-of-the-art audio encoding. At its core, MPEG-H Audio System allows users to position sound elements freely in a three-dimensional space, enabling an unprecedented level of realism. Whether it's the dramatic soundscapes in film or the all-encompassing audio required for virtual reality games, MPEG-H offers flexibility and precision that cater to a wide audience ranging from everyday users to professional creators. The audio system’s compatibility with the next generation TV standards and its adaptability to various playback environments make it particularly advantageous. Its design seamlessly integrates into existing deployment frameworks, providing dynamic and rich audio experiences without the complexity of previous systems. As such, MPEG-H Audio is poised to redefine the standards of digital audio, making its impact felt across entertainment and content production industries worldwide.
Video Codec Standard AV1: Main profile @ L5.1 HEVC: Main/Main10 profile, Main/Main 10 Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L5.2 (Interlaced coding tools are not supported) Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
Video Codec Standard AV1: Main profile @ L6 High tier HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main profile @ L5.1 Main tier 50Mbps HEVC/H.265: Main/Main 10 profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L5.2 (Interlaced coding tools are not supported.) VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding Down-scaler (On-the-fly mode) MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard AV1: Main profile @ L6 Main tier 50Mbps HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main/High profile @ L6 Main tier 50Mbps Professional profile except 12-bit @ L6 Main tier 50Mbps Mono/YUV420/YUV422/YUV444 8-/10-bit HEVC/H.265: Main/Main 10/Main 4:2:2 10 profile @ L6 High tier Main 4:4:4/Main 4:4:4 10 profile @ L6 High tier (Only support 4:2:0 coding tools, high precision weighted prediction, and chroma QP offset list) AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L6 High 10 Intra/High 4:2:2/High 4:2:2 Intra profile with frame_mbs_only_flag = 1 @ L6 High 4:4:4 Predictive/High 4:4:4 Intra/CAVLC 4:4:4 Intra profile @ L6 with: frame_mbs_only_flag = 1 bit_depth_luma ≤ 10 bit_depth_chroma ≤ 10 frame_mbs_only_flag = 1 and qpprime_y_zero_transform_bypass_flag = 0 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported), YUV420 8/10-bit Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Rotate/Mirror Down-scaler Crop Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
Supported standards for Decoder ISO/IEC23008-2 HEVC/H.265, ITU-T Rec. H.265 Main/Main10 Profile L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance Interface AMBA 32-bit APB interface for Host CPU AMBA 128-bit AXI interface for the external memory
Video Codec Standard AV1: Main Profile @ L5.1 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
Decoding/Encoding Tools Support Extended Sequential ISO/IEC 10918-1 JPEG compliance Support one or three color components Three components in a scan (interleaved only) 8-bit and 12-bit samples for each component Support 4:2:0, 4:2:2, 4:4:0, 4:4:4 and 4:0:0 color formats Max. six 8x8 blocks in one MCU Support NV12/NV16/NV24 (CbCr Interleaved), NV21/NV61/NV42 (CrCb Interleaved) Support from 16 x 16 to 32K x 32K (32,768 x 32,768) image size Packed mode is supported 12-bit PPM format is supported Value-added Features Partial mode for encoding and decoding On-the-fly rotator/mirror ROI(Region of Interest) for decoding On-the-fly downsampler for decoding Color format converting for decoding Performance Decode up to 290M pix/s for 4:2:0 color format Encode up to 290M pix/s for 4:2:0 color format Operating clock frequency: 200MHz Ease of integration AMBA 32-bit APB (w/ PREADY) interface for communication with a host processor AMBA 64-bit AXI interface for the external memory
The logiJPGD-LS represents a high-performance lossless Motion JPEG decoder compliant with Annex H of the ISO/IEC 10918-1 JPEG standard. Engineered to operate on AMD's MPSoC, SoC, and FPGA devices, it effectively handles still image and video decompression with precision and efficiency.<br><br>Perfectly suited for applications where the integrity of video and images must be maintained without loss, such as medical imaging, surveillance, and broadcast. The decoder provides reliable decompression outcomes by ensuring full retention of original image quality.<br><br>Incorporating this IP core into systems reduces the complexity associated with lossless image decompression while optimizing processing speed and resource utilization. The logiJPGD-LS allows for the seamless handling of image data across various demanding applications.
Brief specification HEVC/H.265 Main/Main10 Profile @L5.1 AV1 Main Profile @ L5.1 VP9 Profile 0/ Profile 2 @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 System I/F A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/additional Secondary AXI) Burst Write Back (BWB) Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance
HEVC/H.265 Main/Main10 Profile @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 VP9 Profile 0/Profile 2 (HBD) AVS2 Main10 Profile @L8.0.60 Capable of decoding up to 4Kp60 (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Downscaler (on-the-fly mode)
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, and Sorenson decoder HW IP for 2Kp60, 4:2:0 Standards AVC/H.264 BP/CBP/MP/HP L.4.1 Max: 1920x1088; Min: 16x16 MVC SHP L.4.1 Max: 1920x1088; Min: 16x16 MPEG-4 SP/ASP L.5 Max: 1920x1088; Min: 16x16 H.263 Profile 3 Max: 1920x1088; Min: 16x16 VC-1 SP/MP/AP L.3 Max: 1920x1088 or 2048x1024 Min: 16x16 MPEG-1/2 MP L.high Max: 1920x1088; Min: 16x16 Sorenson Spark Max: 1920x1088; Min: 16x16 VP8 WebM/WebP Max: 1920x1088; Min: 16x16 Theora Max: 1920x1088; Min: 16x16 AVS Jizhun/Guangdian L6.2 Max: 1920x1088; Min: 16x16 Features Frame buffer compression (CFrame) Low delay decoding Configurable IP Programmability Low power consumption Frame-based processing Multi-instances Latency tolerance Burst Write Back Down-scaler (on-the-fly mode) Map converter MPEG-2/4 De-ringing Built-in de-blocking filter A 32-bit AMBA3 APB bus and 64-bit AMBA3 AXI buses (w/additional Secondary AXI buses)
The logiJPGE is a versatile Motion JPEG encoder that provides efficient video compression, supporting JPEG standard Baseline DCT. Designed for AMD's All Programmable SoC and FPGA devices, it ensures that high-quality video streams are compressed with precision and efficiency across various applications.<br><br>This encoder is particularly beneficial in environments such as broadcasting and security where rapid, real-time video compression without quality loss is necessary. Its robust design maintains the integrity of video signals during compression, offering a reliable solution for systems demanding consistent video fidelity.<br><br>By delivering flexible and efficient encoding capabilities, the logiJPGE becomes an essential component in managing video streams, facilitating seamless integration into diverse video processing applications. It sets a standard for quality and performance in video compression solutions.
Video Codec Standard HEVC: Main/Main10 profile @ L6 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 (Interlaced coding tools are not supported) Performance 4K120fps@500MHz or 8K60fps@1GHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer *Optional AXI can be used to alleviate bandwidth usage
Video Codec Standard HEVC/H.265: Main/Main 10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz or 8K30fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, Sorenson Decoding and encoding support at 1080p 60fps Supported standards for Decoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP,ASP@L6 SMPTE 421M-2006 VC-1 SP/MP/AP@L3 ISO/IEC 13818-2 MPEG-2 MP@HL ITU-T H.263(Annex I,J,K,T) AVS Jizhun @L6.2 AVS+ Guangdian @L6.2 On2 VP8 Sorenson Spark Theora Supported standards for Encoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP@L6 ITU-T H.263(Annex J,K,T) Supported Max. Resolution Supports up to 2048x2048 resolution Performance Single-stream H.264 HD(1920x1080p) 30fps decoding at <133MHz core clock H.264 HD(1920x1080p) 60fps decoding at <266MHz core clock H.264 HD(1920x1080p) 30fps encoding at <133MHz core clock H.264 HD(1920x1080p) 60fps encoding at <266MHz core clock Multi-stream Dual H.264 HD(1920x1080p) 30fps decoding at <266MHz core clock Dual H.264 HD(1920x1080p) 30fps encoding at <266MHz core clock 6SD/D1(NTSC&PAL) 30fps decoding at <133MHz core clock Full HD(1080p) encoding and decoding at <266MHz core clock Encoding Tools Selective [+/-64,+/-48] Quarter-pel and half-pel accuracy motion estimation using a full- search algorithm Flexible bit-rate control CBR VBR Fixed QP CABAC/CAVLC for AVC/H.264 Built-in pre- rotation/mirroring function 90xn degree rotation Vertical/horizontal mirroring Decoding Tools CABAC/CAVLC for AVC/H.264 MPEG-4 AC/DC prediction AVC/H.264 intra-prediction In-loop deblocking filter for H.264, H.263, and AVS Overlapped smoothing filter for VC-1 Built-in post-processing function 90xn degree rotation Vertical/horizontal mirroring De-ringing De-blocking filter for MPEG-2/4 Interface AMBA 32-bit APB interface for Host CPU AMBA 64-bit AXI interface for the external memory
High-resolution Image Processing IP Performance 4K60p@400MHz (600MHz for display interface) Features Support various color format : YUV420, YUV422, YUV444, and RGB Up-/Down-scaler x1/8~x8 : selectable scaler algorithm with Bi-cubic and Lanczos Two scalers, connected to DRAM and display/direct I/F respectively, operating at different ratios at the same time (configurable to one scaler option) Color space conversion : YUV2RGB and RGB2YUV, coefficient downloadable Optional features Crop and digital zoom : scaling on cropped region Flip : horizontal and vertical 3rd Party interfaces: such as AFBC v1.2 and PVRIC v4 (support output only) Interface Display Interface : 3 channels for components with vertical/horizontal sync signal (ITU-R BT.601 compatible) Direct Interface (optional feature) : On-the-fly interface based on ready-valid protocol Support CF10 (Chips&Media’s Frame buffer compression) for Chips&Media video codec Support AFBC v1.2 and PVRIC v4 (optional feature) for output of MAPI
The logiJPGE-LS is a robust lossless Motion JPEG encoder conforming to the ISO/IEC 10918-1 JPEG standard, specifically Annex H. Designed for AMD MPSoC, SoC, and FPGA, it excels in still image and video compression without sacrificing data integrity.<br><br>This IP core is instrumental in professional fields like medical imaging and security systems, where maintaining image quality during compression is crucial. It aligns well with applications requiring high compression fidelity, ensuring that all data details are retained during encoding.<br><br>The logiJPGE-LS encoder streamlines the creation of compressed video streams, enhancing data efficiency while preserving quality. It is indispensable in scenarios demanding precise image representation combined with optimal resource management.
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Creonic's DVB-S2X LDPC/BCH Decoder is a high-performing solution aimed at optimizing data integrity in digital video broadcasting satellite systems. By combining low-density parity-check (LDPC) and Bose–Chaudhuri–Hocquenghem (BCH) codes, this decoder provides error correction capabilities that ensure clear and uninterrupted signal delivery, which is crucial for high-definition broadcasting and communication applications. The decoder is adept at handling the rigorous data demands associated with the DVB-S2X standard, recognized for facilitating efficient and high-capacity satellite communications. Through its dual coding approach, it mitigates errors that can degrade video quality, thus maintaining the broadcast integrity over long distances and adverse conditions. Its integration capability allows for seamless operation within existing DVB-S2 or DVB-S2X platforms, making upgrades practical and economically viable. By focusing on reliability and performance, the DVB-S2X LDPC/BCH Decoder supports broadcasters and satellite operators in delivering consistent high-quality transmissions. Its advanced error correction algorithms contribute to an efficient use of bandwidth and enhance overall transmission reliability, making it a valuable component in modern satellite communication systems.
The DVB-S2X Modulator from Creonic is designed to enhance digital broadcasting services by efficiently modulating signals in accordance with the DVB-S2X standard. As a key enabler for satellite transmission, this modulator supports advanced modulation schemes and coding that improve bandwidth efficiency and signal robustness. This makes it ideal for applications where high-definition video and broad-spectrum data need to be broadcast efficiently and reliably. A hallmark of this modulator is its ability to adapt to diverse transmission conditions, ensuring optimal performance across a variety of scenarios. It ingeniously balances power usage and spectral efficiency, maximizing throughput while minimizing resource consumption. This is particularly significant for satellite operators and service providers aiming to offer high-quality broadcast services without incurring substantial additional costs. Incorporating sophisticated algorithms, Creonic’s DVB-S2X Modulator ensures crisp, reliable signal transmission even in challenging environments. It is engineered to seamlessly integrate with existing infrastructure, offering an upgrade path for operators seeking to enhance their service offerings in the competitive broadcasting landscape.
The MPEG-1/2 - Layer I/II Audio Decoder specializes in decoding audio streams with precision across various digital platforms. It is crafted to handle the complexities of MPEG-1/2 formats, ensuring that the audio quality remains uncompromised throughout the process. This IP core is designed for integration into systems that require expansive format compatibility and the ability to manage multi-channel operations efficiently. Its real-time capabilities make it advantageous for applications seeking rapid data decoding without additional overhead. Alongside its performance efficiency, the decoder's energy-saving design reduces power consumption, making it an asset for devices prioritizing both efficiency and quality. Its versatility ensures suitability for a broad range of audio-based applications seeking reliable and rapid decoding capabilities.
MPEG-1/2 + AAC Audio Decoders IP combines cutting-edge technology to decode both MPEG and AAC audio streams. Designed for real-time applications, these decoders ensure smooth playback and high-quality audio reproduction across varying system platforms. Harnessing advanced decoding methodologies, this IP core can handle diverse audio formats with accuracy, supporting broad compatibility for consumer electronics and professional audio devices. Its real-time capabilities allow for the handling of multi-stream environments without energy waste. This versatile decoder is optimized to deliver spectacular audio integrity, making it a preferred choice for systems where superior performance and energy saving are equally demanded. It's perfectly suited for media playback, broadcast, and other high-stakes environments requiring meticulous audio handling.
The MPEG-1/2 - Layer I/II Audio Encoder IP provides streamlined encoding capabilities for digital audio systems, compatible with a multitude of audio applications ranging from broadcasting to customized sound design. Supporting MPEG-1/2 Layer I/II, this encoder is designed to offer top performance with minimal power usage. This IP core integrates seamlessly into both ASIC and FPGA frameworks, providing adaptive support across different hardware configurations. Its real-time processing ability makes it a reliable choice for encoding tasks that demand quick and efficient data handling without sacrificing quality. Purposefully architected to manage varied channel operations smoothly, this encoder prides itself on flexibility and precision. Its emphasis on efficient resource use, combined with robust encoding quality, makes it particularly appealing for applications targeting high-efficiency audio solutions.
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