All IPs > Network on Chip > Network on Chip
Network on Chip (NoC) semiconductor IPs play a crucial role in modern electronic design, offering advanced solutions for efficient data communication within integrated circuits. As devices become more complex, traditional bus systems struggle to meet the demand for fast, reliable data transfer. This is where NoC technology comes into play, enhancing the scalability and performance of electronic devices from smartphones to data centers.
At its core, a Network on Chip provides a sophisticated, packet-switched network capable of linking various IP cores in a System on Chip (SoC). This architecture not only boosts communication efficiency but also facilitates easier design of high-performance systems. By implementing NoC semiconductor IPs, designers can effectively manage bandwidth, reduce latency, and improve overall chip performance. These improvements are essential for applications demanding high-speed processing, such as artificial intelligence, machine learning, and real-time data analysis.
Products in the Network on Chip category include a diverse range of solutions, from basic routers and switches to complex network architectures supporting multichip modules. These IPs are tailored to address different design requirements, offering customizable topologies that support varied performance needs. Whether you are building a simple communication channel for a small device or a robust network for a large data center, Silicon Hub provides the semiconductor IPs you need to optimize your design.
In summary, exploring the Network on Chip category at Silicon Hub opens the door to innovative solutions for next-generation electronic systems. With these semiconductor IPs, designers gain the tools necessary to overcome traditional constraints, ultimately achieving faster, more efficient, and scalable devices. Whether your focus is low-power IoT devices or high-performance computing systems, Network on Chip technology is key to unlocking enhanced communication capabilities across your products.
The Akida 2nd Generation represents a leap forward in the realm of AI processing, enhancing upon its predecessor with greater flexibility and improved efficiency. This advanced neural processor core is tailored for modern applications demanding real-time response and ultra-low power consumption, making it ideal for compact and battery-operated devices. Akida 2nd Generation supports various programming configurations, including 8-, 4-, and 1-bit weights and activations, thus providing developers with the versatility to optimize performance versus power consumption to meet specific application needs. Its architecture is fully digital and silicon-proven, ensuring reliable deployment across diverse hardware setups. With features such as programmable activation functions and support for sophisticated neural network models, Akida 2nd Generation enables a broad spectrum of AI tasks. From object detection in cameras to sophisticated audio sensing, this iteration of the Akida processor is built to handle the most demanding edge applications while sustaining BrainChip's hallmark efficiency in processing power per watt.
Designed for memory-coherent systems, the Coherent Network-on-Chip (NOC) by SkyeChip is a scalable, efficient interconnect solution that minimizes routing congestion in large-scale designs. It supports ACE4, ACE5, and CHI protocols, providing robust interconnect options that enhance many-core system performance. Moreover, it is built to support up to 2GHz operating frequencies and seamlessly integrates with non-coherent NOC setups, enhancing connectivity in diverse semiconductor applications.
The Universal Chiplet Interconnect Express (UCIe) by EXTOLL is a cutting-edge interconnect framework designed to revolutionize chip-to-chip communication within heterogeneous systems. This product exemplifies the shift towards chiplet architecture, a modular approach enabling enhanced performance and flexibility in semiconductor designs. UCIe offers an open and customizable platform that supports a wide range of technology nodes, particularly excelling in the 12nm to 28nm range. This adaptability ensures it can meet the diverse needs of modern semiconductor applications, providing a bridge that enhances integration across various chiplet components. Such capabilities make it ideal for applications requiring high bandwidth and low latency. The design of UCIe focuses on minimizing power consumption while maximizing data throughput, aligning with EXTOLL’s objective of delivering eco-efficient technology. It empowers manufacturers to forge robust connections between chiplets, allowing optimized performance and scalability in data-intensive environments like data centers and advanced consumer electronics.
Chimera GPNPU is engineered to revolutionize AI/ML computational capabilities on single-core architectures. It efficiently handles matrix, vector, and scalar code, unifying AI inference and traditional C++ processing under one roof. By alleviating the need for partitioning AI workloads between different processors, it streamlines software development and drastically speeds up AI model adaptation and integration. Ideal for SoC designs, the Chimera GPNPU champions an architecture that is both versatile and powerful, handling complex parallel workloads with a single unified binary. This configuration not only boosts software developer productivity but also ensures an enduring flexibility capable of accommodating novel AI model architectures on the horizon. The architectural fabric of the Chimera GPNPU seamlessly blends the high matrix performance of NPUs with C++ programmability found in traditional processors. This core is delivered in a synthesizable RTL form, with scalability options ranging from a single-core to multi-cluster designs to meet various performance benchmarks. As a testament to its adaptability, the Chimera GPNPU can run any AI/ML graph from numerous high-demand application areas such as automotive, mobile, and home digital appliances. Developers seeking optimization in inference performance will find the Chimera GPNPU a pivotal tool in maintaining cutting-edge product offerings. With its focus on simplifying hardware design, optimizing power consumption, and enhancing programmer ease, this processor ensures a sustainable and efficient path for future AI/ML developments.
SkyeChip's Non-Coherent Network-on-Chip (NOC) is tailored to enhance bandwidth and latency performance, ideal for optimizing silicon area and power usage in integrated circuits. The NOC architecture efficiently reduces routing congestion, supporting protocols such as AXI4, AXI5, and others, with operation frequencies up to 2GHz. It integrates seamlessly with coherent NOC systems and supports advanced die-to-die bridging, offering a comprehensive solution for high-frequency, partitioned interconnect systems in modern semiconductor designs.
The NuLink Die-to-Die PHY for Standard Packaging by Eliyan is engineered to facilitate superior die-to-die interconnectivity on standard organic/laminate package substrates. This innovative PHY IP supports key industry standards such as UCIe and BoW, and includes proprietary technologies like UMI and SBD. The NuLink PHY delivers leading performance and power efficiency, comparable to advanced packaging technologies, but at a fraction of the cost. It features configurations with up to 64 data lanes, supporting a data rate per lane of up to 64Gbps, making it ideal for applications demanding high bandwidth and low latency. The implementation enhances system design while reducing the necessary area and thermal load, which significantly eases integration into existing hardware ecosystems.
aiSim 5 stands as a cutting-edge simulation tool specifically crafted for the automotive sector, with a strong focus on validating ADAS and autonomous driving solutions. It distinguishes itself with an AI-powered digital twin creation capability, offering a meticulously optimized sensor simulation environment that guarantees reproducibility and determinism. The adaptable architecture of aiSim allows seamless integration with existing industry toolchains, significantly minimizing the need for costly real-world testing.\n\nOne of the key features of aiSim is its capability to simulate various challenging weather conditions, enhancing testing accuracy across diverse environments. This includes scenarios like snowstorms, heavy fog, and rain, with sensors simulated based on physics, offering changes in conditions in real-time. Its certification with ISO 26262 ASIL-D attests to its automotive-grade quality and reliability, providing a new standard for testing high-fidelity sensor data in varied operational design domains.\n\nThe flexibility of aiSim is further highlighted through its comprehensive SDKs and APIs, which facilitate smooth integration into various systems under test. Additionally, users can leverage its extensive 3D asset library to establish detailed, realistic testing environments. AI-based rendering technologies underpin aiSim's data simulation, achieving both high efficiency and accuracy, thereby enabling rapid and effective validation of advanced driver assistance and autonomous driving systems.
The Ncore Cache Coherent Interconnect is designed to tackle the complexities inherent in multicore SoC environments. By maintaining coherence across heterogeneous cores, it enables efficient data sharing and optimizes cache use. This in turn enhances the throughput of the system, ensuring reliable performance with reduced latency. The architecture supports a wide range of cores, making it a versatile option for many applications in high-performance computing. With Ncore, designers can address the challenges of maintaining data consistency across different processor cores without incurring significant power or performance penalties. The interconnect's capability to handle multicore scenarios means it is perfectly suited for advanced computing solutions where data integrity and speed are paramount. Additionally, its configuration options allow customization to meet specific project needs, maintaining flexibility in design applications. Its efficiency in multi-threading environments, coupled with robust data handling, marks it as a crucial component in designing state-of-the-art SoCs. By supporting high data throughput, Ncore keeps pace with the demands of modern processing needs, ensuring seamless integration and operation across a variety of sectors.
EXTOLL's High-Speed SerDes for Chiplets is a pioneering connectivity solution crafted for seamless integration in chiplet-based systems. It serves as a core technology in facilitating swift data transfer across different chiplets, ensuring robust and efficient performance. This SerDes excels in maintaining low power consumption to optimize energy efficiency, crucial for modern computing needs. By leveraging innovative design principles, this SerDes supports mainstream technology nodes ranging from 12nm to 28nm. The flexibility provided by such support makes it a versatile choice for various high-speed data applications, ensuring adaptability to future technological advances. This capability underscores its role in facilitating heterogeneous integration, a crucial aspect in cutting-edge semiconductor environments. Furthermore, the High-Speed SerDes is crafted to cater to applications requiring reduced latency and enhanced bandwidth capabilities. Ideal for systems such as data centers and communications infrastructure, it empowers device manufacturers to implement scalable and sustainable solutions efficiently.
The ISPido on VIP Board is tailored specifically for Lattice Semiconductor's Video Interface Platform (VIP) and is designed to achieve clear and balanced real-time imaging. This ISPido variant supports automatic configuration options to provide optimal settings the moment the board is powered on. Alternatively, users can customize their settings through a menu interface, allowing for adjustments such as gamma table selection and convolutional filtering. Equipped with the CrossLink VIP Input Bridge, the board features dual Sony IMX 214 image sensors and an ECP5 VIP Processor. The ECP5-85 FPGA ensures reliable processing power while potential outputs include HDMI in YCrCb 4:2:2 format. This flexibility ensures users have a complete, integrated solution that supports runtime calibration and serial port menu configuration, making it an extremely practical choice for real-time applications. The ISPido on VIP Board is built to facilitate seamless integration and high interoperability, making it a suitable choice for those engaged in designing complex imaging solutions. Its adaptability and high-definition support make it particularly advantageous for users seeking to implement sophisticated vision technologies in a variety of industrial applications.
UTTUNGA is a high-performance PCIe accelerator card, purpose-built to amplify HPC and AI tasks through its integration with the TUNGA SoC. It effectively harnesses the power of multi-core RISC-V technology combined with Posit arithmetic, offering significant enhancements in computation efficiency and memory optimization. Designed to be compatible with a broad range of server architectures, including x86, ARM, and PowerPC, UTTUNGA elevates system capabilities, particularly in precision computing applications. The UTTUNGA card operates by implementing foundational arithmetic operations in Posit configurations, supporting multiple bit-width formats for diverse processing needs. This flexibility is further complemented by a pool of programmable FPGA gates, optimized for scenarios demanding real-time adaptability and cloud computing acceleration. These gates facilitate the acceleration of complex tasks and aid in the effortless management of non-standard data types essential for advanced AI processing and cryptographic applications. By leveraging a seamless integration process, UTTUNGA eliminates the need for data copying in host memory, thus ensuring efficient utilization of resources. It also provides support for well-known scientific libraries, enabling easy adoption for legacy systems while fostering a modern computing environment. UTTUNGA stands as a testament to the profound impact of advancing arithmetic standards like Posit, paving the way for a transformation in computational practices across industries.
The 2D FFT IP extends the power of the traditional FFT by enabling two-dimensional transforms, essential for image and signal processing where data is structured in matrices. With an impressive balance of speed and resource utilization, the 2D FFT handles massive data efficiently using internal or external memory interfaces to fit broad application demands. Its adaptability for FPGA and ASIC applications makes it an ideal candidate for high-performance computing tasks needing complex data manipulation.
The Network on Chip (NOC-X) from EXTOLL is an advanced interconnect network designed for chiplet architectures. It serves as an integral component in facilitating on-chip communication, offering high-speed data exchange between various processing units within a semiconductor device. NOC-X is engineered to provide scalable and efficient routing paths, essential for managing complex data flows in sophisticated computing environments. By reducing congestion and optimizing bandwidth usage, it ensures that high-performance applications can execute seamlessly without bottlenecks, facilitating improved overall system efficiency. With a focus on maintaining low power consumption, NOC-X is suitable for integration within systems using standard nodes between 12nm and 28nm. Its robust design and versatility make it an ideal choice for a wide range of applications, including data center operations and high-performance computing sectors where reliability and scalability are paramount.
The BlueLynx Chiplet Interconnect system provides an advanced die-to-die connectivity solution designed to meet the demanding needs of diverse packaging configurations. This interconnect solution stands out for its compliance with recognized industry standards like UCIe and BoW, while offering unparalleled customization to fit specific applications and workloads. By enabling seamless connection to on-die buses and Networks-on-Chip (NoCs) through standards such as AMBA, AXI, ACE, and CHI, BlueLynx facilitates faster and cost-effective integration processes. The BlueLynx system is distinguished by its adaptive architecture that maximizes silicon utilization, ensuring high bandwidth along with low latency and power efficiency. Designed for scalability, the system supports a remarkable range of data rates from 2 to 40+ Gb/s, with an impressive bandwidth density of 15+ Tbps/mm. It also provides support for multiple serialization and deserialization ratios, ensuring flexibility for various packaging methods, from 2D to 3D applications. Compatible with numerous process nodes, including today’s most advanced nodes like 3nm and 4nm, BlueLynx offers a progressive pathway for chiplet designers aiming to streamline transitions from traditional SoCs to advanced chiplet architectures.
The Hyperspectral Imaging System developed by Imec is designed to capture images across numerous wavelengths, enabling detailed analysis of spectral information beyond conventional imaging. This hyperspectral imaging technology is pivotal in extracting valuable insights in fields such as precision agriculture, environmental monitoring, and industrial inspection. With its versatile applications, it offers enhanced capabilities in material identification, chemical analysis, and quality control processes. This system incorporates state-of-the-art sensors that capture data with high spectral and spatial resolution, providing a comprehensive spectral fingerprint of the imaged scene. It excels in distinguishing subtle differences in material properties by analyzing the light reflected from different surfaces across various spectral bands. By using this advanced imaging system, users can perform complex analyses such as vegetation monitoring, pollution detection, and mineral mapping with unprecedented precision. It allows for non-destructive testing, which is crucial for industries like food safety, pharmaceutical production, and environmental science.
ISPido is a powerful and flexible image signal processing pipeline tailored for high-resolution image processing and tuning. It supports a comprehensive pipeline of image enhancement features such as defect correction, color filter array interpolation, and various color space conversions, all configurable via the AXI4-LITE protocol. Designed to handle input depths of 8, 10, or 12 bits, ISPido excels in processing high-definition resolutions up to 7680x7680 pixels, making it highly suitable for a variety of advanced vision applications. The architecture of ISPido is built to be highly compatible with AMBA AXI4 standards, ensuring that it can be seamlessly integrated into existing systems. Each module in the pipeline is individually configurable, allowing for extensive customization to optimize performance. Features such as auto-white balance, gamma correction, and HDR chroma resampling empower developers to produce precise and visually accurate outputs in complex environments. ISPido's modular and versatile design makes it an ideal choice for deploying in heterogeneous processing environments, ranging from low-power battery-operated devices to sophisticated vision systems capable of handling resolutions higher than 8K. This adaptability makes it a prime solution for developers working across various sectors demanding high-quality image processing.
ShortLink offers a powerful and comprehensive RF Transceiver IP for 433, 868, and 915 MHz frequency bands, which is compliant with the IEEE 802.15.4-2015 standard. With features like data rates ranging from 1.2 k to 500 kbps, it provides a robust solution for diverse low-power wireless network applications. The transceiver handles both transmission and reception at various bands, making it suitable for worldwide deployment. The integration is simplified with built-in voltage regulators, bandgap references, and bias generation. The flexible design of this RF transceiver supports different modulation techniques, including GFSK, BPSK, and O-QPSK, catering to a wide range of communication needs. The configurable architecture ensures compatibility with custom protocols beyond standard applications, providing adaptability for unique project requirements. Built for reliability, the IP showcases RX sensitivity down to -106 dBm and TX power ranging from -20 to +8 dBm, ensuring long-distance communication capabilities and excellent power efficiency. The inherent compliance with standard wireless communication protocols eliminates the need for external radio chips, streamlining the integration process into various SoC designs.
IC Manage offers the Envision Real-Time Analytics Platform as a cutting-edge tool for semiconductor companies looking to analyze design and verification progress. This platform provides visual insights on extensive data sets, leveraging big data technology to offer near-real-time reports that aid efficient decision-making processes. Envision's capabilities extend to tracking millions of data points across massive datasets, providing clear visibility into the design lifecycle's various stages. This comprehensive overview enables design teams to identify trends, predict performance issues, and optimize their workflows to ensure timely project completion. Its ability to analyze vast quantities of data and provide actionable insights is invaluable for companies focusing on efficient design verification. Moreover, the platform's advanced analytics improve collaboration by offering consistent, transparent, and up-to-date information to all stakeholders. It enhances the ability to respond swiftly to potential design challenges, reducing bottlenecks, increasing accuracy, and improving overall efficiency. These features make Envision a critical asset for companies aiming to remain at the forefront of technology innovation.
FlexNoC Interconnect stands as a cornerstone technology for developers aiming to enhance the performance and efficiency of their SoC designs. This flexible, high-performance interconnect supports a multitude of protocols, offering advanced Quality of Service (QoS) and debug features. FlexNoC's capability to accommodate diverse IP cores within a single system enables optimized communication paths, thereby reducing latency and improving data throughput across the chipset. FlexNoC is particularly adept at managing system complexities, thanks to its dynamic configuration abilities. By reducing interconnect wire lengths and facilitating easier integration, it streamlines the backend design process. This not only aids in achieving quicker timing closure but also enhances the overall SoC economics by minimizing manufacturing costs. The interconnect's strength is evidenced by its utilization in various high-demand sectors such as automotive, industrial, and consumer electronics, where the fast, reliable processing of information is crucial. Its ability to balance load and administer traffic control effectively extends its utility across a wide array of applications, ensuring it remains a vital tool for modern SoC development.
Optimized for 5G NTN hybrid networks, AccelerComm's Complete 5G NR Physical Layer solution enhances link performance while maintaining industry-leading size, weight, and power (SWaP) metrics. Designed to support diverse use cases such as broadband, direct-to-device (D2D), and defense applications, the solution is adaptable across various platforms including ARM CPUs, AI Engines, FPGA, and ASIC-ready IP cores. The solution allows early end-to-end integration by running on a range of Commercial off the Shelf (COTS) boards, reducing project risk. Employing innovative algorithms, the physical layer not only achieves high throughput but also supports a vast number of users per chipset, capable of scaling to the capacity needs of next-generation satellite constellations. Moreover, AccelerComm’s unique approach emphasizes flexibility and rapid integration, utilizing standardized interfaces that ensure smooth inclusion in a variety of projects. With a focus on minimizing latency and enhancing error correction capabilities, this solution is crafted to resolve the unique challenges presented by 5G NTN environments.
Thermal oxide, often referred to as SiO2, is an essential film used in creating various semiconductor devices, ranging from simple to complex structures. This dielectric film is created by oxidizing silicon wafers under controlled conditions using high-purity, low-defect silicon substrates. This process produces a high-quality oxide layer that serves two main purposes: it acts as a field oxide to electrically insulate different layers, such as polysilicon or metal, from the silicon substrate, and as a gate oxide essential for device function. The thermal oxidation process occurs in furnaces set between 800°C to 1050°C. Utilizing high-purity steam and oxygen, the growth of thermal oxide is meticulously controlled, offering batch thickness uniformity of ±5% and within-wafer uniformity of ±3%. With different techniques used for growth, dry oxidation results in slower growth, higher density, and increased breakdown voltage, whereas wet oxidation allows faster growth, even at lower temperatures, facilitating the formation of thicker oxides. NanoSILICON, Inc. is equipped with state-of-the-art horizontal furnaces that manage such high-precision oxidation processes. These furnaces, due to their durable quartz construction, ensure stability and defect-free production. Additionally, the processing equipment, like the Nanometrics 210, inspects film thickness and uniformity using advanced optical reflection techniques, guaranteeing a high standard of production. With these capabilities, NanoSILICON Inc. supports a diverse range of wafer sizes and materials, ensuring superior quality oxide films that meet specific needs for your semiconductor designs.
Akronic's mmW-IC Wireless Transceivers represent a pinnacle of design in millimeter-wave frequency domains, offering unparalleled expertise in the development of integrated solutions for both telecom and radar applications. Operating in frequency ranges between 6 GHz and 120 GHz, these transceivers support high-speed communication links and advanced radar sensing applications. The company’s deep-rooted experience includes crafting complete transceiver solutions for next-generation telecom standards, supporting wireless connections across various bands such as unlicensed 60GHz and E-band frequencies. Akronic’s transceivers are known for their robust architectures, incorporating proprietary passives and optimized design topologies. These transceivers offer capabilities for backhaul, fronthaul, and point-to-point applications, featuring strong emphases on reducing cost and risk while accelerating time-to-market. In radar technology, Akronic’s offering includes FMCW radar transceivers for automotive applications and beyond, with specific support for frequencies such as 60GHz, 77GHz, and 94GHz. Their design methodology ensures high first-silicon success rates due to precision in chip-to-PCB landing design and electromagnetic simulations, effectively turning high-frequency requirements into viable silicon solutions.
Tensix Neo represents a groundbreaking leap in AI processing, purpose-built to optimize specific AI workloads with outstanding performance-per-watt efficiency. The platform delivers adaptable solutions to AI developers, facilitating rapid acceleration of AI networks and applications. Designed with a sophisticated Network-on-Chip (NoC), Tensix Neo ensures comprehensive connectivity and scalability to accommodate an expanding array of AI models, allowing developers to match pace with swift industry changes. It supports diverse precision formats and is engineered for seamless interaction with emerging technologies, maintaining flexibility to cater to AI-driven advancements.
OPENEDGES Technology’s Network on Chip (NoC) Bus Interconnect provides a high-performance, scalable communication framework that connects various IP blocks within a SoC. This interconnect is designed to handle large volumes of data traffic efficiently, ensuring minimal latency across different functionalities within the system. The NoC Bus Interconnect is particularly beneficial in multicore processor architectures where effective communication between cores directly impacts overall performance. By efficiently routing information, it plays a crucial role in reducing congestion and improving system bandwidth. In addition to improving data transfer efficiencies, the NoC Bus Interconnect offers a customizable architecture that can be tailored to meet specific application requirements. Its integration capability with existing systems ensures that it can enhance performance without necessitating significant redesign efforts in the core architecture.
The SEMIFIVE SoC Platform is a bespoke development environment designed to expedite the creation of custom silicon solutions by leveraging domain-specific architectures. It integrates a pre-verified IP pool, providing a robust foundation for applications requiring tailored performance and cost efficiencies. This platform significantly reduces development time and associated risks by offering a ready-to-use environment that includes silicon-proven design components. With its comprehensive set of features, the platform facilitates rapid prototyping and market deployment, employing a high degree of reusability in design and verification components. By decreasing non-recurring engineering (NRE) costs and enhancing design reliability, the SoC Platform ensures faster time-to-market, making it ideal for industries aiming for quick product turnarounds. The SoC Platform supports scalable integration with third-party IPs, allowing flexibility to meet diverse application needs. Its architecture includes support for multiple processors, memory interfaces, and connectivity solutions, providing a one-stop solution for industries across AI, IoT, and HPC domains, ensuring performance optimization and minimal risk.
The Pipelined FFT IP stands out with its continuous-stream processing capacity, suitable for applications needing uninterrupted data flow and low memory use. By using a single butterfly per rank architecture, it balances between speed and resource efficiency. This design makes it highly appropriate for applications with steady incoming data streams that require real-time processing, ensuring consistent output without the need for extensive buffers or memory.
IC Manage's IP Central Management System is an advanced platform designed to streamline the management of semiconductor IPs. This system is engineered to consolidate all IPs—both internal and external—into a comprehensive, searchable catalog, enhancing accessibility and security across a company's design teams. It addresses the complexities of IP reuse and integration, facilitating a more structured and efficient approach to leveraging IP assets. IP Central stands out by supporting seamless information dissemination and access control, crucial for optimizing design workflows and maximizing IP utility. It empowers organizations to effectively catalog their IP portfolios, integrating them into an enterprise-wide repository that is easily accessible yet tightly secure. This feature is particularly beneficial for design teams striving to balance diverse historical designs and methodologies in their projects. Moreover, the platform is instrumental in establishing a global IP catalog, a strategic advantage for companies looking to enhance the value of their IPs. By fostering a culture of organized and secure IP sharing, IP Central aids in reducing development time, costs while increasing reliability and design accuracy. This tool is a critical component for companies aiming to capitalize on their IP investments through improved management and deployment.
Atrevido is a powerful out-of-order RISC-V core from Semidynamics, designed to support high-performance processing requirements in AI and HPC domains. This 64-bit processor features an advanced out-of-order execution system that is configurable for 2, 3, or 4-wide instruction handling, ensuring peak computing efficiency. Its architecture incorporates both vector and tensor processing capabilities, providing zero-latency integration which is critical for AI inferencing and high-speed data processing. One of Atrevido's standout features is the integration of Semidynamics’ proprietary Gazzillion Misses™ technology, which enhances data throughput by overcoming memory bottlenecks, allowing up to 128 concurrent memory requests. This makes the processor ideally suited for demanding tasks such as machine learning inferencing, sparse data management, and complex analytics. Atrevido’s multiprocessor readiness, with support for both AXI and CHI interfaces, further enhances its adaptability to high-bandwidth infrastructure requirements. The processor supports a wide range of extensions, making it adaptable to various use-cases including bit manipulation and cryptographic operations. This makes Atrevido particularly attractive for users needing a robust and configurable core that can be tailored to meet specific performance and energy efficiency needs. Its architectural flexibility and high processing power make Atrevido a quintessential element for building next-gen AI-driven solutions.
The UltraLong FFT IP is designed for applications requiring extended FFT calculation lengths and re-targets towards both FPGA and ASIC platforms. With a focus on high performance, this IP core provides medium throughput and medium logic resource requirements, using external memory to expand data handling capacity. Ideal for applications involving large data sets, the UltraLong FFT IP core boasts robust capabilities, effectively managing bandwidth-intensive tasks.
Akronic excels in RF and mm-Wave IC design, targeting frequencies from several MHz up to 100GHz. They bring a wealth of expertise in high-frequency subsystems for wireless radio transceivers, known for their integration at RF/mmWave frequencies to achieve optimum noise performance, output power, and linearity. Akronic uses sophisticated circuit topologies and attentive chip layouts, ensuring robust system performance across small silicon areas with minimal power consumption. The company's extensive design experience covers essential components like single-sideband and double-sideband mixers, variable gain amplifiers, low noise amplifiers, and power amplifiers. They also offer VCOs, frequency doublers/triplers, and drivers for RSSI and power detection. Akronic's RF and mmWave designs incorporate comprehensive electromagnetic simulation methodologies and precise device modeling to maintain a high level of design accuracy and performance matching between simulations and real-world measurements. Their approach includes a focus on stability, with custom-made passives to enhance circuit performance. Akronic's design capabilities extend to applications in multi-gigabit wireless communications, backhaul/fronthaul networks, and radar systems, providing custom solutions tailored to specific client needs and industry standards, ensuring high scalability and fast time-to-market.
iNoCulator is an innovative solution designed to expedite the development of flexible and configurable Network-on-Chips (NoCs). This comprehensive platform supports NoC creation from initial concepts to system architecture, culminating in RTL simulation, emulation, and implementation. Notable for its user-friendly editing tools, iNoCulator offers complete configuration flexibility and integrates fully with existing EDA environments. This makes it an ideal choice for designers needing seamless and efficient NoC development processes. Its adaptability not only enhances the speed and efficiency of SoC architectures but also significantly reduces time-to-market.
The intricacies of building a robust SoC lie in having a well-integrated network-on-chip framework. Marquee Semiconductor stands out in developing both coherent and non-coherent NoC-based subsystems and platforms. By integrating various components, these implementations create scalable chiplets that optimize and enhance the performance of complex systems. This setup enables efficient handling of increasing data and device interconnections, ensuring seamless integration within modern SoCs.
Akeana's Processor System IP encompasses a comprehensive range of components essential for creating complete and customized processor solutions. These include components such as Compute Coherence Blocks (CCBs), interconnect fabrics for coherent and non-coherent systems, and advanced interrupt architectures. Designed with flexibility and scalability in mind, Akeana's system IP enables clients to efficiently manage complex system designs through robust architectures supporting AMBA protocols for seamless integration. The system IP not only supports the construction of many-core systems, it's also built to optimize performance, offering advanced memory management features and dedicated support for sophisticated interrupt controls. With a focus on delivering tailored solutions, Akeana's Processor System IP stands out for its ability to adapt to diverse system specifications and enhance processing reliability and efficiency. This set of sophisticated IP blocks enables developers to architect system solutions that are efficient, reliable, and uniquely suited to customer-specific requirements across industries.
The 40G MAC/PCS module is engineered to deliver ultra-low latency for high-speed data transfer in trading environments, where every nanosecond counts. As part of the nxFramework, this IP core is optimized for use in FPGAs, ensuring efficient handling of data streams with minimal latency. Designed expressly for 40G Ethernet, this MAC/PCS core addresses the increasing demand for high-bandwidth, low-latency network solutions in financial markets. By managing data efficiently, it supports the seamless execution of trading strategies that rely on rapid data throughput and minimal delay. With the ability to integrate effortlessly into existing FPGA platforms, this IP core enhances the trading infrastructure, helping financial firms achieve optimal performance in their data processing and trading operations while maintaining robust system reliability and speed.
The Intelligent Sensor and Power Management Platform (ISP) by IQonIC Works is engineered for sensor-driven and IoT applications that demand refined power management and efficient processing. This platform-centric solution aims to accelerate the design lifecycle, offering an integrated suite of pre-validated IP and design blocks that minimize time-to-market and development costs. ISP focuses on three core design challenges: power management, sensor interface, and software-programmable processing. It provides a comprehensive energy management framework supporting a variety of operational modes, from ultra-low power to active processing states. The platform's capability extends to harvesting and managing energy effectively, which is crucial for battery-operated or energy-scarce environments. The platform's versatility allows for scalable solutions, supporting a wide array of I/O components and processing cores such as RISC-V and ARM Cortex-M variants. It facilitates seamless expansion through industry-standard interfaces, allowing the integration of third-party components and enabling sophisticated communication and control features, ensuring adaptability and robustness in dynamically changing application environments.
The nxAccess Trading Engine is an advanced solution that harnesses FPGA technology to offer ultra-low latency and deterministic performance in trading scenarios. This engine allows users to preload orders and utilize market data to trigger and update these orders with the precision of hardware execution, complemented by the adaptability of a software interface. The nxAccess system is crafted for high-frequency trading applications, offering particular benefits for market-making strategies and arbitrage, where speed is a crucial driver of success. By leveraging FPGA technology, it mitigates the traditional costs associated with FPGA deployment while delivering high-speed algorithmic trading capabilities. One of the distinctive features of nxAccess is its ability to integrate effortlessly into existing trading infrastructures. It features dual data paths: an FPGA path optimized for low-latency and a software path for more complex processing needs, ensuring that trading strategies can be executed seamlessly across hardware and software. Moreover, nxAccess includes a pattern matcher, a lightweight market data decoder that significantly reduces latency by bypassing unnecessary data normalization and delivering critical market information directly to trading algorithms. This trading engine is particularly suited to environments demanding rapid execution and high throughput, providing tools to efficiently manage and execute orders while maintaining minimal delay from tick-to-trade. The nxAccess system is well-suited for professional trading firms focused on shaving microseconds off their trade execution times to gain market advantages. Its versatility and robust feature set provide an edge in developing sophisticated trading strategies and managing market activities with finesse.
The Mixed Radix FFT core is engineered to handle various non-radix-2 FFT lengths using combinations of radix-2, 3, 5, and 7. This flexibility allows the core to optimize performance for a breadth of applications, accommodating diverse computational requirements. Featuring medium throughput and logic usage, the core efficiently manages resources while delivering tailored FFT solutions for non-standard computational loads. Designed for both FPGA and ASIC platforms, it delivers robust performance in heterogeneous computing environments.
Menta's eFPGA IP Cores offer a robust technology for designers needing the flexibility of FPGA within the compact design of an ASIC. These cores facilitate the integration of custom logic, seamlessly merging the benefits of FPGA with the efficiency of ASIC. They enable significant power savings and security enhancements by integrating adaptable features directly within FPGA fabric, such as crypto capabilities, making them suitable for a wide range of applications, especially where security is a priority. The cores are tailor-made to meet varied application demands, allowing for post-fabrication reconfiguration without altering the hardware design. This adaptability underpins their appeal across fast-evolving industries like telecommunications and automotive sectors. Menta's eFPGA technology prioritizes scalability, empowering designers to dynamically adjust resources such as logic elements and memory blocks. This flexibility ensures that the same solution can be efficiently employed across different technologies or evolving application requirements. Furthermore, the cost-effectiveness of these cores is a major advantage, as they eliminate the need for separate FPGA chips by integrating FPGA features directly within ASIC architecture, minimizing BOM costs and overall power consumption. The innovative design of Menta's eFPGA cores incorporates state-of-the-art software capabilities through the Origami Programmer tool, which streamlines the configuration process and optimizes RTL synthesis specifically for Menta's architecture. This synergy between hardware and software ensures that eFPGA IPs are not only high-performing but also simplify the development and deployment process for end-users seeking the agility and customization provided by FPGA in a compact and efficient form.
Parallel FFT IP offers a streamlined approach to executing FFT operations, employing multiple parallel processing streams to significantly enhance throughput. Featuring a low logic and memory footprint, this IP core is tailored for deployment on high-performance FPGA systems. By utilizing a series of highly efficient parallel algorithms, it dramatically accelerates FFT processing in both small and large configurations, supporting real-time signal analysis and complex data computations efficiently.
The Load Unload FFT IP focuses on efficient data handling during Fast Fourier Transform operations. This IP core is adept at balancing high-speed data processing with minimal logic usage, ensuring swift and reliable data transfers during FFT calculations. It is optimized for FPGA and ASIC targets, making it a versatile choice for demanding signal processing applications that require a seamless flow of data.
The 10G MAC/PCS is a high-performance media access control and physical coding sublayer module optimized for ultra-low latency applications in financial trading environments. Exclusively available on the nxFramework, this IP core is designed to provide exceptional speed and performance for FPGA deployments. This MAC/PCS core is tailored for applications requiring rapid data transmission with minimal delay. It integrates seamlessly into FPGA architectures, offering a streamlined solution for managing data flow in high-frequency trading and other latency-sensitive contexts. A core component of this module is its ability to efficiently handle 10G Ethernet traffic, ensuring high-speed data processing and reduced latency. This makes it a critical asset for trading firms looking to enhance their network infrastructure and achieve superior performance metrics in trading operations.
Stellar Packet Classification Platform is tailored for high-efficiency search and sorting operations across networked systems using ACL and LPM rules. Designed to handle complex rule sets with ultra-fast lookup speeds, this platform is engineered for environments where rapid data processing and high reliability are critical. It adapts seamlessly for varied applications like firewalls, IPV4/6 routing, and Anti-DDoS systems, delivering consistent high performance even in demanding scenarios.
The 5G ORAN Base Station is designed to be a cornerstone in the next generation of mobile networking. With 5G, wireless communication will see unprecedented growth in data capacity and opportunities for novel wireless applications. This base station enhances the efficiency and coverage of mobile networks, fostering the growth of smart cities, connected devices, and industrial automation. It integrates seamlessly with various network architectures, making it a versatile component in the telecommunications sector.
The NC-NoC offers an advanced, configurable NoC solution that is both scalable and physically aware. It is designed to accommodate multiple clocking schemes, making it suitable for a wide range of applications not requiring coherency. This solution is compatible with various protocols such as AXI4/3, AHB, APB, and AXI-lite, with bus widths ranging from 32 to 2048 bits. Its layered architecture facilitates seamless integration into diverse SoC environments, providing a robust framework for efficient data routing and high system performance. The NC-NoC stands out for its capacity to support complex, multi-protocol operations, delivering reliable and high-speed interconnectivity within SoCs.
The Hybrid Ultra-Low Latency FPGA Framework from Orthogone integrates the high-speed capabilities of FPGAs with the flexibility of software development, providing an ideal solution for high-frequency trading in financial markets. By combining these elements, developers can build responsive trading systems that minimize latency without sacrificing scalability or ease of programming. This framework includes a complete suite of IP cores and development tools that facilitate rapid prototyping of ultra-low latency trading systems. It seamlessly scales with growing data and adapts to changing market conditions by integrating FPGA hardware's high-performance capabilities with software's adaptability. Excellent security features ensure reliable transactions, while expert support drives smooth implementation and ongoing optimization. It allows for high transaction throughput, reducing delays and increasing profitability for trading operations.
The FlexGen Smart Network-on-Chip (NoC) is a revolutionary approach to system connectivity within SoCs. Featuring AI-driven heuristics, FlexGen optimizes wire length, refines topology, and reduces latency to vastly improve performance. This intelligent NoC solution automates the network configuration process, ensuring seamless connectivity across diverse components within the system. FlexGen offers unmatched flexibility, accommodating varied requirements seamlessly, making it ideal for contemporary SoC designs that demand high efficiency and low latency. Its automation capabilities reduce development time significantly, saving resources and boosting productivity. Furthermore, FlexGen's adaptations to changes in design requirements or system components underscore its versatile application. In scenarios where speed and reliability are paramount, FlexGen smart NoC delivers. It assures that advanced technological demands are met without compromising on quality or performance, reinforcing its status as a leading choice for modern high-speed applications.
C-NoC represents a major advancement in coherent NoC technology, scheduled for release in the second half of 2023. It supports an array of topologies, including mesh, grid, and torus, and incorporates on-chip L3 cache to reduce latency significantly. This solution is engineered to support multiple protocols such as CHI, AXI4/3, AXI-lite, ACE, and ACE-lite, with adaptability to bus widths from 32 to 2048 bits. C-NoC's versatile design makes it a powerful option for systems that require coherence and high-speed data processing. The integration of robust caching mechanisms ensures optimized data flow and enhanced system efficiency, making it a valuable addition for sophisticated SoC designs.
MIPS Sense products focus on advancing autonomous platforms by enabling rapid data movement and processing capabilities. These engines are notably crafted for processing data from diverse sensors, seamlessly integrating and processing this information in real-time. This functionality is critical for platforms that require instantaneous decision-making, such as industrial robotics and automotive applications where sensor fusion dictates operational dynamics. The Sense Data Movement Engines are engineered to manage multiple data streams simultaneously, ensuring that even under demanding conditions, the data processed is reliable and reflective of the real-time environment. This ensures high performance through low-latency operations, significantly enhancing computational efficiency and response accuracy across complex scenarios. Specifically designed with scalable application processors, the Sense engines help in executing detailed control processes and interfacing with hardware accelerators for efficient data handling. By facilitating robust data fusion, these engines contribute to smarter automated operations, paving the way for advancements in autonomous tech and data-driven operations across various sectors.
The GL3004 serves as a crucial interface controller designed to operate effectively across diverse platforms. It supports multiple USB standards, offering versatility for devices that require efficient and fast data connection capabilities. This controller enhances the performance in computing and peripheral connectivity, ensuring seamless data transmission and interaction. Built for environments that demand high-speed data exchanges, the GL3004 is ideal for use in computing, industrial applications, and consumer electronics. Its durable design assures consistent performance even under intensive data workload conditions, making it suitable for mission-critical applications. By incorporating advanced USB interfacing techniques, the GL3004 optimizes data flow and communication between connected devices, reducing latency and enhancing operational efficiency. This IP has become integral in systems where maintaining high-speed connectivity and low power usage is a primary objective. Developers benefit from the GL3004's ability to simplify system architecture with its flexible and integrated design approach, reducing time-to-market for new products. Its reliability and performance make it a favored choice for professionals seeking robust connectivity solutions in their technology.
KMX 100G UDPIP Core implements UDP/IP protocol hardware stack that achieves high-speed communication over a LAN or a point-to-point connection, which is ideal to offload systems from demanding tasks of UDP/IP encapsulation and to enable media streaming in both FPGA and RISC designs. The core supports ARP request, reply and manages 32-entry ARP cache. ICMP ping reply is included. The core provides DHCP client engine, which can get an IP address from external DHCP servers. The 100G UDPIP Core implements V3 IGMP membership Query/Report messaging. IP jumbo packets are supported as well as UDP port number filters and VLAN. IP/UDP checksum generation and validation are implemented. They can be enabled or disabled. The MDIO bus access to external device via AXI4-Lite bus is included. The IP raw packets are supported in both TX and RX. IP fragmentation and TCP protocol hardware stack companion core are available on demand. The core supports 32 RX channels and 32 TX channels. Each of the RX channels can be configured and associated with any of five RX ports. Each of the TX channels can be used to send IP packets on any of five TX Ports. The core connects to user logic through Control write Interface and Control Read Interface of AXI4-Lite buses; five RX Dedicated Ports of AXI4-Stream buses and five TX Dedicated Ports of AXI4-Stream buses. The core connects to 100G MAC module through AXI4-Stream bus. KMX 100G MAC and PCS cores are available to KMX customers.
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