All IPs > Platform Level IP > Multiprocessor / DSP
In the realm of semiconductor IP, the Multiprocessor and Digital Signal Processor (DSP) category plays a crucial role in enhancing the processing performance and efficiency of a vast array of modern electronic devices. Semiconductor IPs in this category are designed to support complex computational tasks, enabling sophisticated functionalities in consumer electronics, automotive systems, telecommunications, and more. With the growing need for high-performance processing in a compact and energy-efficient form, multiprocessor and DSP IPs have become integral to product development across industries.
The multiprocessor IPs are tailored to provide parallel processing capabilities, which significantly boost the computational power required for intensive applications. By employing multiple processing cores, these IPs allow for the concurrent execution of multiple tasks, leading to faster data processing and improved system performance. This is especially vital in applications such as gaming consoles, smartphones, and advanced driver-assistance systems (ADAS) in vehicles, where seamless and rapid processing is essential.
Digital Signal Processors are specialized semiconductor IPs used to perform mathematical operations on signals, allowing for efficient processing of audio, video, and other types of data streams. DSPs are indispensable in applications where real-time data processing is critical, such as noise cancellation in audio devices, image processing in cameras, and signal modulation in communication systems. By providing dedicated hardware structures optimized for these tasks, DSP IPs deliver superior performance and lower power consumption compared to general-purpose processors.
Products in the multiprocessor and DSP semiconductor IP category range from core subsystems and configurable processors to specialized accelerators and integrated solutions that combine processing elements with other essential components. These IPs are designed to help developers create cutting-edge solutions that meet the demands of today’s technology-driven world, offering flexibility and scalability to adapt to different performance and power requirements. As technology evolves, the importance of multiprocessor and DSP IPs will continue to grow, driving innovation and efficiency across various sectors.
The 2nd Generation Akida processor introduces groundbreaking enhancements to BrainChip's neuromorphic processing platform, particularly ideal for intricate network models. It integrates eight-bit weight and activation support, improving energy efficiency and computational performance without enlarging model size. By supporting an extensive application set, Akida 2nd Generation addresses diverse Edge AI needs untethered from cloud dependencies. Notably, Akida 2nd Generation incorporates Temporal Event-Based Neural Nets (TENNs) and Vision Transformers, facilitating robust tracking through high-speed vision and audio processing. Its built-in support for on-chip learning further optimizes AI efficiency by reducing reliance on cloud training. This versatile processor fits perfectly for spatio-temporal applications across industrial, automotive, and healthcare sectors. Developers gain from its Configurable IP Platform, which allows seamless scalability across multiple use cases. The Akida ecosystem, including MetaTF, offers developers a strong foundation for integrating cutting-edge AI capabilities into Edge systems, ensuring secure and private data processing.
The NMP-750 is designed as a cutting-edge performance accelerator for edge computing, tailored to address challenges in sectors like automotive, telecommunications, and smart factories. This product offers ample support for mobility, autonomous control, and process automation, setting a benchmark in high-performance computing for varied applications. With a processing power of up to 16 TOPS and 16 MB of local memory, it supports RISC-V/Arm Cortex-R or A 32-bit CPUs for substantial computational tasks. Its architecture supports a rich set of applications, including multi-camera stream processing and energy management, enabled through its AXI4 128-bit interfaces that manage extensive data traffic efficiently. This accelerator is particularly suited for complex scenarios such as spectral efficiency and smart building management, offering unparalleled performance capabilities. Designed for scalability and reliability, the NMP-750 reaches beyond traditional computing barriers, ensuring outstanding performance in real-time applications and next-gen technology deployments.
The NMP-750 is designed as a cutting-edge performance accelerator for edge computing, tailored to address challenges in sectors like automotive, telecommunications, and smart factories. This product offers ample support for mobility, autonomous control, and process automation, setting a benchmark in high-performance computing for varied applications. With a processing power of up to 16 TOPS and 16 MB of local memory, it supports RISC-V/Arm Cortex-R or A 32-bit CPUs for substantial computational tasks. Its architecture supports a rich set of applications, including multi-camera stream processing and energy management, enabled through its AXI4 128-bit interfaces that manage extensive data traffic efficiently. This accelerator is particularly suited for complex scenarios such as spectral efficiency and smart building management, offering unparalleled performance capabilities. Designed for scalability and reliability, the NMP-750 reaches beyond traditional computing barriers, ensuring outstanding performance in real-time applications and next-gen technology deployments.
The NMP-350 is specifically designed to serve as a cost-effective endpoint accelerator with a strong emphasis on low power consumption, making it ideal for various applications in AIoT, automotive, and smart appliances. This product is equipped with a robust architecture to facilitate myriad applications, such as driver authentication, digital mirrors, and predictive maintenance, while ensuring efficient resource management. Capable of delivering up to 1 TOPS, the NMP-350 integrates up to 1 MB of local memory, supporting RISC-V/Arm Cortex-M 32-bit CPU cores. It utilizes a triple AXI4 interface, each with a capacity of 128 bits, to manage host, CPU, and data traffic seamlessly. This architecture supports a host of applications in wearables, Industry 4.0, and health monitoring, adding significant value to futuristic technology solutions. Strategically targeting markets like AIoT/sensors and smart appliances, the NMP-350 positions itself as a favored choice for developing low-cost, power-sensitive device solutions. As industries gravitate toward energy-efficient technologies, products like NMP-350 offer a competitive edge in facilitating smart, green development processes.
WAVE6 represents the pinnacle of multi-standard video coding. It supports AV1 encoding, known for its efficient use of bandwidth and high compression quality. Featuring a simple architecture, it boasts a single-clock domain that synchronizes the entropy and video codec engines on the fly. The efficiency of WAVE6 is further enhanced by its power-efficient design, which minimizes consumer energy requirements through effective clock gating. It serves various sectors, including data centers and surveillance systems, operating with a remarkable performance of up to 8K60fps @ 1GHz. The integration of advanced coding techniques ensures a reduced need for external memory, thanks to the proprietary CFrame lossless compression.
A2e Technologies offers a cutting-edge H.264 FPGA Encoder and CODEC that promises the industry's smallest and fastest solution with ultra-low latency. This core is ITAR-compliant and adaptable, capable of delivering a 1080p60 video stream while retaining a minimal footprint. The H.264 core is engineered to adapt to unique pixel depths and resolutions, leveraging a modular design that allows for seamless integration into a variety of FPGA environments. Supporting both I and P frames, this encoder ensures robust video compression with customizable configurations for various applications. The core's flexibility extends to its ability to handle multiple video streams with differing sizes or compression ratios simultaneously. Its fully synchronous design supports resolutions up to 4096 x 4096, illustrating its capacity to manage high-definition sources effectively. The flexibility in design permits its application across FPGAs from numerous manufacturers, including Xilinx and AMD, making it versatile for diverse project requirements. With enhancements like an improved AXI wrapper for better integration and significant reductions in RAM needs for raster-to-macroblock transformations, A2e's H.264 Encoder is equipped for high performance. It supports a variety of encoding styles with a processing rate of 1.5 clocks per pixel and includes comprehensive deliverables such as FPGA-specific netlists and testing environments to ensure a swift and straightforward deployment.
The High Performance RISC-V Processor from Cortus represents the forefront of high-end computing, designed for applications demanding exceptional processing speeds and throughput. It features an out-of-order execution core that supports both single-core and multi-core configurations for diverse computing environments. This processor specializes in handling complex tasks requiring multi-threading and cache coherency, making it suitable for applications ranging from desktops and laptops to high-end servers and supercomputers. It includes integrated vector and AI accelerators, enhancing its capability to manage intensive data-processing workloads efficiently. Furthermore, this RISC-V processor is adaptable for advanced embedded systems, including automotive central units and AI applications in ADAS, providing enormous potential for innovation and performance across various markets.
Cortus's Automotive AI Inference SoC is a breakthrough solution tailored for autonomous driving and advanced driver assistance systems. This SoC combines efficient image processing with AI inference capabilities, optimized for city infrastructure and mid-range vehicle markets. Built on a RISC-V architecture, the AI Inference SoC is capable of running specialized algorithms, akin to those in the Yolo series, for fast and accurate image recognition. Its low power consumption makes it suitable for embedded automotive applications requiring enhanced processing without compromising energy efficiency. This chip demonstrates its adequacy for Level 2 and Level 4 autonomous driving systems, providing a comprehensive AI-driven platform that enhances safety and operational capabilities in urban settings.
The Chimera GPNPU by Quadric is a versatile processor specifically designed to enhance machine learning inference tasks on a broad range of devices. It provides a seamless blend of traditional digital signal processing (DSP) and neural processing unit (NPU) capabilities, which allow it to handle complex ML networks alongside conventional C++ code. Designed with a focus on adaptability, the Chimera GPNPU architecture enables easy porting of various models and software application programming, making it a robust solution for rapidly evolving AI technologies. A key feature of the Chimera GPNPU is its scalable design, which extends from 1 to a remarkable 864 TOPs, catering to applications from standard to advanced high-performance requirements. This scalability is coupled with its ability to support a broad range of ML networks, such as classic backbones, vision transformers, and large language models, fulfilling various computational needs across industries. The Chimera GPNPU also excels in automotive applications, including ADAS and ECU systems, due to its ASIL-ready design. The processor's hybrid architecture merges Von Neumann and 2D SIMD matrix capabilities, promoting efficient execution of scalar, vector, and matrix operations. It boasts a deterministic execution pipeline and extensive customization options, including configurable instruction caches and local register memories that optimize memory usage and power efficiency. This design effectively reduces off-chip memory accesses, ensuring high performance while minimizing power consumption.
The NMP-550 stands out as a performance-focused accelerator catered towards applications necessitating high efficiency, especially in demanding fields such as automotive, drones, and AR/VR. This technology caters to various application needs, including driver monitoring, image/video analytics, and heightened security measures through its powerful architecture and processing capability. Boasting a significant computation potential of up to 6 TOPS, the NMP-550 includes up to 6 MB of local memory. Featuring RISC-V/Arm Cortex-M or A 32-bit CPUs, the product ensures robust processing for advanced applications. The triple AXI4 interface provides a seamless 128-bit data exchange across hosts, CPUs, and data channels, magnifying flexibility for technology integrators. Ideal for medical devices, this product also expands its utility into security and surveillance, supporting crucial processes like super-resolution and fleet management. Its comprehensive design and efficiency make it an optimal choice for applications demanding elevated performance within constrained resources.
Building on its predecessor, the WAVE5 series offers robust multi-standard video encoding capabilities with an established reputation within media and entertainment sectors. WAVE5 is versatile, boasting formats like HEVC and AVC, and delivers outstanding performance, with outputs like 4K240fps at 1GHz. It has been fine-tuned to handle complex multi-instance operations by efficiently managing data transfer and conversion tasks. Its ability to maintain high visual fidelity while offering low installation costs makes it a strategic choice for multiple application fields such as automotive and mobile entertainment. The use of secondary AXI ports and a fully integrated rotation and scaling mechanic add to its versatility.
InCore's RISC-V Core-hub Generators are a revolutionary tool designed to give developers unparalleled control over their SoC designs. These generators enable the customization of core-hub configurations down to the ISA and microarchitecture level, promoting a tailored approach to chip creation. Built around the robustness of the RISC-V architecture, the Core-hub Generators support versatile application needs, allowing designers to innovate without boundaries. The Core-hub concept is pivotal to speeding up SoC development by offering a framework of diverse cores and optimized fabric components, including essential RISC-V UnCore features like PLICs, Debug, and Trace components. This systemic flexibility ensures that each core hub aligns with specific customer requirements, providing a bespoke design experience that enhances adaptability and resource utilization. By integrating efficient communication protocols and optimized processing capabilities, InCore's Core-hub Generators foster seamless data exchange across modules. This is essential for developing next-gen semiconductor solutions that require both high performance and security. Whether used in embedded systems, high-performance industrial applications, or sophisticated consumer electronics, these generators stand as a testament to InCore's commitment to innovation and engineering excellence.
The Ultra-Low-Power 64-Bit RISC-V Core by Micro Magic represents a significant advancement in energy-efficient computing. This core, operating at an astonishingly low 10mW while running at 1GHz, sets a new standard for low-power design in processors. Micro Magic's proprietary methods ensure that this core maintains high performance even at reduced voltages, making it a perfect fit for applications where power conservation is crucial. Micro Magic's RISC-V core is designed to deliver substantial computational power without the typical energy costs associated with traditional architectures. With capabilities that make it suitable for a wide array of high-demand tasks, this core leverages sophisticated design approaches to achieve unprecedented power efficiency. The core's impressive performance metrics are complemented by Micro Magic's specialized tools, which aid in integrating the core into larger systems. Whether for embedded applications or more demanding computational roles, the Ultra-Low-Power 64-Bit RISC-V Core offers a compelling combination of power and performance. The design's flexibility and power efficiency make it a standout among other processors, reaffirming Micro Magic's position as a leader in semiconductor innovation. This solution is poised to influence how future processors balance speed and energy usage significantly.
The Dynamic Neural Accelerator II by EdgeCortix is a pioneering neural network core that combines flexibility and efficiency to support a broad array of edge AI applications. Engineered with run-time reconfigurable interconnects, it facilitates exceptional parallelism and efficient data handling. The architecture supports both convolutional and transformer neural networks, offering optimal performance across varied AI use cases. This architecture vastly improves upon traditional IP cores by dynamically reconfiguring data paths, which significantly enhances parallel task execution and reduces memory bandwidth usage. By adopting this approach, the DNA-II boosts its processing capability while minimizing energy consumption, making it highly effective for edge AI applications that require high output with minimal power input. Furthermore, the DNA-II's adaptability enables it to tackle inefficiencies often seen in batching tasks across other IP ecosystems. The architecture ensures that high utilization and low power consumption are maintained across operations, profoundly impacting sectors relying on edge AI for real-time data processing and decision-making.
The Software-Defined High PHY from AccelerComm is an adaptable solution designed for ARM processor architectures, providing versatile platform support. This PHY can function with or without hardware acceleration, catering to varying demands in capacity and power for diverse applications. It seamlessly integrates into O-RAN environments and can be tailored to optimize performance, aligning with specific network requirements. This versatile solution capitalizes on the strengths of ARM processors and offers additional flexibility through optional hardware accelerations. By providing a scalable framework, the Software-Defined High PHY supports efficient deployment, regardless of the network size or complexity. This adaptability ensures that network managers can configure the PHY to meet specific performance objectives, maximizing throughput while minimizing power consumption. Esteemed for its flexibility and ease of integration, this solution exemplifies AccelerComm's commitment to delivering high-caliber, platform-independent PHY solutions. It empowers network developers to tailor their setups, thus enhancing performance metrics like latency and spectral efficiency.
VSORA's Tyr Superchip epitomizes high-performance capabilities tailored for the demanding worlds of autonomous driving and generative AI. With its advanced multi-core architecture, this superchip can execute any algorithm efficiently without relying on CUDA, which promotes versatility in AI deployment. Built to deliver a seamless combination of AI and general-purpose processing, the Tyr Superchip utilizes sparsity techniques, supporting quantization on-the-fly, which optimizes its performance for a wide array of computational tasks. The Tyr Superchip is distinctive for its ability to support the simultaneous execution of AI and DSP tasks, selectable on a layer-by-layer basis, which provides unparalleled flexibility in workload management. This flexibility is further complemented by its low latency and power-efficient design, boasting performance near theoretical maximums, with support for next-generation algorithms and software-defined vehicles (SDVs). Safety is prioritized with the implementation of ISO26262/ASIL-D features, making the Tyr Superchip an ideal solution for the automotive industry. Its hardware is designed to handle the computational load required for safe and efficient autonomous driving, and its programmability allows for ongoing adaptations to new automotive standards and innovations.
The NPU, part of the ENLIGHT series by OPENEDGES Technology, is designed as a deep learning accelerator focusing on inferencing computations with superior efficiency and compute density. Developed for high-performance edge computing, this neural processing unit supports a range of operations pertinent to deep neural networks, including convolution and pooling, providing state-of-the-art capability in both power and performance. The NPU's architecture is based on mixed-precision computation using 4-/8-bit quantization which significantly reduces DRAM traffic, thereby optimizing bandwidth utilization and power consumption. Its design incorporates an advanced vector engine optimized for modern deep neural network architectures, enriching its ability to modernize and scale with evolving AI workloads. Accompanying the hardware capabilities, the NPU offers a comprehensive software toolkit featuring network conversion, quantization, and simulation tools. This suite is built for compatibility with mainstream AI frameworks and ensures seamless integration and efficiency in real-world applications ranging from automotive systems to surveillance.
The Cortus ULYSS range of automotive microcontrollers is engineered to meet the demands of sophisticated automotive applications, extending from body control to ADAS and infotainment systems. Utilizing a RISC-V architecture, these microcontrollers provide high performance and efficiency suitable for automotive tasks. Each variant within the ULYSS family caters to specific automotive functions, with capabilities ranging from basic energy management to complex networking and ADAS processing. For instance, the ULYSS1 caters to body control applications with a single-core CPU, while the ULYSS3 provides robust networking capabilities with a quad-core, lockstep MPU operating up to 1.5 GHz. The ULYSS line is structured to offer scalability and flexibility, allowing automotive manufacturers to integrate these solutions seamlessly into various components of a vehicle's electronic system. This focus on adaptability helps Cortus provide both a cost-effective and high-performance solution for its automotive partners.
The eSi-3264 processor core provides advanced DSP functionality within a 32/64-bit architecture, enhanced by Single Instruction, Multiple Data (SIMD) operations. This high-performance CPU is crafted to excel in tasks demanding significant digital signal processing power, such as audio processing or motion control applications. It incorporates advanced SIMD DSP extensions and floating point support, optimizing the core for parallel data processing. The architecture supplies options for extensive custom configurations including instruction and data caches to tailor performance to the specific demands of high-speed and low-power operations. The eSi-3264's hardware debug capabilities combined with its versatile pipeline make it an ideal match for high-precision computing environments where performance and efficiency are crucial. Its ability to handle complex arithmetic operations efficiently with minimal silicon area further cements its position as a leading solution in DSP-focused applications.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
The M3000 Graphics Processor is DMP's offering for high-power 3D graphics processing designed for energy-efficient performance. It features sophisticated graphics processing capabilities based on DMP’s proprietary Musashi 3D graphics architecture. This architecture is tailored to deliver state-of-the-art graphics performance, specifically aligning with complex computation requirements found in VR and AR applications, alongside other visual computing demands. The M3000 is crafted to achieve optimal Power, Performance, and Area (PPA) metrics, supporting OpenGL ES 3.0 to ensure compatibility with cutting-edge visual processing standards. Its adaptability stems from a flexible shader cluster architecture that can be adjusted to meet varying client needs for performance and size. This flexibility extends to its implementational capacity across diverse devices such as ASICs, ASSPs, SoCs, and more. Technically, the M3000 supports outputs at resolutions reaching 4k x 2k, with interfaces like AXI 3/4 and APB for communication, suited for numerous applications ranging from IoT devices to automotive infotainment systems. This processor redefines efficiency and power in graphics acceleration, rendered for seamless integration into modern HMI systems.
The Spiking Neural Processor T1 by Innatera is a revolutionary microcontroller designed to handle sensory processing with extreme efficiency. This processor is specifically crafted to operate at ultra-low power levels, below 1 milliwatt, yet it delivers exceptional performance in pattern recognition tasks right at the sensor edge. Utilizing a neuromorphic architecture, it processes sensor data in real time to identify patterns such as audio signals or movements, significantly outperforming traditional processing methods in both speed and power consumption. Engineered to function in always-on operation modes, this microcontroller is critical for applications where maintaining continuous operation is essential. Its design offloads processing tasks from the main application processor, allowing for dedicated computation of sensor data. This includes conditioning, filtering, and classification tasks, ensuring they are carried out efficiently within the strictest power limits. With its ability to be integrated with various sensors, the Spiking Neural Processor T1 empowers devices to achieve advanced functionalities such as presence detection, touch-free interfaces, and active monitoring in wearable devices. This product supports a comprehensive range of applications through its innovative approach to sensor data handling, leveraging the unique capabilities of spiking neural networks to drive cognitive processing in less power-intensive environments.
The Yitian 710 processor is a flagship Arm server chip developed by T-Head. It utilizes advanced architecture to deliver exceptional performance and bandwidth, supporting the latest Armv9 instruction set. Constructed with a 2.5D packaging, the processor integrates two dies, boasting a staggering 60 billion transistors. Designed for high-efficiency computing, it includes 128 high-performance Armv9 CPU cores. Each core encompasses a 64KB level one instruction cache, a 64KB level one data cache, and a shared 1MB level two cache. This architecture supports extensive on-chip memory including a 128MB system cache, ensuring rapid data access and processing.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
SiFive Automotive E6-A reflects a significant step forward for RISC-V in the automotive domain, emphasizing safety and performance. The E6-A series is designed with automotive-grade robustness, adhering to modern functional safety standards such as ISO26262 ASIL B. This series is tailored to meet the stringent demands of contemporary automotive applications, including advanced driver-assistance systems (ADAS) and infotainment. The 32-bit E6-A processors are particularly optimized for achieving balanced power and performance metrics, critical for real-time in-vehicle applications. These processors support functional safety requirements and are built to operate effectively within the constrained environments typical of automotive systems. With support for secure, deterministic processing, the E6-A series fosters enhanced security and performance in vehicles, ensuring that these processes can be executed reliably and efficiently. SiFive collaborates closely with automotive OEMs to ensure their solutions align well with the industry's future technology roadmaps.
Trilinear’s Cobra for the Xilinx Kintex-7 Platform is a development solution tailored to enhance the performance of Xilinx’s FPGA technology. This platform is designed to accelerate the development cycle by providing a robust and adaptable foundation for complex computing tasks. The Cobra platform is engineered to support a wide array of applications, making it highly beneficial for developers aiming to innovate within an FPGA framework. Its design facilitates rapid prototyping and efficient deployment, essential for fast-paced development environments. Leveraging the power of the Kintex-7, users can execute computationally intensive processes while maintaining high efficiency and reliability. As part of Trilinear's developmental toolkit, Cobra stands out for its flexibility, making it an excellent choice for complex and varied use cases in the semiconductor industry. It reflects Trilinear’s commitment to providing cutting-edge tools that streamline development processes, allowing for greater innovation in FPGA design and implementation.
The RISC-V Core IP from AheadComputing is engineered to deliver high performance while maintaining flexibility and efficiency in design. The open specification architecture allows users to tailor the core to meet diverse application demands, ensuring adaptability across various computing environments. This core IP is ideal for applications requiring customization and optimization, offering a robust solution for modern challenges in computing. Facilitated by a standards-based approach, AheadComputing’s RISC-V Core IP ensures seamless integration and compatibility, supporting a wide range of interfaces and functionalities. This extensibility makes it an excellent choice for projects where quick time-to-market and cost efficiency are critical factors. Moreover, the architecture is designed to support progressive enhancements and iterations, staying relevant in the fast-paced technology world. Particularly advantageous for embedded systems and consumer electronics, the RISC-V Core IP offers advanced processing capabilities without compromising on power efficiency. As the industry moves towards more open structures, this IP serves as a pivotal component in developing next-generation computing solutions.
The SiFive Performance family of RISC-V processors targets maximum throughput and efficiency for environments including web servers and multimedia processing. These processors come in configurations ranging from three to six wide Out-of-Order (OoO) cores, with dedicated vector engines designed for AI workloads. By providing energy-efficiency without compromising on performance, the SiFive Performance Cores are tailored to meet the needs of diverse high-performance applications. These cores are scalable, offering configurations that can extend up to 256 cores. This scalability is essential for data centers and mobile infrastructures alike, where performance and efficiency are paramount. Key technical features include a six-wide out-of-order core architecture, RAS functionality, and a scalable core cluster. In datacenters and beyond, they facilitate the development of a diverse range of applications, including big data analytics and enterprise infrastructure solutions. SiFive's commitment to high-performance RISC-V processors caters to growing demands for performance and area-efficient application processors.
VisualSim Architect serves as a comprehensive platform for modeling and simulating electronic systems. It's designed to bridge the gap between system specifications, enhancing the model-based system engineering process. It provides crucial timing and power simulations that help identify potential bottlenecks early in development, thus optimizing system performance and functionality. Besides streamlining the specification process, it supports extensive use-case exploration and architecture optimization on various platforms. With its capacity to generate detailed reports on performance and power, engineers can gauge system efficiency accurately. VisualSim Architect's powerful capabilities significantly reduce the risk of design errors and expedite the development cycle. This tool is especially beneficial for semiconductor design, where precise performance and power predictions are crucial.
The AON1100 represents AONDevices' flagship in edge AI solutions aimed at voice and sensor applications. Its design philosophy centers on providing high accuracy combined with super low-power consumption. This chip shines when processing tasks such as voice commands, speaker identification, and sensor data integration. With a power rating of less than 260μW, the AON1100 maintains operational excellence even in environments with sub-0dB Signal-to-Noise Ratios. Its performance is highly appreciated in always-on devices, making it suitable for smart home applications, wearables, and automotive systems that demand real-time responsiveness and minimal energy draw. The AON1100 incorporates streamlined algorithms that enhance its sensor fusion capabilities, paving the way for smarter device contexts beyond traditional interactions. Its RISC-V support adds an additional layer of flexibility and compatibility with a wide range of applications, contributing significantly to the chip's adaptability and scalability across various domains.
The SAKURA-II AI Accelerator is a state-of-the-art energy-efficient AI processing unit designed to meet the demanding needs of generative AI applications. Boasting up to 60 TOPS performance, this accelerator is built on EdgeCortix's patented Dynamic Neural Accelerator architecture that allows high efficiency and low power consumption in edge AI tasks. It supports a wide array of models including Llama 2, Stable Diffusion, ViT, and large transformer and convolutional networks, typically operating within an 8W power envelope. Offering enhanced DRAM bandwidth and a maximum memory capacity of 32GB, SAKURA-II is optimized for real-time data streaming and efficient handling of large language models (LLMs) and vision-based AI workloads. This accelerator achieves exceptionally high AI compute utilization and provides robust energy-efficient performance, making it ideal for advanced applications in vision, language, audio, and more. The accelerator is available in modular M.2 and PCIe card formats, facilitating seamless integration into existing systems. These form factors ensure that the SAKURA-II can be effortlessly integrated into space-constrained or power-limited environments, providing the best choice for both development and deployment phases of edge AI initiatives.
The AI Inference Platform by SEMIFIVE is designed to accelerate artificial intelligence applications with optimized compute capabilities. It supports a variety of frameworks and offers robust integration with existing systems to streamline advanced data processing tasks. This platform is engineered to enhance performance efficiency, offering significant power savings and minimizing latency, thus addressing the demanding needs of AI-driven markets. Additionally, it boasts a modular design to accommodate updates and scalability.
EnSilica's eSi-ADAS is a comprehensive radar accelerator suite designed to enhance the capabilities and performance of radar systems. It is particularly suited for automotive, drone, and UAV applications where quick, responsive situational awareness is critical. This radar co-processor engine enables rapid data processing, contributing significantly to vehicle safety systems and providing a real-time operational advantage. It boasts efficient integration with existing systems, maximizing the benefits of advanced digital signal processing (DSP) techniques tailored to radar applications. By accelerating radar algorithm execution, this IP helps designers create more efficient detection systems and improve the operational reliability of advanced driver-assistance systems (ADAS).
The Digital Radio (GDR) from GIRD Systems is an advanced software-defined radio (SDR) platform that offers extensive flexibility and adaptability. It is characterized by its multi-channel capabilities and high-speed signal processing resources, allowing it to meet a diverse range of system requirements. Built on a core single board module, this radio can be configured for both embedded and standalone operations, supporting a wide frequency range. The GDR can operate with either one or two independent transceivers, with options for full or half duplex configurations. It supports single channel setups as well as multiple-input multiple-output (MIMO) configurations, providing significant adaptability in communication scenarios. This flexibility makes it an ideal choice for systems that require rapid reconfiguration or scalability. Known for its robust construction, the GDR is designed to address challenging signal processing needs in congested environments, making it suitable for a variety of applications. Whether used in defense, communications, or electronic warfare, the GDR's ability to seamlessly switch configurations ensures it meets the evolving demands of modern communications technology.
The Tachyum Prodigy Universal Processor is a pioneering technology, serving as the world's first universal processor. It seamlessly integrates the capabilities of CPUs, GPGPUs, and TPUs into a single architectural framework. This innovation drastically enhances performance, energy efficiency, and space utilization, making it a favored choice for AI, high-performance computing, and hyperscale data centers. Designed to operate at lower costs than traditional processors, Prodigy provides a notable reduction in the total cost of ownership for data centers, while simultaneously delivering superior execution speed, surpassing conventional Xeon processors. The processor enables the transformation of data centers into integrated computational environments, supporting an array of applications from basic processing tasks to advanced AI training and inference. The Prodigy processor also supports a wide range of applications, allowing developers to run existing software without modifications. This flexibility is complemented by the ability to lower energy consumption significantly, making it an environmental ally by decreasing carbon emissions. The processor's design strategy sidesteps silicon underutilization, fostering an ecosystem for energy-efficient simulations and data analysis. This sustainability focus is vital as high-performance computing demands continue to escalate, making Prodigy a forward-thinking choice for enterprises focused on green computing solutions.
The Speedster7t FPGAs are renowned for their optimization for high-data-rate applications. Engineered to overcome the limitations faced by conventional FPGA architectures, they provide significant enhancements in bandwidth, making them ideal for complex, data-intensive tasks. The unique architecture of Speedster7t mitigates traditional bottlenecks by incorporating features such as PCIe Gen5, 400G Ethernet, and support for the latest memory interfaces like DDR4 and GDDR6, ensuring swift processing and data transfer for demanding applications. These FPGAs cater to a range of fields including AI, machine learning, networking, and 5G infrastructure. Their design includes an innovative Network-on-Chip (NoC) architecture that effectively manages data communication internally, ensuring higher throughput and lower latency. This makes Speedster7t devices particularly suited for applications requiring extensive data crunching and fast interconnectivity. Furthermore, Speedster7t FPGAs are built to accommodate modern design challenges. They integrate seamlessly with Achronix's ACE design tools, providing users with a cohesive environment for developing high-performance systems. The FPGAs are supported by extensive documentation and technical support, making them an accessible choice for industries aiming for robust, scalable solutions in high-performance computing contexts.
The ZIA DV700 Series represents a sophisticated AI processing solution, optimized for a broad range of data types such as images and videos. This product line offers a unique combination of high inference speed and precision, effectively balancing real-time processing, safety, and privacy requirements for edge-based AI systems. Offering support for deep neural network (DNN) models, this series allows seamless inference processing, essential for applications requiring device independence and reliable AI functioning. The core of the ZIA DV700 lies in its ability to handle inference tasks with multiple AI models simultaneously. Known for its Hardware architecture, the DV700 supports a full suite of models like MobileNet and Yolo v3, ensuring robust object detection and segmentation processes. Moreover, it provides a development environment, featuring SDKs and tools compatible with standard AI frameworks, enabling easy model integration and processing tasks. Distinct features of the DV700 include its use of FP16 precision for floating-point computations, retaining the high accuracy rates established during model training from PC or cloud-based servers. As a result, it is an ideal choice for autonomous driving applications and robotics systems, where AI interpretation efficiency directly correlates with system safety and dependability. By facilitating seamless AI inference without retraining models, the DV700 series marks a significant leap in inference processing efficiency and versatility for varied model structures.
SEMIFIVE's AIoT Platform is crafted for the burgeoning Internet of Things market, combining artificial intelligence with IoT capabilities to create smart, interconnected systems. The platform integrates powerful AI processors with IoT modules that enhance machine learning capabilities at the edge, delivering enhanced data analytics and real-time processing. It is designed for ease of deployment and flexibility, ensuring quick adaptation to ever-evolving IoT environments. This integration is optimized for power efficiency and cost-effectiveness, making it an ideal solution for large-scale AIoT implementations.
The Catalyst-GPU series heralds a new era of computing flexibility and power in the PXIe/CPCIe arena with its integration of NVIDIA Quadro T600 and T1000 GPUs. These modules offer outstanding compute acceleration and significant graphics capabilities, crucial for detailed signal processing and AI-driven tasks, making them indispensable for Modular Test & Measurement and Electronic Warfare applications. Boasting a significant performance gain, the Catalyst-GPU sets the stage for seamless, real-time processing abilities across a range of programming environments including MATLAB, Python, and popular AI frameworks. With multi-teraflop capabilities, the Catalyst-GPU ensures that even the most computationally demanding processes are handled with precision, thereby eliminating bottlenecks in data acquisition and computational tasks. Different models within this lineup are tailored to diverse application needs, maintaining ease of programmatic interaction and integration across both Windows and Linux platforms. This adaptability, coupled with a focus on cost-effective solutions, positions the Catalyst-GPU as a leading candidate for industries looking to enhance their AI application infrastructures.
Dyumnin's RISCV SoC is built around a robust 64-bit quad-core server class RISC-V CPU, offering various subsystems that cater to AI/ML, automotive, multimedia, memory, and cryptographic needs. This SoC is notable for its AI accelerator, including a custom CPU and tensor flow unit designed to expedite AI tasks. Furthermore, the communication subsystem supports a wide array of protocols like PCIe, Ethernet, and USB, ensuring versatile connectivity. As for the automotive sector, it includes CAN and SafeSPI IPs, reinforcing its utility in diverse applications such as automotive systems.
The Trifecta-GPU series by RADX Technologies represents a leap forward in processing power with the integration of NVIDIA RTX A2000 Embedded GPUs. Designed specifically for high-demand tasks, these COTS PXIe/CPCIe GPU Modules deliver remarkable compute acceleration through 8.3 FP32 TFLOPS performance, making them ideal for advanced signal processing and machine learning inference applications. Enhanced by its use of MATLAB, Python, and C/C++ programming environments, the Trifecta-GPU is well-suited for both Windows and Linux operating systems, providing maximum versatility in deployment. A hallmark of the Trifecta-GPU is its adaptability to various PXIe chassis configurations, making it an excellent fit for both single and dual-slot requirements, accommodating legacy and modern setups alike. Its peak performance is over 20 times more powerful than typical FPGA modules, underlining its pioneering place in the industry. This makes the Trifecta-GPU exceptionally capable in scenarios requiring extensive data analysis and AI-driven tasks. This prominent GPU option offers features like arbitrary length FFTs and exceptional machine learning support—attributes that positions it as a critical tool for endeavors such as signal classification and geolocation. Its BAA & TAA compliant design, combined with a highly competitive price-per-performance metric, makes the Trifecta-GPU an accessible yet powerful choice for those working in sophisticated test and measurement applications.
The TSP1 Neural Network Accelerator from Applied Brain Research is a cutting-edge AI solution built to handle complex AI workloads with remarkable efficiency. Designed specifically for battery-powered devices, this chip excels in low-power operations while processing extensive neural network tasks. At its core, the TSP1 integrates state-of-the-art processing capabilities tailored for time series data, essential for applications like natural voice interfaces and bio-signal classification. This innovative chip is notable for its energy efficiency, consuming less than 10mW for complex AI tasks, making it an ideal solution for energy-conscious applications. Furthermore, it supports an array of sensor signal applications, ensuring versatile functionality across different domains including AR/VR, smart home automation, and medical wearables. By incorporating the Legendre Memory Unit, a proprietary advanced state-space neural network model, the TSP1 achieves superior data efficiency compared to traditional network architectures. ABR’s TSP1 stands out for its ability to perform powerful AI inferences with low latency, essential for real-time applications. It supports a wide range of interfaces, making it suitable for diverse integration scenarios, from voice recognition to industrial automation. Additionally, the chip's optimized hardware is key for algorithm scaling, facilitating smooth processing of larger neural models without compromising speed or performance.
TUNGA emerges as a revolutionary multi-core SoC integrating RISC-V cores with posit arithmetic capabilities. This solution is specifically architected for enhancing high-performance computing (HPC) and artificial intelligence workloads by leveraging the advantages of posit data types. As data centers struggle with the limitations of traditional number formats, TUNGA offers improved accuracy and efficiency, transforming real-number calculations with its innovative RISC-V foundation. This cutting-edge SoC includes the QUIRE accumulator, adept at executing precise dot products, crucial for delivering high-accuracy computations across extensive datasets. TUNGA's design incorporates reconfigurable FPGA gates, offering adaptability in critical function accelerations tailored for datacenter tasks. This adaptability extends to managing unique data types, thereby expediting AI training and inference. TUNGA stands out for its capability to streamline applications such as cryptography and AI support functions, making it a vital tool in pushing data center technologies to new horizons.
The EMSA5-FS is a 32-bit Functional Safety Processor built on the RISC-V architecture, specifically tailored for applications requiring functional safety certification. Equipped with an ISO 26262 ASIL-D Ready certificate, the processor excels in environments where safety is paramount. The EMSA5-FS features a five-stage pipeline with optional L0 cache and supports a comprehensive range of RISC-V ISA options. The design incorporates advanced safety features such as Dual Modular Redundancy (DMR), Error Correcting Code (ECC), and sample reset modules, making it robust against faults.\n\nThis processor is highly customizable, allowing users to select specific ISA options that best apply to their application, including support for embedded and vector instructions. The deliverables for the EMSA5-FS include a comprehensive safety manual and diagnostic analysis reports, providing users with all necessary documentation to proceed with certification processes.\n\nPerformance-wise, the EMSA5-FS is scalable, with DMR implementations starting at 40k gates and triple TMR setups from 60k gates, enabling high-frequency operation over 1GHz on advanced nodes. This makes it particularly suited for use in automotive and industrial sectors where safety and reliability are crucial.
This specialized radar DSP accelerator integrates with a RISC-V core to provide unmatched processing speeds for critical applications like ADAS. Designed for flexibility, hypr_risc enables adaptable configurations applicable to a range of systems, while offering significant savings on size and power. RISC-V's open architecture allows for extensive customization, fueling innovation in embedded computing environments.
The MGNSS IP Core offered by Accord Software and Systems is a sophisticated silicon-proven core designed to facilitate the integration of GNSS capabilities into SoCs used in automotive, precision, and IoT applications. This core is designed to support multi-constellation and multi-frequency GNSS operations, making it highly versatile for a variety of uses. It offers a high level of configurability to accommodate both existing and future GNSS signals, allowing it to operate in parallel or sequential modes depending on the specific application requirements. This flexibility ensures that developers can optimize the core's functionality for the specific requirements of their end products. One of the key features of the MGNSS IP Core is its ability to process input from two RF channels, providing dual-frequency GNSS capabilities which contribute significantly to enhancing accuracy and reducing acquisition time. The core is also equipped with advanced interference rejection features, enabling it to maintain performance in environments that are subject to signal disturbances. This makes it particularly suitable for applications that cannot afford to have compromised performances, such as automotive navigation systems and precision surveying tools. The baseband architecture of the MGNSS IP Core is designed for efficient power consumption, with options for low sampling rates and power-down modes that are beneficial for portable and battery-dependent devices. It supports a wide range of GNSS frequencies, including those from GPS, Galileo, GLONASS, BeiDou, QZSS, IRNSS, and SBAS, ensuring broad applicability across global markets. Furthermore, the core's design adheres to AHB standards, simplifying integration with other system components and enhancing the overall efficiency of the solution.
The Vega eFPGA is a flexible programmable solution crafted to enhance SoC designs with substantial ease and efficiency. This IP is designed to offer multiple advantages such as increased performance, reduced costs, secure IP handling, and ease of integration. The Vega eFPGA boasts a versatile architecture allowing for tailored configurations to suit varying application requirements. This IP includes configurable tiles like CLB (Configurable Logic Blocks), BRAM (Block RAM), and DSP (Digital Signal Processing) units. The CLB part includes eight 6-input Lookup Tables that provide dual outputs, and also an optional configuration with a fast adder having a carry chain. The BRAM supports 36Kb dual-port memory and offers flexibility for different configurations, while the DSP component is designed for complex arithmetic functions with its 18x20 multipliers and a wide 64-bit accumulator. Focused on allowing easy system design and acceleration, Vega eFPGA ensures seamless integration and verification into any SoC design. It is backed by a robust EDA toolset and features that allow significant customization, making it adaptable to any semiconductor fabrication process. This flexibility and technological robustness places the Vega eFPGA as a standout choice for developing innovative and complex programmable logic solutions.
The GateMate FPGA is designed to offer exceptional flexibility and adaptability for a wide range of applications. FPGAs, known for their configurability post-manufacturing, enable users to tailor designs to specific needs. GateMate FPGAs are particularly suited for industries such as telecommunications, automotive, aerospace, and industrial sectors, where adaptability and parallel processing are crucial. GateMate FPGAs employ the latest technology, ensuring users benefit from high-speed processing and superior connectivity options. This makes them ideal for applications that require real-time data processing and parallel task execution. Their utility extends across diverse applications, from advanced driver-assistance systems in automotive to complex image processing tasks in medical devices. Manufactured using GlobalFoundries' proven 28nm process node, GateMate FPGAs strike a perfect balance between performance and power efficiency. This manufacturing detail ensures high-quality standards and a reliable supply chain, delivering FPGAs that meet both economic and technical demands.
The Jotunn8 AI Accelerator by VSORA is a game-changing product in the realm of AI inference, designed to handle any algorithm on any host processor, offering unparalleled programmability. This AI accelerator provides a substantial 6,400 Tflops of performance using fp8 Tensor Cores and is highly adaptable for large language models like GPT-4, significantly reducing deployment costs to below $0.002 per query. Its architecture allows large-scale AI models to function efficiently, emphasizing low latency and minimized power consumption. Utilizing high-level programming, the Jotunn8 is algorithm-agnostic, meaning it can seamlessly process both AI and general-purpose tasks, chosen layer-by-layer. It is equipped with 192 GB of on-chip memory to support hefty data handling requirements, ensuring that substantial AI workloads can be managed effectively without reliance on external memory systems. This characteristic is crucial in overcoming the 'Memory Wall' challenge inherent in traditional computing setups. Designed for both cloud and on-premise applications, the Jotunn8’s peak power consumption is pegged at 180W, reinforcing its position as a high-performance yet energy-efficient solution. This AI accelerator provides a balance between energy efficiency and performance, making it an exemplary choice for environments demanding rapid AI deployment and execution.
The Chimera SDK from Quadric is an all-encompassing software development toolkit designed to facilitate the creation and optimization of complex applications for the Chimera GPNPU. It offers developers a powerful platform to blend data parallel algorithms expressed as machine learning graphs with traditional C++ code, thereby delivering unprecedented flexibility and performance. This toolkit provides users with access to Quadric's Developer Studio, where applications can be developed using a straightforward drag-and-drop interface. The Chimera SDK supports both online and on-premise use, allowing developers to either work directly within a browser environment or download and deploy the SDK within their own infrastructure. This flexibility ensures that proprietary C++ code and ML models can be compiled and optimized efficiently. The SDK is bolstered by the Chimera Graph Compiler, which transforms ML inference models from popular training frameworks into optimized C++ code. This streamlined conversion process, alongside the detailed profiling capabilities of the Chimera Instruction Set Simulator, enables developers to thoroughly optimize their applications for both performance and memory utilization. The Chimera SDK thus represents a significant leap forward in simplifying the design and deployment of sophisticated AI applications.