All IPs > Platform Level IP > Processor Core Independent
In the ever-evolving landscape of semiconductor technologies, processor core independent IPs play a crucial role in designing flexible and scalable digital systems. These semiconductor technologies offer the versatility of enabling functionalities independent of a specific processor core, making them invaluable for a variety of applications where flexibility and reusability are paramount.
Processor core independent semiconductor IPs are tailored to function across different processor architectures, avoiding the constraints tied to any one specific core. This characteristic is particularly beneficial in embedded systems, where designers aim to balance cost, performance, and power efficiency while ensuring seamless integration. These IPs provide solutions that accommodate diverse processing requirements, from small-scale embedded controllers to large-scale data centers, making them essential components in the toolkit of semiconductor design engineers.
Products in this category often include memory controllers, I/O interfaces, and various digital signal processing blocks, each designed to operate autonomously from the central processor's architecture. This independence allows manufacturers to leverage these IPs in a broad array of devices, from consumer electronics to automotive systems, without the need for extensive redesigns for different processor families. Moreover, this flexibility championed by processor core independent IPs significantly accelerates the time-to-market for many devices, offering a competitive edge in high-paced industry environments.
Furthermore, the adoption of processor core independent IPs supports the development of customized, application-specific integrated circuits (ASICs) and system-on-chips (SoCs) that require unique configurations, without the overhead of processor-specific dependencies. By embracing these advanced semiconductor IPs, businesses can ensure that their devices are future-proof, scalable, and capable of integrating new functionalities as technologies advance without being hindered by processor-specific limitations. This adaptability positions processor core independent IPs as a vital cog in the machine of modern semiconductor design and innovation.
Designed for high-performance applications, the Metis AIPU PCIe AI Accelerator Card employs four Metis AI Processing Units to deliver exceptional computational power. With its ability to reach up to 856 TOPS, this card is tailored for demanding vision applications, making it suitable for real-time processing of multi-channel video data. The PCIe form factor ensures easy integration into existing systems, while the customized software platform simplifies the deployment of neural networks for tasks like YOLO object detection. This accelerator card ensures scalability and efficiency, allowing developers to implement AI applications that are both powerful and cost-effective. The card’s architecture also takes advantage of RISC-V and Digital-In-Memory Computing technologies, bringing substantial improvements in speed and power efficiency.
The Origin E1 neural engines by Expedera redefine efficiency and customization for low-power AI solutions. Specially crafted for edge devices like home appliances and security cameras, these engines serve ultra-low power applications that demand continuous sensing capabilities. They minimize power consumption to as low as 10-20mW, keeping data secure and eliminating the need for external memory access. The advanced packet-based architecture enhances performance by facilitating parallel layer execution, thereby optimizing resource utilization. Designed to be a perfect fit for dedicated AI functions, Origin E1 is tailored to support specific neural networks efficiently while reducing silicon area and system costs. It supports various neural networks, from CNNs to RNNs, making it versatile for numerous applications. This engine is also one of the most power-efficient in the industry, boasting an impressive 18 TOPS per Watt. Origin E1 also offers a full TVM-based software stack for easy integration and performance optimization across customer platforms. It supports a wide array of data types and networks, ensuring flexibility and sustained power efficiency, averaging 80% utilization. This makes it a reliable choice for OEMs looking for high performance in always-sensing applications, offering a competitive edge in both power efficiency and security.
The ORC3990 SoC is a state-of-the-art solution designed for satellite IoT applications within Totum's DMSS™ network. This low-power sensor-to-satellite system integrates an RF transceiver, ARM CPUs, memories, and PA to offer seamless IoT connectivity via LEO satellite networks. It boasts an optimized link budget for effective indoor signal coverage, eliminating the need for additional GNSS components. This compact SoC supports industrial temperature ranges and is engineered for a 10+ year battery life using advanced power management.
The Origin E8 NPUs represent Expedera's cutting-edge solution for environments demanding the utmost in processing power and efficiency. This high-performance core scales its TOPS capacity between 32 and 128 with single-core configurations, addressing complex AI tasks in automotive and data-centric operational settings. The E8’s architecture stands apart due to its capability to handle multiple concurrent tasks without any compromise in performance. This unit adopts Expedera's signature packet-based architecture for optimized parallel execution and resource management, removing the necessity for hardware-specific tweaks. The Origin E8 also supports high input resolutions up to 8K and integrates well across standard and custom neural networks, enhancing its utility in future-forward AI applications. Leveraging a flexible, scalable design, the E8 IP cores make use of an exhaustive software suite to augment AI deployment. Field-proven and already deployed in a multitude of consumer vehicles, Expedera's Origin E8 provides a robust, reliable choice for developers needing optimized AI inference performance, ideally suited for data centers and high-power automobile systems.
The AX45MP is engineered as a high-performance processor that supports multicore architecture and advanced data processing capabilities, particularly suitable for applications requiring extensive computational efficiency. Powered by the AndesCore processor line, it capitalizes on a multicore symmetric multiprocessing framework, integrating up to eight cores with robust L2 cache management. The AX45MP incorporates advanced features such as vector processing capabilities and support for MemBoost technology to maximize data throughput. It caters to high-demand applications including machine learning, digital signal processing, and complex algorithmic computations, ensuring data coherence and efficient power usage.
Origin E2 NPUs focus on delivering power and area efficiency, making them ideal for on-device AI applications in smartphones and edge nodes. These processing units support a wide range of neural networks, including video, audio, and text-based applications, all while maintaining impressive performance metrics. The unique packet-based architecture ensures effective performance with minimal latency and eliminates the need for hardware-specific optimizations. The E2 series offers customization options allowing it to fit specific application needs perfectly, with configurations supporting up to 20 TOPS. This flexibility represents significant design advancements that help increase processing efficiency without introducing latency penalties. Expedera's power-efficient design results in NPUs with industry-leading performance at 18 TOPS per Watt. Further augmenting the value of E2 NPUs is their ability to run multiple neural network types efficiently, including LLMs, CNNs, RNNs, and others. The IP is field-proven, deployed in over 10 million consumer devices, reinforcing its reliability and effectiveness in real-world applications. This makes the Origin E2 an excellent choice for companies aiming to enhance AI capabilities while managing power and area constraints effectively.
The AndeShape Platforms are designed to streamline system development by providing a diverse suite of IP solutions for SoC architecture. These platforms encompass a variety of product categories, including the AE210P for microcontroller applications, AE300 and AE350 AXI fabric packages for scalable SoCs, and AE250 AHB platform IP. These solutions facilitate efficient system integration with Andes processors. Furthermore, AndeShape offers a sophisticated range of development platforms and debugging tools, such as ADP-XC7K160/410, which reinforce the system design and verification processes, providing a comprehensive environment for the innovative realization of IoT and other embedded applications.
The Chimera GPNPU by Quadric is a versatile processor specifically designed to enhance machine learning inference tasks on a broad range of devices. It provides a seamless blend of traditional digital signal processing (DSP) and neural processing unit (NPU) capabilities, which allow it to handle complex ML networks alongside conventional C++ code. Designed with a focus on adaptability, the Chimera GPNPU architecture enables easy porting of various models and software application programming, making it a robust solution for rapidly evolving AI technologies. A key feature of the Chimera GPNPU is its scalable design, which extends from 1 to a remarkable 864 TOPs, catering to applications from standard to advanced high-performance requirements. This scalability is coupled with its ability to support a broad range of ML networks, such as classic backbones, vision transformers, and large language models, fulfilling various computational needs across industries. The Chimera GPNPU also excels in automotive applications, including ADAS and ECU systems, due to its ASIL-ready design. The processor's hybrid architecture merges Von Neumann and 2D SIMD matrix capabilities, promoting efficient execution of scalar, vector, and matrix operations. It boasts a deterministic execution pipeline and extensive customization options, including configurable instruction caches and local register memories that optimize memory usage and power efficiency. This design effectively reduces off-chip memory accesses, ensuring high performance while minimizing power consumption.
The Origin E6 neural engines are built to push the boundaries of what's possible in edge AI applications. Supporting the latest in AI model innovations, such as generative AI and various traditional networks, the E6 scales from 16 to 32 TOPS, aimed at balancing performance, efficiency, and flexibility. This versatility is essential for high-demand applications in next-generation devices like smartphones, digital reality setups, and consumer electronics. Expedera’s E6 employs packet-based architecture, facilitating parallel execution that leads to optimal resource usage and eliminating the need for dedicated hardware optimizations. A standout feature of this IP is its ability to maintain up to 90% processor utilization even in complex multi-network environments, thus proving its robustness and adaptability. Crafted to fit various use cases precisely, E6 offers a comprehensive TVM-based software stack and is well-suited for tasks that require simultaneous running of numerous neural networks. This has been proven through its deployment in over 10 million consumer units. Its design effectively manages power and system resources, thus minimizing latency and maximizing throughput in demanding scenarios.
AndesCore Processors offer a robust lineup of high-performance CPUs tailored for diverse market segments. Employing the AndeStar V5 instruction set architecture, these cores uniformly support the RISC-V technology. The processor family is classified into different series, including the Compact, 25-Series, 27-Series, 40-Series, and 60-Series, each featuring unique architectural advances. For instance, the Compact Series specializes in delivering compact, power-efficient processing, while the 60-Series is optimized for high-performance out-of-order execution. Additionally, AndesCore processors extend customization through Andes Custom Extension, which allows users to define specific instructions to accelerate application-specific tasks, offering a significant edge in design flexibility and processing efficiency.
InCore's RISC-V Core-hub Generators are a revolutionary tool designed to give developers unparalleled control over their SoC designs. These generators enable the customization of core-hub configurations down to the ISA and microarchitecture level, promoting a tailored approach to chip creation. Built around the robustness of the RISC-V architecture, the Core-hub Generators support versatile application needs, allowing designers to innovate without boundaries. The Core-hub concept is pivotal to speeding up SoC development by offering a framework of diverse cores and optimized fabric components, including essential RISC-V UnCore features like PLICs, Debug, and Trace components. This systemic flexibility ensures that each core hub aligns with specific customer requirements, providing a bespoke design experience that enhances adaptability and resource utilization. By integrating efficient communication protocols and optimized processing capabilities, InCore's Core-hub Generators foster seamless data exchange across modules. This is essential for developing next-gen semiconductor solutions that require both high performance and security. Whether used in embedded systems, high-performance industrial applications, or sophisticated consumer electronics, these generators stand as a testament to InCore's commitment to innovation and engineering excellence.
The Titanium Ti375 FPGA from Efinix boasts a high-density, low-power configuration, ideal for numerous advanced computing applications. Built on the well-regarded Quantum compute fabric, this FPGA integrates a robust set of features including a hardened RISC-V block, SerDes transceiver, and LPDDR4 DRAM controller, enhancing its versatility in challenging environments. The Ti375 model is designed with an intuitive I/O interface, allowing seamless communication and data handling. Its innovative architecture ensures minimal power consumption without compromising on processing speed, making it highly suitable for portable and edge devices. The inclusion of MIPI D-PHY further expands its applications in image processing and high-speed data transmission tasks. This FPGA is aligned with current market demands, emphasizing efficiency and scalability. Its architecture allows for diverse design challenges, supporting applications that transcend traditional boundaries. Efinix’s commitment to delivering sophisticated yet energy-efficient solutions is embodied in the Titanium Ti375, enabling new possibilities in the realm of computing.
GSHARK is a high-performance GPU IP designed to accelerate graphics on embedded devices. Known for its extreme power efficiency and seamless integration, this GPU IP significantly reduces CPU load, making it ideal for use in devices like digital cameras and automotive systems. Its remarkable track record of over one hundred million shipments underscores its reliability and performance. Engineered with TAKUMI's proprietary architecture, GSHARK integrates advanced rendering capabilities. This architecture supports real-time, on-the-fly graphics processing similar to that found in PCs, smartphones, and gaming consoles, ensuring a rich user experience and efficient graphics applications. This IP excels in environments where power consumption and performance balance are crucial. GSHARK is at the forefront of embedded graphics solutions, providing significant improvements in processing speed while maintaining low energy usage. Its architecture easily handles demanding graphics rendering tasks, adding considerable value to any embedded system it is integrated into.
The Ultra-Low-Power 64-Bit RISC-V Core by Micro Magic represents a significant advancement in energy-efficient computing. This core, operating at an astonishingly low 10mW while running at 1GHz, sets a new standard for low-power design in processors. Micro Magic's proprietary methods ensure that this core maintains high performance even at reduced voltages, making it a perfect fit for applications where power conservation is crucial. Micro Magic's RISC-V core is designed to deliver substantial computational power without the typical energy costs associated with traditional architectures. With capabilities that make it suitable for a wide array of high-demand tasks, this core leverages sophisticated design approaches to achieve unprecedented power efficiency. The core's impressive performance metrics are complemented by Micro Magic's specialized tools, which aid in integrating the core into larger systems. Whether for embedded applications or more demanding computational roles, the Ultra-Low-Power 64-Bit RISC-V Core offers a compelling combination of power and performance. The design's flexibility and power efficiency make it a standout among other processors, reaffirming Micro Magic's position as a leader in semiconductor innovation. This solution is poised to influence how future processors balance speed and energy usage significantly.
The Dynamic Neural Accelerator II by EdgeCortix is a pioneering neural network core that combines flexibility and efficiency to support a broad array of edge AI applications. Engineered with run-time reconfigurable interconnects, it facilitates exceptional parallelism and efficient data handling. The architecture supports both convolutional and transformer neural networks, offering optimal performance across varied AI use cases. This architecture vastly improves upon traditional IP cores by dynamically reconfiguring data paths, which significantly enhances parallel task execution and reduces memory bandwidth usage. By adopting this approach, the DNA-II boosts its processing capability while minimizing energy consumption, making it highly effective for edge AI applications that require high output with minimal power input. Furthermore, the DNA-II's adaptability enables it to tackle inefficiencies often seen in batching tasks across other IP ecosystems. The architecture ensures that high utilization and low power consumption are maintained across operations, profoundly impacting sectors relying on edge AI for real-time data processing and decision-making.
The Trion FPGA family by Efinix addresses the dynamic needs of edge computing and IoT applications. These devices range from 4K to 120K logic elements, balancing computational capability with efficient power usage for a wide range of general-purpose applications. Trion FPGAs are designed to empower edge devices with rapid processing capabilities and flexible interfacing. They support a diverse array of use-cases, from industrial automation systems to consumable electronics requiring enhanced connectivity and real-time data processing. Offering a pragmatic solution for designers, Trion FPGAs integrate seamlessly into existing systems, facilitating swift development and deployment. They provide unparalleled adaptability to meet the intricate demands of modern technological environments, thereby enabling innovative edge and IoT solutions to flourish.
Dream Chip Technologies' Arria 10 System on Module (SoM) emphasizes embedded and automotive vision applications. Utilizing Altera's Arria 10 SoC Devices, the SoM is compact yet packed with powerful capabilities. It features a dual-core Cortex A9 CPU and supports up to 480 KLEs of FPGA logic elements, providing ample space for customization and processing tasks. The module integrates robust power management features to ensure efficient energy usage, with interfaces for DDR4 memory, PCIe Gen3, Ethernet, and 12G SDI among others, housed in a form factor measuring just 8 cm by 6.5 cm. Engineered to support high-speed data processing, the Arria 10 SoM includes dual DDR4 memory interfaces and 12 transceivers at 12 Gbit/s and above. It provides comprehensive connectivity options, including two USB ports, Gigabit Ethernet, and multiple GPIOs with level-shifting capabilities. This level of integration makes it optimal for developing solutions for automotive systems, particularly in scenarios requiring high-speed data and image processing. Additionally, the SoM comes with a suite of reference designs, such as the Intel Arria 10 Golden System Reference Design, to expedite development cycles. This includes pre-configured HPS and memory controller IP, as well as customized U-Boot and Angström Linux distributions, further enriching its utility in automotive and embedded domains.
The Software-Defined High PHY from AccelerComm is an adaptable solution designed for ARM processor architectures, providing versatile platform support. This PHY can function with or without hardware acceleration, catering to varying demands in capacity and power for diverse applications. It seamlessly integrates into O-RAN environments and can be tailored to optimize performance, aligning with specific network requirements. This versatile solution capitalizes on the strengths of ARM processors and offers additional flexibility through optional hardware accelerations. By providing a scalable framework, the Software-Defined High PHY supports efficient deployment, regardless of the network size or complexity. This adaptability ensures that network managers can configure the PHY to meet specific performance objectives, maximizing throughput while minimizing power consumption. Esteemed for its flexibility and ease of integration, this solution exemplifies AccelerComm's commitment to delivering high-caliber, platform-independent PHY solutions. It empowers network developers to tailor their setups, thus enhancing performance metrics like latency and spectral efficiency.
VSORA's Tyr Superchip epitomizes high-performance capabilities tailored for the demanding worlds of autonomous driving and generative AI. With its advanced multi-core architecture, this superchip can execute any algorithm efficiently without relying on CUDA, which promotes versatility in AI deployment. Built to deliver a seamless combination of AI and general-purpose processing, the Tyr Superchip utilizes sparsity techniques, supporting quantization on-the-fly, which optimizes its performance for a wide array of computational tasks. The Tyr Superchip is distinctive for its ability to support the simultaneous execution of AI and DSP tasks, selectable on a layer-by-layer basis, which provides unparalleled flexibility in workload management. This flexibility is further complemented by its low latency and power-efficient design, boasting performance near theoretical maximums, with support for next-generation algorithms and software-defined vehicles (SDVs). Safety is prioritized with the implementation of ISO26262/ASIL-D features, making the Tyr Superchip an ideal solution for the automotive industry. Its hardware is designed to handle the computational load required for safe and efficient autonomous driving, and its programmability allows for ongoing adaptations to new automotive standards and innovations.
ZIA Stereo Vision (SV) represents DMP's cutting-edge depth sensing solution, engineered to offer high-precision stereo vision for various AI applications. It's designed to process stereo images for advanced depth mapping, utilizing 4K inputs to facilitate distance estimation via stereo matching algorithms like Semi-Global Matching (SGM). Through this technique, ZIA SV ensures that distance information is extracted accurately, a critical capability for applications like autonomous mobile robots or advanced imaging systems. Pre- and post-processing optimization provides the ZIA SV with the tools necessary to refine depth estimates and ensure high accuracy. It supports 8-bit greyscale inputs and outputs a disparity map with an accuracy up to 0.8%, provided by advanced filtering techniques that enhance precision while maintaining a compact form factor crucial in embedded systems. This IP core integrates smoothly into systems requiring reliable depth measurement, utilizing efficient AMBA AXI interfaces for easy integration into diverse applications. With capabilities to support a wide range of hardware platforms and favorable performance-to-size ratios, the ZIA Stereo Vision core embodies DMP's philosophy of compact, high-performance solutions for smarter decision-making in machine vision applications.
The General Purpose Accelerator (Aptos) from Ascenium stands out as a redefining force in the realm of CPU technology. It seeks to overcome the limitations of traditional CPUs by providing a solution that tackles both performance inefficiencies and high energy demands. Leveraging compiler-driven architecture, this accelerator introduces a novel approach by simplifying CPU operations, making it exceptionally suited for handling generic code. Notably, it offers compatibility with the LLVM compiler, ensuring a wide range of applications can be adapted seamlessly without rewrites. The Aptos excels in performance by embracing a highly parallel yet simplified CPU framework that significantly boosts efficiency, reportedly achieving up to four times the performance of cutting-edge CPUs. Such advancements cater not only to performance-oriented tasks but also substantially mitigate energy consumption, providing a dual benefit of cost efficiency and reduced environmental impact. This makes Aptos a valuable asset for data centers seeking to optimize their energy footprint while enhancing computational capabilities. Additionally, the Aptos architecture supports efficient code execution by resolving tasks predominantly at compile-time, allowing the processor to handle workloads more effectively. This allows standard high-level language software to run with improved efficiency across diverse computing environments, aligning with an overarching goal of greener computing. By maximizing operational efficiency and reducing carbon emissions, Aptos propels Ascenium into a leading position in the sustainable and high-performance computing sector.
The SiFive Essential family embodies a customizable range of processor cores, designed to fulfill various market-specific requirements. From small microcontroller units (MCUs) to more complex 64-bit processors capable of running operating systems, the Essential series provides flexibility in design and functionality. These processors support a diverse set of applications including IoT devices, real-time controls, and control plane processing. They offer scalable performance through sophisticated pipeline architectures, catering to both embedded and rich-OS environments. The Essential series offers advanced configurations which can be tailored to optimize for power and area footprint, making it suitable for devices where space and energy are limited. This aligns well with the needs of edge devices and other applications where efficiency and performance must meet in a balanced manner.
Time-Triggered Ethernet is an enhanced network solution tailored for environments requiring stringent timing and synchronization. By leveraging the principles of time-triggered communication, it enhances standard Ethernet with deterministic capabilities. This advanced protocol is instrumental in ensuring timely and predictable data exchange, making it ideal for complex network architectures where timing precision is a must. Utilizing synchronized clocks across the network, Time-Triggered Ethernet virtually eliminates latency variability. This predictability across the Ethernet infrastructure supports a variety of applications, from aviation systems requiring certified safety levels to automotive networks needing high reliability. The protocol helps in managing critical tasks efficiently by scheduling communication activities down to precise microsecond accuracy. Time-Triggered Ethernet enhances both the fault tolerance and robustness of networks it supports, making it a preferred choice for high-stakes scenarios. Its ability to carry safety-critical and time-sensitive data over existing Ethernet infrastructure ensures wide applicability and adaptability. By optimizing performance while maintaining compatibility with Ethernet standards, it supports diverse applications from smart industry automation to critical aerospace systems.
The Codasip RISC-V BK Core Series offers a versatile solution for a broad range of computing needs, from low-power embedded devices to high-performance applications. These cores leverage the open RISC-V instruction set architecture (ISA), enabling designers to take advantage of expansive customization options that optimize performance and efficiency. The BK Core Series supports high configurability, allowing users to adapt the microarchitecture and extend the instruction set based on specific application demands. Incorporating advanced features like zero-overhead loops and SIMD instructions, the BK Core Series is designed to handle computationally intensive tasks efficiently. This makes them ideal for applications in audio processing, AI, and other scenarios requiring high-speed data processing and computation. Additionally, these cores are rigorously verified to meet industry standards, ensuring robustness and reliability even in the most demanding environments. The BK Core Series also aligns with Codasip's focus on functional safety and security. These processors come equipped with features to bolster system reliability, helping prevent cyber threats and errors that could lead to system malfunctions. This makes the BK Core Series an excellent choice for industries that prioritize safety, such as automotive and industrial automation.
SystemBIST represents a comprehensive plug-and-play device enhancing FPGA configurations and embedded JTAG testing methodologies on PCBs. This sophisticated module allows for seamless FPGA device programming and reconfiguration in-field, supporting IEEE 1532 and IEEE 1149.1 standards. Designed with a vendor-independent approach, SystemBIST offers scalable configurations for both flash memory and CPLD devices, integrating built-in self-tests (BIST) that utilize stored test patterns in flash memory. This product simplifies the traditional complex methods of FPGA configuration, removing the need for large PROM parts and streamlining production concerns with its cost-effective design, widening its appeal across sectors needing flexible, reliable re-programmable solutions.
TySOM boards are embedded system prototyping platforms that integrate high-performance FPGAs, including Xilinx Zynq and Microchip PolarFire SoCs. These boards are ideal for developing applications like automotive ADAS, AI, and industrial automation. By leveraging industry-standard interfaces, TySOM boards ensure versatility and wide compatibility, making them a cornerstone in rapid application development.
The BlueLynx Chiplet Interconnect offers an advanced die-to-die interconnect solution, tailored to meet the rigorous demands of contemporary chiplet designs. With support for Universal Chiplet Interconnect Express (UCIe) and the Open Compute Project's Bunch of Wires (BoW), this IP establishes a robust physical and link layer interface for chiplet communications. It's built to connect efficiently with on-die bus standards like AMBA AXI and ACE, streamlining the process of linking chiplets within advanced package configurations. Technologically sophisticated, BlueLynx supports a variety of fabrication nodes ranging from 16nm down to 3nm, ensuring compatibility across multiple semiconductor foundries. This interconnect solution is silicon-proven and enables not only rapid development but also minimizes the traditional risks associated with new designs. Clients receive a comprehensive ASIC integration package, including platform software and design references, which allows for swift silicon bring-up and ensures that first-pass silicon achieves expected operational standards. The architecture of BlueLynx is designed to be both customizable and efficient. With data rates stretching from 2 Gb/s up to over 40 Gb/s, and low power consumption underpinning its design, BlueLynx manages to provide a high bandwidth density of over 15 Tbps/mm². This results in optimal performance scaling across diverse applications while accommodating advanced 3D packaging options. The PHY component of the IP is specifically designed for high compatibility and minimal latency, built on the architecture that supports configurable serialization and deserialization ratios, multiple PHY slices, along with detailed specifications for bump pitch and package applications.
Trilinear’s Cobra for the Xilinx Kintex-7 Platform is a development solution tailored to enhance the performance of Xilinx’s FPGA technology. This platform is designed to accelerate the development cycle by providing a robust and adaptable foundation for complex computing tasks. The Cobra platform is engineered to support a wide array of applications, making it highly beneficial for developers aiming to innovate within an FPGA framework. Its design facilitates rapid prototyping and efficient deployment, essential for fast-paced development environments. Leveraging the power of the Kintex-7, users can execute computationally intensive processes while maintaining high efficiency and reliability. As part of Trilinear's developmental toolkit, Cobra stands out for its flexibility, making it an excellent choice for complex and varied use cases in the semiconductor industry. It reflects Trilinear’s commitment to providing cutting-edge tools that streamline development processes, allowing for greater innovation in FPGA design and implementation.
The SiFive Performance family of RISC-V processors targets maximum throughput and efficiency for environments including web servers and multimedia processing. These processors come in configurations ranging from three to six wide Out-of-Order (OoO) cores, with dedicated vector engines designed for AI workloads. By providing energy-efficiency without compromising on performance, the SiFive Performance Cores are tailored to meet the needs of diverse high-performance applications. These cores are scalable, offering configurations that can extend up to 256 cores. This scalability is essential for data centers and mobile infrastructures alike, where performance and efficiency are paramount. Key technical features include a six-wide out-of-order core architecture, RAS functionality, and a scalable core cluster. In datacenters and beyond, they facilitate the development of a diverse range of applications, including big data analytics and enterprise infrastructure solutions. SiFive's commitment to high-performance RISC-V processors caters to growing demands for performance and area-efficient application processors.
VisualSim Architect serves as a comprehensive platform for modeling and simulating electronic systems. It's designed to bridge the gap between system specifications, enhancing the model-based system engineering process. It provides crucial timing and power simulations that help identify potential bottlenecks early in development, thus optimizing system performance and functionality. Besides streamlining the specification process, it supports extensive use-case exploration and architecture optimization on various platforms. With its capacity to generate detailed reports on performance and power, engineers can gauge system efficiency accurately. VisualSim Architect's powerful capabilities significantly reduce the risk of design errors and expedite the development cycle. This tool is especially beneficial for semiconductor design, where precise performance and power predictions are crucial.
The Camera ISP Core is designed to optimize image signal processing by integrating sophisticated algorithms that produce sharp, high-resolution images while requiring minimal logic. Compatible with RGB Bayer and monochrome image sensors, this core handles inputs from 8 to 14 bits and supports resolutions from 256x256 up to 8192x8192 pixels. Its multi-pixel processing capabilities per clock cycle allow it to achieve performance metrics like 4Kp60 and 4Kp120 on FPGA devices. It uses AXI4-Lite and AXI4-Stream interfaces to streamline defect correction, lens shading correction, and high-quality demosaicing processes. Advanced noise reduction features, both 2D and 3D, are incorporated to handle different lighting conditions effectively. The core also includes sophisticated color and gamma corrections, with HDR processing for combining multiple exposure images to improve dynamic range. Capabilities such as auto focus and saturation, contrast, and brightness control are further enhanced by automatic white balance and exposure adjustments based on RGB histograms and window analyses. Beyond its core features, the Camera ISP Core is available with several configurations including the HDR, Pro, and AI variations, supporting different performance requirements and FPGA platforms. The versatility of the core makes it suitable for a range of applications where high-quality real-time image processing is essential.
Ncore Cache Coherent Interconnect from Arteris is a sophisticated NoC interconnect solution engineered to tackle the multifaceted challenges of designing modern multi-core ASICs. Ncore's architecture supports various protocols and processors, including Arm and RISC-V, to foster more efficient inter-core communication, power optimization, reliability, and safety in complex SoCs. The IP is especially lauded for its ability to maintain comprehensive coherence for cached processors and I/O coherency, adapted for accelerators and different component communications within the SoC. It also supports ISO 26262 standards for functional safety compliance, making it a prime candidate for use in safety-critical applications. Noteworthy features include true heterogeneous coherency integrated with AMBA CHI and ACE support, making it ideal for creating high-performance, flexible SoC designs that address stringent safety and power consumption concerns. Additionally, Ncore enables advanced configuration of snoop filters, quality of service management, and debugging capabilities, thereby optimizing power usage and integration complexity. The flexibility in topologies and robust support for various coherent agents make Ncore an invaluable asset for SoC developers seeking modular, scalable design options for diverse applications.
The NOC-X, or Network on Chip, developed by Extoll, serves as a crucial infrastructure for advanced chiplet systems, providing a highly efficient communication backbone for complex semiconductor designs. This technology is specifically architected to cater to the demands of high-data traffic environments, offering ultra-low power consumption and greatly enhanced data throughput. With Extoll's expertise in digital-centric architectures, the NOC-X is designed to streamline data transfer across large-scale chiplet configurations, ensuring that bandwidth is optimized, and latency is minimized. This network system is pivotal for integrating sizeable multicore designs, significantly enhancing the ability of various cores to operate in sync, while maintaining low energy costs. The NOC-X’s offerings make it indispensable in applications requiring precise control and efficient data management. Engineers and developers focusing on next-generation semiconductor designs will find NOC-X to be an invaluable asset. It simplifies the implementation of complex network topologies within a chip, thus paving the way for more scalable and powerful computing solutions. By integrating the NOC-X into their systems, developers can achieve remarkable improvements in system performance and efficiency, meeting the rigorous demands of modern technological applications.
The SAKURA-II AI Accelerator is a state-of-the-art energy-efficient AI processing unit designed to meet the demanding needs of generative AI applications. Boasting up to 60 TOPS performance, this accelerator is built on EdgeCortix's patented Dynamic Neural Accelerator architecture that allows high efficiency and low power consumption in edge AI tasks. It supports a wide array of models including Llama 2, Stable Diffusion, ViT, and large transformer and convolutional networks, typically operating within an 8W power envelope. Offering enhanced DRAM bandwidth and a maximum memory capacity of 32GB, SAKURA-II is optimized for real-time data streaming and efficient handling of large language models (LLMs) and vision-based AI workloads. This accelerator achieves exceptionally high AI compute utilization and provides robust energy-efficient performance, making it ideal for advanced applications in vision, language, audio, and more. The accelerator is available in modular M.2 and PCIe card formats, facilitating seamless integration into existing systems. These form factors ensure that the SAKURA-II can be effortlessly integrated into space-constrained or power-limited environments, providing the best choice for both development and deployment phases of edge AI initiatives.
The AI Inference Platform by SEMIFIVE is designed to accelerate artificial intelligence applications with optimized compute capabilities. It supports a variety of frameworks and offers robust integration with existing systems to streamline advanced data processing tasks. This platform is engineered to enhance performance efficiency, offering significant power savings and minimizing latency, thus addressing the demanding needs of AI-driven markets. Additionally, it boasts a modular design to accommodate updates and scalability.
EnSilica's eSi-ADAS is a comprehensive radar accelerator suite designed to enhance the capabilities and performance of radar systems. It is particularly suited for automotive, drone, and UAV applications where quick, responsive situational awareness is critical. This radar co-processor engine enables rapid data processing, contributing significantly to vehicle safety systems and providing a real-time operational advantage. It boasts efficient integration with existing systems, maximizing the benefits of advanced digital signal processing (DSP) techniques tailored to radar applications. By accelerating radar algorithm execution, this IP helps designers create more efficient detection systems and improve the operational reliability of advanced driver-assistance systems (ADAS).
The Digital Radio (GDR) from GIRD Systems is an advanced software-defined radio (SDR) platform that offers extensive flexibility and adaptability. It is characterized by its multi-channel capabilities and high-speed signal processing resources, allowing it to meet a diverse range of system requirements. Built on a core single board module, this radio can be configured for both embedded and standalone operations, supporting a wide frequency range. The GDR can operate with either one or two independent transceivers, with options for full or half duplex configurations. It supports single channel setups as well as multiple-input multiple-output (MIMO) configurations, providing significant adaptability in communication scenarios. This flexibility makes it an ideal choice for systems that require rapid reconfiguration or scalability. Known for its robust construction, the GDR is designed to address challenging signal processing needs in congested environments, making it suitable for a variety of applications. Whether used in defense, communications, or electronic warfare, the GDR's ability to seamlessly switch configurations ensures it meets the evolving demands of modern communications technology.
The EFLX eFPGA is renowned for its capability to provide reconfigurable logic that can be embedded within custom chips. This technology powers advances in various applications, from communication systems to custom ASICs and SoCs, thanks to its high-speed and low-power operation. The flexibility of the EFLX eFPGA makes it a crucial component for industries seeking adaptive solutions to meet specific hardware requirements. Leveraging such technology, companies can future-proof their designs, ensuring continuous compatibility with evolving standards and protocols. Its integration allows for real-time updates and changes, driving system adaptability in fast-paced tech environments.
The G13 and G13X IP cores are engineered to accomplish 512-bit correction blocks, which are commonly used in NAND devices with 2KB and 4KB page sizes. As SLC NAND transitions toward smaller geometries, this IP extends existing controller capabilities to meet more demanding ECC requirements. Not only available in standard configurations, Cyclic Design can tailor this IP to perfectly align with the specific needs of any controller hardware, addressing latency, bandwidth, and area prerequisites.
ASIC North offers a comprehensive suite of ARM Cortex-M® microcontrollers and processors, tailored for seamless integration into a variety of industry-specific systems. These ASICs are designed to deliver top-notch performance and efficiency, suitable for applications ranging from IoT to complex industrial systems. With a focus on providing reliable and scalable solutions, these ASICs cater to evolving technological needs while maintaining a high standard of quality and technical precision.<br><br>The ARM M-Class ASICs provide clients with the flexibility to adapt quickly to changing market demands. Leveraging years of expertise in semiconductor design, ASIC North ensures that these processors are optimized for a wide range of tasks, from enhancing communication protocols to facilitating advanced data processing functions. Continuous development and testing further ensure that these ASICs fulfill rigorous industry standards and client specifications.<br><br>By integrating these ARM M-Class ASICs, businesses gain access to next-generation capabilities that enhance overall operational efficiency. Whether deployed in robust industrial applications or cutting-edge consumer electronics, these ASICs are built to support dynamic performance needs, offering both reliability and adaptability across various sectors.
The MPSoC-Modul ZU7EV-1I, equipped with AMD Zynq UltraScale+ ZU7EV, combines high computing power with flexible interfacing and is optimized for applications such as real-time data processing. Featuring 4 GB of DDR4 memory, this module is designed to handle intensive compute tasks efficiently. Its compact form factor, coupled with high-speed transceivers, renders it suitable for a variety of industry applications including telecommunications and automotive systems.
SEMIFIVE's AIoT Platform is crafted for the burgeoning Internet of Things market, combining artificial intelligence with IoT capabilities to create smart, interconnected systems. The platform integrates powerful AI processors with IoT modules that enhance machine learning capabilities at the edge, delivering enhanced data analytics and real-time processing. It is designed for ease of deployment and flexibility, ensuring quick adaptation to ever-evolving IoT environments. This integration is optimized for power efficiency and cost-effectiveness, making it an ideal solution for large-scale AIoT implementations.
IMEC's Monolithic Microsystems offer a leap forward in integrating complex electronic systems onto a single chip. These systems are developed to meet the growing demand for miniaturization, performance, and multifunctionality in electronics, particularly significant for industries looking to enhance device sophistication without expanding physical footprint. Monolithic Microsystems are pivotal in applications ranging from consumer electronics to industrial automation, where space efficiency and performance are key. The innovation lies in the seamless integration of multiple components into a single monolith, significantly reducing interconnections and enhancing signal integrity. This approach not only streamlines the manufacturing process but also boosts reliability and enhances the system’s overall performance. The small form factor and high functionality make it a preferred choice for developing smarter, interconnected devices across various high-tech sectors. These microsystems are specifically engineered to cater to advanced applications such as wearable technology, smart medical devices, and sophisticated sensors. By marrying advanced materials with innovative design paradigms, IMEC ensures that these microsystems can withstand challenging operating conditions, offering robustness and longevity. Further, the monolithic integration allows for new levels of device intelligence and integration, facilitating the growth of next-generation electronics tailored to specific industry needs.
ASIC North specializes in creating sensor interface derivatives, custom-designed to enhance existing system functionalities. These interfaces are strategically developed to seamlessly integrate with a myriad of industry applications, offering precision and adaptability. Through cutting-edge design practices, ASIC North ensures that these sensor interface circuits can handle a diverse array of inputs, providing reliable data conversion and processing across different environments.<br><br>Each sensor interface derivative is crafted to meet the specific needs of advanced technological systems, supporting applications such as IoT devices, smart home technologies, and industrial automation. Utilizing a comprehensive design and testing methodology, ASIC North guarantees high performance and compatibility with current industry standards. This meticulous attention to detail helps improve system reliability and operational efficiency.<br><br>By choosing ASIC North's sensor interface derivatives, companies benefit from unparalleled technical support and innovative solutions tailored to their unique challenges. These interfaces not only enhance the capabilities of existing systems but also ensure scalability and future-proofing, aligning with dynamic technological advancements and evolving market trends.
TUNGA emerges as a revolutionary multi-core SoC integrating RISC-V cores with posit arithmetic capabilities. This solution is specifically architected for enhancing high-performance computing (HPC) and artificial intelligence workloads by leveraging the advantages of posit data types. As data centers struggle with the limitations of traditional number formats, TUNGA offers improved accuracy and efficiency, transforming real-number calculations with its innovative RISC-V foundation. This cutting-edge SoC includes the QUIRE accumulator, adept at executing precise dot products, crucial for delivering high-accuracy computations across extensive datasets. TUNGA's design incorporates reconfigurable FPGA gates, offering adaptability in critical function accelerations tailored for datacenter tasks. This adaptability extends to managing unique data types, thereby expediting AI training and inference. TUNGA stands out for its capability to streamline applications such as cryptography and AI support functions, making it a vital tool in pushing data center technologies to new horizons.
The DQ80251 is an ultra-high-performance microcontroller core designed for embedded systems. It supports 16-bit and 32-bit operations and utilizes a Quad-Pipeline architecture to enhance processing capabilities. With a versatile instruction set compatible with both 8051 and 80251 standards, this core ensures broad applicability in various systems. Notably, it achieves impressive performance metrics, allowing it to manage extensive code bases while maintaining efficient processing speeds. Through its optimized framework, it facilitates streamlined integration with a range of peripheral devices and offers significant improvements in data throughput.
The G12 is a highly optimized BCH error correction solution focused on 256-byte correction blocks. Particularly beneficial for specialized applications that require smaller block sizes, this IP offers dynamic flexibility with block sizes ranging from 2 to 450 bytes. Users can maximize area efficiency by specifying the ECC level, supporting both single and multi-channel configurations. Delivered as Verilog source with SystemVerilog Assertions, the G12 can accommodate higher ECC levels upon request.
This specialized radar DSP accelerator integrates with a RISC-V core to provide unmatched processing speeds for critical applications like ADAS. Designed for flexibility, hypr_risc enables adaptable configurations applicable to a range of systems, while offering significant savings on size and power. RISC-V's open architecture allows for extensive customization, fueling innovation in embedded computing environments.
The Vega eFPGA is a flexible programmable solution crafted to enhance SoC designs with substantial ease and efficiency. This IP is designed to offer multiple advantages such as increased performance, reduced costs, secure IP handling, and ease of integration. The Vega eFPGA boasts a versatile architecture allowing for tailored configurations to suit varying application requirements. This IP includes configurable tiles like CLB (Configurable Logic Blocks), BRAM (Block RAM), and DSP (Digital Signal Processing) units. The CLB part includes eight 6-input Lookup Tables that provide dual outputs, and also an optional configuration with a fast adder having a carry chain. The BRAM supports 36Kb dual-port memory and offers flexibility for different configurations, while the DSP component is designed for complex arithmetic functions with its 18x20 multipliers and a wide 64-bit accumulator. Focused on allowing easy system design and acceleration, Vega eFPGA ensures seamless integration and verification into any SoC design. It is backed by a robust EDA toolset and features that allow significant customization, making it adaptable to any semiconductor fabrication process. This flexibility and technological robustness places the Vega eFPGA as a standout choice for developing innovative and complex programmable logic solutions.
Calibrator for AI-on-Chips is designed to enhance precision and performance in AI System-on-Chips using post-training quantization techniques. By employing architecture-aware algorithms, this calibrator maintains high accuracy levels even in fixed-point architectures such as INT8. It supports heterogeneous multicore devices, ensuring compatibility with various processing engines and bit-width configurations. The product utilizes a sophisticated precision simulator for accurate quantization across data paths, leveraging hardware-specific controls for precise calibration. The included calibration workflow efficiently produces a quantization table that seamlessly integrates with compilers to fine-tune model precision without altering neural network topologies. Supporting interoperability with popular frameworks, the Calibrator for AI-on-Chips enhances performance without necessitating retraining. Users benefit from expedited quantization processes, which reduce the precision drop to minimal levels, thus ensuring high-quality outputs even for complex AI models.