All IPs > Security IP
Security IPs are an integral category within the semiconductor industry focusing on the protection of electronic data and hardware. As technological advancements continue to proliferate across critical sectors like finance, healthcare, and automotive, securing data and hardware has never been more paramount. Security IPs are designed to provide essential security features such as encryption, secure communications, and access control to safeguard sensitive information and devices from unauthorized access and cyber threats.
Within the Security IP category, you will find robust offerings that include both hardware and software-based solutions tailored to various security needs. Content Protection Software enables secure data transmission and protects digital content from piracy and unauthorized distribution. Cryptography Cores and Cryptography Software Libraries offer foundational tools for implementing strong encryption algorithms that are crucial for securing communications and data storage.
Embedded Security Modules are integrated within semiconductor devices to facilitate secure data processing and enhance trust in device operations by preventing code tampering and unauthorized hardware modification. Platform Security solutions encompass a broad range of protective measures designed to secure the entire hardware and software ecosystem, ensuring that devices are safe from potential vulnerabilities at every level.
Additionally, Security Protocol Accelerators and Security Subsystems act as dedicated processing units to efficiently handle complex security algorithms and protocols, enhancing the performance of security operations while reducing the burden on primary CPUs. With an unpredictable security landscape, leveraging a range of specialized Security IPs allows designers and engineers to build robust, secure, and reliable semiconductor solutions that can withstand evolving cyber threats.
The Akida Neural Processor is a sophisticated AI processing unit designed to handle complex neural network tasks with unmatched precision and efficiency. Utilizing an event-based processing model, Akida exploits data sparsity to minimize operations and hence decrease power usage significantly while enhancing throughput. This processor is built around a mesh network interconnect, with each node equipped with configurable Neural Network Engines that can handle convolutional and fully connected neural networks. With these capabilities, Akida can process data at the edge, maintaining high-speed, low-latency responses ideal for real-time applications. Akida maintains seamless functionality in diverse use cases, from predictive maintenance to streaming analytics in sensors. By supporting on-chip learning and providing strong privacy controls, this processor ensures data security by reducing cloud data exchanges, making it a trusted component for sensitive applications.
The 2nd Generation Akida processor introduces groundbreaking enhancements to BrainChip's neuromorphic processing platform, particularly ideal for intricate network models. It integrates eight-bit weight and activation support, improving energy efficiency and computational performance without enlarging model size. By supporting an extensive application set, Akida 2nd Generation addresses diverse Edge AI needs untethered from cloud dependencies. Notably, Akida 2nd Generation incorporates Temporal Event-Based Neural Nets (TENNs) and Vision Transformers, facilitating robust tracking through high-speed vision and audio processing. Its built-in support for on-chip learning further optimizes AI efficiency by reducing reliance on cloud training. This versatile processor fits perfectly for spatio-temporal applications across industrial, automotive, and healthcare sectors. Developers gain from its Configurable IP Platform, which allows seamless scalability across multiple use cases. The Akida ecosystem, including MetaTF, offers developers a strong foundation for integrating cutting-edge AI capabilities into Edge systems, ensuring secure and private data processing.
Overview: Cybersecurity IPs offer a range of essential security features to protect your digital assets and sensitive information. From True Random Number Generators (TRNG) to advanced encryption algorithms like AES, DES, 3DES, and cryptographic hash functions like SHA, as well as RSA for secure key exchange and digital signatures, the IPs provide a comprehensive suite of tools to safeguard your data. Key Features: True Random Number Generator (TRNG): Generates unpredictable and unbiased random numbers for cryptographic applications. Advanced Encryption Standard (AES): Provides robust encryption with symmetric key algorithms for securing data. Data Encryption Standard (DES) and Triple DES (3DES): Implement legacy encryption algorithms for data protection. Hash Functions: Includes secure cryptographic hash functions like SHA (Secure Hash Algorithm) for data integrity verification. RSA: Enables secure key exchange, encryption, and digital signatures for secure communication. These cybersecurity IPs are designed to meet the stringent security requirements of modern applications, ensuring the confidentiality, integrity, and authenticity of your data.
Overview: The Secure Boot IP is a turnkey solution that provides a secure boot facility for an SoC. It implements the Post Quantum secure Leighton-Micali Signature (LMS) as specified in NIST SP800-208. The Secure Boot IP operates as a master or slave peripheral to an Application Processor, serving as a secure enclave that securely stores keys to ensure their integrity and the integrity of the firmware authentication process. Features: Post Quantum Secure LMS Signature: Utilizes a robust Post-Quantum secure algorithm for enhanced security. Firmware Updates: Supports up to 32 thousand firmware updates with a minimal signature size of typically less than 5KBytes. SESIP Level 3 Pre-Certification: Pre-certified to SESIP Level 3 for added security assurance. RTL Delivery: Delivered as RTL for ease of integration into SoC designs. Proprietary IP: Based on proprietary IP with no 3rd party rights or royalties. Operation: The Secure Boot IP operates as a master, managing the boot process of the Application Processor to ensure that it only boots from and executes validated and authenticated firmware. The Secure Boot IP also functions as a slave peripheral, where the Application Processor requests validation of the firmware as part of its boot process, eliminating the need for managing keys and simplifying the boot process. Applications: The Secure Boot IP is versatile and suitable for a wide range of applications, including but not limited to: Wearables Smart/Connected Devices Metrology Entertainment Applications Networking Equipment Consumer Appliances Automotive Industrial Control Systems Security Systems Any SoC application that requires executing authenticated firmware in a simple but secure manner.
Tiempo Secure's True Random Number Generator (TRNG) is a cryptographic IP core designed to infuse high levels of security in digital systems. This module is vital for generating unpredictable random numbers used across various cryptographic functions such as key generation, encryption, digital signatures, and more. The TRNG is crafted to adhere to the highest standards of randomness and security as outlined by NIST and AIS31 test suites. It supports crucial protocols in secure communications like IPsec, MACsec, and TLS/SSL while providing raw data access for AIS31 characterization and incorporating comprehensive health tests. With its ability to integrate seamlessly into existing designs, the TRNG stands as a critical element for enhancing system security. Its implementation includes wrappers for standard buses such as APB and AXI, ensuring compatibility and ease of integration into existing SoC architectures. The TRNG is a cornerstone for secure device operation, ensuring that cryptographic operations maintain their integrity and randomness, thereby safeguarding against potential security breaches in the system.
Overview: The Secure Enclave IPs are Common Criteria (CC) EAL5+PP0084/PP0117 and EAL5+PP0117 certification-ready Secure Enclaves, respectively. They are available as hard macros for seamless integration into SoCs. These Secure Enclave IPs provide the highest level of security for an SoC, incorporating patented design techniques and countermeasures against side-channel and perturbation attacks to ensure robust security while minimizing power consumption. Key Features: Cryptographic Hardware Accelerators: Efficiently support standard cryptography and security operations to increase throughput while adhering to power constraints and security requirements. BootROM and Secondary Boot Loader: Manage the certified life cycle of the Secure Enclave, enforcing and assuring security from manufacturing to deployment. Proprietary IP: Based on proprietary IP that is free of 3rd party rights and royalties. Benefits: The Secure Enclave IPs offer robust security measures, efficient cryptographic support, and secure life cycle management, making them ideal for applications that require the highest levels of security and reliability. Applications: The Secure Enclave IP is versatile and suitable for a wide range of applications, including but not limited to: Secured and Certified iSIM & iUICC EMVco Payment Hardware Cryptocurrency Wallets FIDO2 Web Authentication V2X HSM Protocols Smart Car Access Secured Boot Secure OTA Firmware Updates Secure Debug Any design requiring a Secure Enclave, Secure Element, or Hardware Root of Trust protected against side-channel and perturbation fault attacks. Compliance and Support: The Secure Enclave is compliant with and ready for CC EAL5+ and EMVCo certification. It is delivered with an SDK and pre-certified CryptoLibrary and secure Boot Loader for seamless integration and enhanced security.
The Origin E1 neural engines by Expedera redefine efficiency and customization for low-power AI solutions. Specially crafted for edge devices like home appliances and security cameras, these engines serve ultra-low power applications that demand continuous sensing capabilities. They minimize power consumption to as low as 10-20mW, keeping data secure and eliminating the need for external memory access. The advanced packet-based architecture enhances performance by facilitating parallel layer execution, thereby optimizing resource utilization. Designed to be a perfect fit for dedicated AI functions, Origin E1 is tailored to support specific neural networks efficiently while reducing silicon area and system costs. It supports various neural networks, from CNNs to RNNs, making it versatile for numerous applications. This engine is also one of the most power-efficient in the industry, boasting an impressive 18 TOPS per Watt. Origin E1 also offers a full TVM-based software stack for easy integration and performance optimization across customer platforms. It supports a wide array of data types and networks, ensuring flexibility and sustained power efficiency, averaging 80% utilization. This makes it a reliable choice for OEMs looking for high performance in always-sensing applications, offering a competitive edge in both power efficiency and security.
Spec-TRACER is a robust requirements lifecycle management platform tailored for FPGA and ASIC projects. Focusing on facilitating seamless requirements capture, management, and traceability, it ensures that every stage of the design process is aligned with the initial specifications. Its analytical features further enable a comprehensive evaluation of design progress, promoting efficiency and thoroughness throughout the development lifecycle.
The AHB-Lite APB4 Bridge operates as a versatile interconnect bridge that facilitates communication between the AMBA 3 AHB-Lite and AMBA APB protocols. As a soft IP, it is fully parameterized, offering adaptability in various system designs. This bridge enhances the flexibility of integrating peripherals into main system architectures while maintaining low latency and high throughput operations.
Akida IP stands as an advanced neuromorphic processor, emulating brain-like processing to efficiently handle sensor inputs at acquisition points. This digital processor offers superior performance, precision, and significant reductions in power usage. By facilitating localized AI/ML tasks, it decreases latency and enhances data privacy. Akida IP is built to infer and learn at the edge, offering highly customizable, event-based neural processing. The architecture of Akida IP is scalable and compact, supporting an extensive mesh network connection of up to 256 nodes. Each node includes four Neural Network Layer Engines (NPEs), configurable for convolutional and fully connected processes. By leveraging data sparsity, Akida optimizes operation reduction, making it a cost-effective solution for various edge AI applications. Including MetaTF support for model simulations, Akida IP brings a fully synthesizable RTL IP package compatible with standard EDA tools, emphasizing ease of integration and deployment. This enables developers to swiftly design, develop, and implement custom AI solutions with robust security and privacy protection.
SphinX offers high-performance and low-latency encryption/decryption through AES-XTS, an industry-standard for data protection. Its independent and non-blocking encryption and decryption channels make it particularly valuable for enhancing data security in high-throughput environments. This technology is crucial for organizations that prioritize data integrity and confidentiality alongside operational efficiency. The SphinX solution ensures that sensitive data is safeguarded without compromising on speed or reliability, making it ideal for applications where both security and performance are critical. Its design allows for seamless integration into existing systems, minimizing the resource drain on processing power while offering robust security features. By focusing on ultra-low latency, SphinX is apt for use in fast-paced environments such as financial services, healthcare, and other sectors dealing with sensitive information. This highlights ZeroPoint Technologies’ commitment to providing cutting-edge solutions that navigate the complexities of modern data security demands, catering to both integrity and speed requirements.
The RV12 is a flexible RISC-V CPU designed for embedded applications. It stands as a single-core processor, compatible with RV32I and RV64I architectures, offering a configurable solution that adheres to the industry-standard RISC-V instruction set. The processor's Harvard architecture supports concurrent instruction and data memory accesses, optimizing its operation for a wide array of embedded tasks.
Post-Quantum Cryptography Processing Engine Adds support for lattice-based cryptographic operations such as ML-KEM and ML-DSA. PQPlatform-Lattice provides post-quantum support for these NIST-standardized algorithms with minimal area, and leverages an existing SHA-3 accelerator, powered by PQShield-supplied firmware. It’s designed for minimal area, and maximum compatibility, and is deployed with optional firmware-backed side-channel resistance.
This high-performance interconnect fabric provides a low-latency connection between numerous bus masters and slaves within AHB-Lite architectures. The switch supports an unlimited number of connections, facilitating scalable and efficient data flow across complex systems. Its ability to handle various data paths concurrently makes it an invaluable asset in high-speed applications.
PUFrt serves as a foundational hardware root of trust, featuring advanced key generation and storage capabilities inherent to the chip. It integrates a true random number generator (TRNG) and hardcore anti-tamper protections. With a built-in secure OTP, PUFrt provides unrivaled security for sensitive data, ensuring encryption and decryption processes are secured at the hardware level. This IP is adept at securing the semiconductor supply chain, countering the risks of reverse engineering and ensuring device authenticity through its robust identification systems. PUFrt features extensive customization options and interfaces for integration across diverse architectures, aiming to minimize user effort in embedding security functions within complex systems.
The xT CDx is an advanced FDA-approved assay designed for tumor and normal DNA sequencing. Incorporating a comprehensive 648-gene panel, this assay provides critical insights for diagnosing and treating solid tumors, with specific functions in guiding targeted therapies in colorectal cancer patients. The test includes a thorough mutation profiling system that allows healthcare professionals to analyze substitutions, insertions, and deletions, delivering a powerful means to refine treatment options. Beyond the standard, the xT CDx offers tumor and normal matched sequencing to distinguish somatic alterations, reducing false-positive results and improving accuracy in clinical assessments. Its integration into clinical practices is supported by its compatibility with various companion diagnostic claims, making it an essential tool for aligning treatment decisions with approved therapeutic products. By utilizing next-generation sequencing technologies, the xT CDx supports the optimization of treatment pathways and enhances patient care through detailed molecular insights. With the capacity to perform detailed analyses on formalin-fixed paraffin-embedded tumor tissues and matched normal samples, this assay promises high specificity and sensitivity in tumor profiling. Leveraging Tempus' cutting-edge bioinformatics infrastructure, the xT CDx ensures healthcare providers can make informed decisions supported by rich genetic data, setting a transformative benchmark in precision oncology.
Secure OTP is designed to offer superior data protection through anti-fuse OTP technology. This IP provides comprehensive security for embedded non-volatile memory, suitable for CMOS technologies with robust anti-tamper features. Secure OTP simplifies integration for use across multiple IC markets, offering the ability to secure keys and boot code in major applications like SSDs and smart TVs. The IP leverages a 1024-bit PUF for superior data scrambling and secure memory access, thereby safeguarding critical information present in semiconductor devices. Secure OTP is built to address increasing IoT security concerns and stands out for its versatile application across ASIC and SoC platforms.
Secure Protocol Engines by Secure-IC are designed to offload network and security processing tasks in high-performance computing environments. These engines provide specialized IP blocks that can handle complex cryptographic protocols efficiently. The solution optimizes system performance by allowing primary processors to focus on core functionalities while the protocol engines manage the security operations. This capability is crucial for systems requiring robust security without compromising on speed or efficiency, such as in telecommunication or data center applications.
The AES Encrypt/Decrypt module offers robust security features, accommodating 128/192/256-bit keys for both encryption and decryption tasks. This module is engineered for low latency and minimal power consumption, making it suitable for high-demand environments where security and performance are critical. The design implements Galois Field calculations using an 8-bit primitive polynomial, enabling parallel processing of key calculation and data encryption to minimize clock cycle use. The flexibility of the module is evident in its runtime programmability, ensuring that each operation can be tailored to meet specific security and performance criteria. Applications span across secure communications and any data exchange requiring high encryption standards, with the system delivering verified RTL against a broad suite of scenarios to guarantee functional integrity.
The Dynamic Neural Accelerator II by EdgeCortix is a pioneering neural network core that combines flexibility and efficiency to support a broad array of edge AI applications. Engineered with run-time reconfigurable interconnects, it facilitates exceptional parallelism and efficient data handling. The architecture supports both convolutional and transformer neural networks, offering optimal performance across varied AI use cases. This architecture vastly improves upon traditional IP cores by dynamically reconfiguring data paths, which significantly enhances parallel task execution and reduces memory bandwidth usage. By adopting this approach, the DNA-II boosts its processing capability while minimizing energy consumption, making it highly effective for edge AI applications that require high output with minimal power input. Furthermore, the DNA-II's adaptability enables it to tackle inefficiencies often seen in batching tasks across other IP ecosystems. The architecture ensures that high utilization and low power consumption are maintained across operations, profoundly impacting sectors relying on edge AI for real-time data processing and decision-making.
Tiempo Secure's Post-Quantum Cryptography (PQC) is designed to offer protection against emerging quantum computing threats, ensuring that cryptographic systems remain secure in the future. This cryptographic solution integrates advanced algorithms that are resilient to quantum attacks, providing a robust next-generation security layer. Key components of the PQC offering include quantum-resistant code signatures, key encapsulation mechanisms, and digital signatures, leveraging advanced algorithms such as the Leighton-Micali Hash-Based Signature Scheme, Crystals-Dilithium, and Crystals-Kyber. These mechanisms are engineered to provide future-proof security, aligning with evolving cryptographic requirements. Tailored for adaptability, PQC ensures dependable security through architecture-ready, hardware-accelerated algorithms that fit into various digital systems. This adaptability makes it suitable for applications seeking enhanced protective measures against quantum threats. With PQC, Tiempo Secure offers a forward-looking approach to securing digital assets, ensuring they are safeguarded from the potential risks posed by quantum computing advancements. This makes it an essential component for modern security strategies, providing peace of mind in a fast-evolving technological landscape.
Efinix's Topaz FPGA series is engineered for mass-market applications, delivering a perfect mix of efficiency and adaptability. These FPGAs encapsulate a highly efficient architecture, combined with the industry's essential features and protocols, such as PCIe Gen3, MIPI, and LPDDR4. This configuration allows users to harness substantial performance while maintaining ample room for future innovations. Topaz FPGAs are optimized for high-volume production environments where cost-effectiveness and swift integration are paramount. Their design promotes ease of implementation in various applications, spanning from automotive to deeply embedded systems, where reliability and robustness are key. Featuring a streamlined architecture, Topaz series FPGAs support modern connectivity standards and data processing capabilities. These devices are tailored for industries requiring scalable solutions that can adapt to evolving technological landscapes, ensuring that Efinix customers remain competitive in their respective fields.
The Aeonic Integrated Droop Response System is designed to enhance droop and DVFS response for integrated circuits. It includes multi-threshold droop detection and fast adaptation times, ensuring power savings and optimal system performance. This technology provides extensive observability and integrates standard interfaces like APB & JTAG, aiding silicon health management by delivering data-driven insights for lifecycle analytics.
Creonic delivers advanced Polar Encoders/Decoders that offer high flexibility and efficiency for cutting-edge communications. The company’s Polar solutions capitalize on polar code technology, which is recognized for its channel capacity achievement capabilities in the field of communications. These encoders and decoders are particularly input for Ultra Reliable Low Latency Communications (URLLC), with applications extending to 5G networks and beyond. Creonic’s solution supports various coding rates and code lengths, providing a robust framework for creating customized configurations based on customer specifications. Compatibility with major FPGA platforms allows for seamless integration into existing systems, ensuring optimal performance and scalability across numerous applications. The Polar Encoder/Decoder IP is designed to handle both short and long frames, providing enhanced reliability and ensuring data is efficiently and accurately transmitted over different communication channels.
Post-quantum cryptography library for memory-constrained platforms PQCryptoLib-Embedded is a version of PQCryptoLib, PQShield’s library of post-quantum cryptographic algorithms, which is designed for microcontrollers or memory-constrained platforms. The library is highly configurable at build time, which means binary size and memory footprint can be minimized, making this product ideal for constrained devices. Efficiency is important in implementing ML-DSA and ML-KEM, especially for devices or networks requiring quantum-safe TLS communication such as in IoT environment. As a standard software library, PQCryptoLib-Embedded is a versatile tool for developing post-quantum protocols in memory-constrained situations.
PUFcc is an advanced crypto coprocessor that combines a hardware root of trust with a full spectrum of cryptographic algorithms. Equipped with the latest security engines, PUFcc is ideal for integrating complex security protocols across various architectures, including IoT and fintech applications. Its design supports TLS communication protocols and features upgraded algorithms for robust performance and augmented security. PUFcc's architecture includes multiple subprocessors and memory access controls, making it a go-to solution for ensuring secure boot and data protection. As a drop-in security IP, it simplifies SoC design processes, ensuring comprehensive, integrated security from the chip to software layers.
Creonic's Turbo Encoders/Decoders offer advanced error correction features for modern digital communication systems. Originating from iterative decoding theory, the turbo codes provided are known for their efficiency and performance close to Shannon’s limit. These encoders and decoders come in various configurations to suit both existing and emergent network standards such as DVB-RCS2 and 4G LTE. Engineered with scalability in mind, Creonic's Turbo solutions support a wide range of data rates and frame sizes, making them a flexible choice for operators targeting satellite or terrestrial networks. Their modular design ensures easy integration and adaptability across various digital platforms and communication technologies. The products maintain high data integrity, enabling reliable data delivery even in high-noise environments. Creonic ensures that each turbo code solution is compliant with international standards, providing a seamless interoperability experience across diverse network architectures.
FortiCrypt is FortifyIQ's premier product focused on providing ultra-high-level security with unprecedented efficiency. It encompasses a suite of AES solutions that protect against side-channel and fault injection attacks, including SIFA, without compromising on speed, performance, or physical dimensions. The technology harnesses finite field arithmetic for masking methods, safeguarding against attacks while maintaining low latency and high performance, evidenced by its ability to perform at hundreds of Gbps rates. This IP core supports a wide array of configurations, including ultra-low power and ultra-compact modes, making it versatile for battery-powered and space-constrained applications. Tested rigorously using the TVLA methodology, FortiCrypt ensures robust protection across diverse environments, from IoT devices to critical infrastructure.
Creonic's LDPC Encoders/Decoders are engineered to deliver high throughput and low latency for communications and data applications. The exceptional performance of these encoders and decoders ensures that they are ideally suited for applications such as satellite communications, broadband wireless, and high-speed networking. Creonic provides a comprehensive range of LDPC solutions that can be customized to match various standards, including DVB-S2X, 5G NR, IEEE, and CCSDS. Each LDPC solution is robustly engineered, offering maximum flexibility to adapt to different code rates and frame sizes. These cores are implemented to ensure compatibility with diverse FPGA platforms like Xilinx and Intel. Customers benefit from a solid framework that integrates efficient encoding and decoding mechanisms, ensuring reliable data transfer across challenging communication environments. The LDPC products stand out for their superior error correction capabilities, which help in mitigating the adverse effects of signal degradation. Creonic's solutions target both existing and emerging communications standards, ensuring future-proof reliability and performance enhancement.
Post-Quantum Software Library General purpose FIPS 140-3 certified cryptographic library for a wide variety of applications. PQCryptoLib is designed to provide the latest standardized post-quantum and classical algorithms in a software environment. With a configurable, secure and easy to use API, it’s optimized for crypto-agility, particularly when it comes to FIPS compliant hybrid solutions and protecting against harvest-now-decrypt-later attacks. The goal of PQCryptoLib is to help organizations transition to quantum resistance in a manageable, easy-to-integrate solution.
The PSA Compliant Crypto API by Tiempo Secure offers a streamlined interface for implementing cryptographic functions, ensuring robust digital security. It is a comprehensive package that simplifies cryptographic operations while adhering strictly to the Platform Security Architecture (PSA) benchmarks. Engineered for efficiency, the API provides a software library supporting both Physical Unclonable Functions (PUFs) and a True Random Number Generator with Deterministic Random Bit Generator (TRNG+DRBG). Its design ensures minimal on-chip SRAM usage, occupying only a few kilobytes, ideal for space-constrained environments. Platforms integrating this API can achieve the prestigious 'PSA Certified Storage' status, proving compliance with stringent standards. Its extensive logging options, highly optimized SHA-256, and adherence to MISRA C standards make it a robust choice for enhancing system security. This API enables secure storage of arbitrary keys using SRAM PUFs and supports the generation of 256-bit true random seeds, vital for secure operating environments. It simplifies complex security functions, making it an ideal choice for enhancing system protection across various platforms.
The 100 Gbps Polar Encoder and Decoder is engineered for the next-generation communication systems demanding ultra-high data rates and reliability. It employs Polar coding, a recent advancement in code theory, which provides a capacity achieving solution to enhance data transfer efficiency in modern networks, particularly suitable for 5G technologies. This IP core supports data rates up to 100 Gbps, enabling rapid data encoding and decoding essential for high-speed communication backbones. The technology ensures robust error correction and maximal utilization of spectral resources by leveraging the power of Polar code combined with optimized algorithmic implementations. Strategically designed for industry-leading performance, this Polar Encoder and Decoder is applicable in systems where bandwidth efficiency and processing speed are critical. It is highly applicable to the telecommunication industries involved in mobile networks, data centers, and any large-scale data streaming operations.
Trilinear Technologies offers an HDCP Encryption-Decryption Engine that ensures secure transmission of digital content, aligning with the demands of digital rights management in modern electronics. This engine plays a crucial role in protecting high-definition multimedia data from unauthorized access and duplication. By safeguarding digital pathways, it preserves confidentiality and integrity, vital for maintaining intellectual property rights across various platforms. The engine is effective in encrypting and decrypting content with minimal latency, thus preserving the original data's quality and delivery speed. This engine is versatile and built to seamlessly integrate into a wide range of devices, from personal media players to large-scale digital networks. It supports cutting-edge encryption standards, testifying to Trilinear's prowess in engineering secure and reliable solutions for the digital world. Its application-focused design assures stakeholders of its capability to shield content effectively within the complex landscapes of today’s digital ecosystem.
The Platform-Level Interrupt Controller (PLIC) from Roa Logic is a fully configurable and parameterized component, ensuring complete compliance with RISC-V standards. It's designed to manage and streamline the handling of numerous interrupts in a system, offering the flexibility demanded by diverse application needs. This PLIC is ideal for deployments where robust interrupt management is crucial.
The Cortus ULYSS range of automotive microcontrollers is engineered to meet the demands of sophisticated automotive applications, extending from body control to ADAS and infotainment systems. Utilizing a RISC-V architecture, these microcontrollers provide high performance and efficiency suitable for automotive tasks. Each variant within the ULYSS family caters to specific automotive functions, with capabilities ranging from basic energy management to complex networking and ADAS processing. For instance, the ULYSS1 caters to body control applications with a single-core CPU, while the ULYSS3 provides robust networking capabilities with a quad-core, lockstep MPU operating up to 1.5 GHz. The ULYSS line is structured to offer scalability and flexibility, allowing automotive manufacturers to integrate these solutions seamlessly into various components of a vehicle's electronic system. This focus on adaptability helps Cortus provide both a cost-effective and high-performance solution for its automotive partners.
ArrayNav represents a significant leap forward in navigation technology through the implementation of multiple antennas which greatly enhances GNSS performance. With its capability to recognize and eliminate multipath signals or those intended for jamming or spoofing, ArrayNav ensures a high degree of accuracy and reliability in diverse environments. Utilizing four antennas along with specialized firmware, ArrayNav can place null signals in the direction of unwanted interference, thus preserving the integrity of GNSS operations. This setup not only delivers a commendable 6-18dB gain in sensitivity but also ensures sub-meter accuracy and faster acquisition times when acquiring satellite data. ArrayNav is ideal for urban canyons and complex terrains where signal integrity is often compromised by reflections and multipath. As a patented solution from EtherWhere, it efficiently remedies poor GNSS performance issues associated with interference, making it an invaluable asset in high-reliability navigation systems. Moreover, the system provides substantial improvements in sensitivity, allowing for robust navigation not just in clear open skies but also in challenging urban landscapes. Through this additive capability, ArrayNav promotes enhanced vehicular ADAS applications, boosting overall system performance and achieving higher safety standards.
The Polar ID Biometric Security System represents a major innovation in smartphone security, offering a simplified yet highly secure face unlock solution. Unlike traditional systems, Polar ID uses breakthrough meta-optic technology to capture the unique 'polarization signature' of a face, enabling it to detect and prevent spoofing attempts with exceptional accuracy. This system provides more than 10 times the resolution of existing facial authentication solutions, functioning reliably under various light conditions, from bright daylight to complete darkness. It achieves this with a single low-profile near-infrared polarization camera and a 940nm illumination source, eliminating the need for bulky and expensive optical modules. Furthermore, the Polar ID not only reduces the required footprint of the technology, allowing it to fit into more compact form factors, but it also lowers costs, making secure face recognition accessible to a broader range of devices. This advancement in biometric technology is particularly valuable for mobile and consumer electronics, offering enhanced security without sacrificing convenience. The Polar ID sets a new benchmark for mobile security solutions with its unique combination of size, security, and cost-efficiency.
The THOR Toolbox by Presto Engineering is a specialty toolbox that integrates NFC and UHF connectivity, designed to expedite the development and testing of wireless communication interfaces within ASIC designs. This IP supports wireless sensor connectivity and effective RF interfacing through a combination of analog and digital interface methodologies, providing a versatile platform for rapid prototyping and proof-of-concept creation. Engineered to facilitate direct NFC communication and UHF signal reception, the THOR Toolbox allows for efficient data transmission in demanding environments, offering flexibility for integration into various communication protocols and systems. Its design encompasses features aimed at lowering power consumption while maintaining robust connectivity capabilities, which are critical in evolving IoT applications and modern electronic systems. By leveraging the THOR Toolbox, developers can benefit from an accelerated pathway to test, verify, and implement high-performance NFC and UHF solutions. This toolbox serves as a powerful resource in enabling swift adaptation to market needs and is particularly well-suited for applications requiring dependable wireless interaction, such as asset tracking and contactless payment systems.
The Alcora V-by-One HS FMC daughter card by Parretto facilitates the integration of V-by-One HS interfaces into FPGA systems with ease. It provides 8 RX and 8 TX lanes, allowing for a total of 16 lanes when two cards are used, capable of supporting 4K resolutions at 120Hz, or 8K at 30Hz. Designed for versatility, Alcora comes in two configurations: 51-pin and 41-pin headers. Built for stability, it includes two clock generators to synthesize the transceiver reference clock and reduce jitter, optimizing digital video transmission over the high-speed interface. V-by-One HS technology, developed by THine Electronics, Inc., positions the Alcora card as a prime component for high-resolution video and flat panel display markets, bridging the gap between superior video outputs and a variety of digital displays.
ChipJuice is a versatile and potent software tool developed by Texplained to facilitate the reverse engineering of integrated circuits. It is instrumental in various activities, from digital forensics and backdoor research to technology intelligence and IP infringement investigations. The software's intuitive design and sophisticated processing algorithms make it accessible to a broad range of users, including LEAs, chip makers, and research institutions. ChipJuice excels at analyzing the internal architecture of ICs, providing detailed netlists and hardware description language files, which are vital for understanding and securing chip designs.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
Sofics' TakeCharge Electrostatic Discharge (ESD) Solutions are designed to protect delicate semiconductor components from potentially damaging electrostatic discharges. These solutions are applicable across various technology nodes, including the most advanced ones like TSMC's 3nm FinFET processes. Sofics employs innovative design techniques to ensure these ESD protections are both area-efficient and performance-optimized, making them integral to semiconductor products aimed at high-speed, high-performance applications. Sofics' TakeCharge IP is not only aimed at protecting high-speed interfaces such as SerDes but also at enhancing the robustness of die-to-die connections, ensuring secure operation without compromising on speed or functionality. Furthermore, TakeCharge addresses challenges inherent in narrow ESD design windows of FinFET technologies, which are traditionally difficult to manage with conventional approaches. By leveraging proprietary technologies like Silicon Control Rectifiers (SCRs), Sofics' ESD solutions enable more reliable and compact protection strategies, further bolstering their suitability for complex electronics design challenges. Their offerings also extend robustness in applications varying from automotive to data center communications, illustrating a versatile applicability and ensuring consistent device reliability across different industrial sectors. Through its affiliation with various IP alliances and its collaborative approach, Sofics ensures that its ESD solutions are well-integrated into different foundry processes, including those of Intel and TSMC, reflecting its commitment to maintaining a high standard of integration and performance efficiency across diverse fabrication environments.
Creonic’s Miscellaneous FEC and DSP IP Cores are an essential toolkit for enhancing digital signal processing capabilities across various fields. These include solutions like Viterbi Decoders, FFT/IFFT processors, and advanced BCH code implementations, which are cornerstones in data correction and signal processing. These DSP cores are engineered for high performance and efficiency, vital for applications demanding robust signal integrity and processing speed. From Doppler Channel processing found in satellite and radio communications to sophisticated stream processing in broadband networks, every core is fine-tuned for specific performance requirements. Creonic provides adaptable designs that are geared for seamless integration into existing platforms, ensuring continued enhancement of network efficiency and data reliability. The flexibility of these cores means they can be tailored to fit diverse operational standards, making them invaluable in meeting complex communication challenges.
The ATEK367P4 is an analog phase shifter designed to operate within the 2 to 4 GHz frequency band. It is engineered for precision phase control, offering a phase range of 0 to 375 degrees. With a low insertion loss of 3 dB, it is equipped to handle high-performance RF applications that require fine phase adjustment and consistent signal integrity.
The eSi-Crypto suite from EnSilica encompasses a comprehensive range of cryptographic IPs targeted for ASIC and FPGA designs. This suite features low resource consumption and high throughput, crucial for secure and efficient cryptographic solutions. A key component is a robust True Random Number Generator (TRNG) compliant with NIST 800-22, available only as a hard macro. This IP provides essential cryptographic functions such as encryption, decryption, and authentication using algorithms like AES, RSA, ECC/ECDSA, and many more. Designed to cater to the evolving threat of quantum computing, this IP supports post-quantum cryptographic algorithms to future-proof data security. These cryptographic tools are integrated as standalone IPs or come with AMBA AHB/AXI bus interfaces, enabling seamless incorporation into a wide range of customized or standardized security applications across industries.
The Post-Quantum Cryptography (PQC) IP from Secure-IC offers solutions resilient against quantum computing threats. The PQC IP includes a hybrid hardware-software model that enables scalable security across various applications. It forms part of Secure-IC's forward-looking approach to cybersecurity that emphasizes both hardware accelerators and software libraries, which execute key generation and encapsulation with protection against side-channel attacks. This kind of versatility in cryptography makes it an excellent choice for next-generation secure communication platforms.
The SHA-2 Crypto Engine from Tiempo Secure delivers advanced hashing functionality that is pivotal for ensuring data integrity and security in various applications. This IP core stands out for its efficient processing capabilities, supporting hashing functions like SHA-256 and SHA-224. Designed with a 1 cycle per round architecture, the SHA-2 Crypto Engine supports both the import and export of SHA-256 states, catering to even the most complex cryptographic operations. Its ability to handle any message length with bit granularity makes it versatile for wide-ranging applications. Internal padding is seamlessly handled within the IP, and for ease of integration, it comes with wrappers for standard buses such as APB and AXI. This ensures it fits well into a plethora of existing designs, making it a reliable choice for implementing digital signatures and data integrity checks. A unique feature of the SHA-2 Crypto Engine is its readiness to handle pre-padded payloads, optimizing processing without compromising on performance. It empowers developers to boost their system's security robustness while benefiting from an optimized silicon resource-to-performance ratio.
The Xinglian-500 Interconnect Fabric is a self-developed solution by StarFive that focuses on providing consistent memory coherence in multicore CPU and SoC implementations. This IP solution is pivotal in constructing multicore systems by connecting various CPU clusters, I/O devices, and DDR, ensuring efficient data management and communication within high-performance systems. It introduces a network-on-chip (NoC) mechanism that supports multiple CPU clusters, enhancing the overall system performance through streamlined communication paths. The Xinglian-500 is engineered to maintain memory coherence across the SoC environment, making it an invaluable component for developers looking to optimize multicore processing solutions. Due to its scalable architecture, the Xinglian-500 offers flexibility in configuration, readily adapting to the growing demands of computational efficiency. It is designed to support both consumer and enterprise-level applications, enabling lengthy and complex operations with enhanced bandwidth management and reduced latency.
The AES-XTS solution by Helion is tailored for disk encryption, leveraging the Tweakable block cipher algorithm to provide enhanced data security at the sector level on storage devices. The AES-XTS mode is designed to prevent threats like copy-and-paste or dictionary attacks and can independently encrypt and decrypt data in sector-sized blocks. This encryption core is crucial for safeguarding sensitive data on storage arrays, ensuring that identical plaintext blocks placed at different sectors result in distinct ciphertext. Helion offers a variety of AES-XTS cores to address differing data throughput needs, with capabilities ranging from less than 1Gbps to over 64Gbps, making it suitable for singular hard disks to large server arrays. Helion's AES-XTS solutions can be deployed on both ASIC and FPGA platforms, ensuring maximum performance and resource efficiency across varied technological landscapes. They support key sizes of 128-bit and 256-bit, with options for Ciphertext Stealing, adapting to diverse encryption protocols and operational environments.
The Cramium Personal Hardware Security Module (PHSM) from Crossbar is an advanced security solution designed to safeguard digital assets with unparalleled protection. With a unique architecture that combines high-security with ease of use, this module is an integrated single-chip platform capable of executing complex cryptographic computations while ensuring the utmost security of sensitive data like private keys. The PHSM is engineered to perform Multi-Party Computation (MPC) within its secure element, thereby avoiding exposure of key shares, and supports Zero-Knowledge Proof (ZKP) to enhance data protection without unnecessary compromise. Designed to fit into various usage scenarios, from institutional cryptocurrency management to personal security devices, the Cramium PHSM offers a range of key management configurations, including BIP32/39, Multi-Signature wallets, and FIDO2 passkey support. By remaining offline when not actively used, it provides robust safeguarding against unauthorized accesses, marking it as an ideal choice for high-stakes custodianship and secure storage needs. Beyond its traditional usage, the PHSM's capacity for customization and compliance with various protocols places it as a versatile choice for protecting digital identities and assets, suitable for both end-user applications and enterprise-level security systems. This reliability makes it an essential tool for organizations seeking to bolster their defenses amidst increasing cyber threats, particularly those necessitating two-factor authentication and cryptographic safeguards.