All IPs > Security IP
Security IPs are an integral category within the semiconductor industry focusing on the protection of electronic data and hardware. As technological advancements continue to proliferate across critical sectors like finance, healthcare, and automotive, securing data and hardware has never been more paramount. Security IPs are designed to provide essential security features such as encryption, secure communications, and access control to safeguard sensitive information and devices from unauthorized access and cyber threats.
Within the Security IP category, you will find robust offerings that include both hardware and software-based solutions tailored to various security needs. Content Protection Software enables secure data transmission and protects digital content from piracy and unauthorized distribution. Cryptography Cores and Cryptography Software Libraries offer foundational tools for implementing strong encryption algorithms that are crucial for securing communications and data storage.
Embedded Security Modules are integrated within semiconductor devices to facilitate secure data processing and enhance trust in device operations by preventing code tampering and unauthorized hardware modification. Platform Security solutions encompass a broad range of protective measures designed to secure the entire hardware and software ecosystem, ensuring that devices are safe from potential vulnerabilities at every level.
Additionally, Security Protocol Accelerators and Security Subsystems act as dedicated processing units to efficiently handle complex security algorithms and protocols, enhancing the performance of security operations while reducing the burden on primary CPUs. With an unpredictable security landscape, leveraging a range of specialized Security IPs allows designers and engineers to build robust, secure, and reliable semiconductor solutions that can withstand evolving cyber threats.
The 2nd Generation Akida builds upon BrainChip's neuromorphic legacy, broadening the range of supported complex network models with enhancements in weight and activation precision up to 8 bits. This generation introduces additional energy efficiency, performance optimizations, and greater accuracy, catering to a broader set of intelligent applications. Notably, it supports advanced features like Temporal Event-Based Neural Networks (TENNs), Vision Transformers, and extensive use of skip connections, which elevate its capabilities within spatio-temporal and vision-based applications. Designed for a variety of industrial, automotive, healthcare, and smart city applications, the 2nd Generation Akida boasts on-chip learning which maintains data privacy by eliminating the need to send sensitive information to the cloud. This reduces latency and secures data, crucial for future autonomous and IoT applications. With its multipass processing capabilities, Akida addresses the challenge of limited hardware resources smartly, processing complex models efficiently on the edge. Offering a flexible and scalable IP platform, it is poised to enhance end-user experiences across various industries by enabling efficient real-time AI processing on compact devices. The introduction of long-range skip connections further supports intricate neural networks like ResNet and DenseNet, showcasing Akida's potential to drive deeper model efficiencies without excessive host CPU calculation dependence.
Overview: Cybersecurity IPs offer a range of essential security features to protect your digital assets and sensitive information. From True Random Number Generators (TRNG) to advanced encryption algorithms like AES, DES, 3DES, and cryptographic hash functions like SHA, as well as RSA for secure key exchange and digital signatures, the IPs provide a comprehensive suite of tools to safeguard your data. Key Features: True Random Number Generator (TRNG): Generates unpredictable and unbiased random numbers for cryptographic applications. Advanced Encryption Standard (AES): Provides robust encryption with symmetric key algorithms for securing data. Data Encryption Standard (DES) and Triple DES (3DES): Implement legacy encryption algorithms for data protection. Hash Functions: Includes secure cryptographic hash functions like SHA (Secure Hash Algorithm) for data integrity verification. RSA: Enables secure key exchange, encryption, and digital signatures for secure communication. These cybersecurity IPs are designed to meet the stringent security requirements of modern applications, ensuring the confidentiality, integrity, and authenticity of your data.
Overview: The Secure Enclave IPs are Common Criteria (CC) EAL5+PP0084/PP0117 and EAL5+PP0117 certification-ready Secure Enclaves, respectively. They are available as hard macros for seamless integration into SoCs. These Secure Enclave IPs provide the highest level of security for an SoC, incorporating patented design techniques and countermeasures against side-channel and perturbation attacks to ensure robust security while minimizing power consumption. Key Features: Cryptographic Hardware Accelerators: Efficiently support standard cryptography and security operations to increase throughput while adhering to power constraints and security requirements. BootROM and Secondary Boot Loader: Manage the certified life cycle of the Secure Enclave, enforcing and assuring security from manufacturing to deployment. Proprietary IP: Based on proprietary IP that is free of 3rd party rights and royalties. Benefits: The Secure Enclave IPs offer robust security measures, efficient cryptographic support, and secure life cycle management, making them ideal for applications that require the highest levels of security and reliability. Applications: The Secure Enclave IP is versatile and suitable for a wide range of applications, including but not limited to: Secured and Certified iSIM & iUICC EMVco Payment Hardware Cryptocurrency Wallets FIDO2 Web Authentication V2X HSM Protocols Smart Car Access Secured Boot Secure OTA Firmware Updates Secure Debug Any design requiring a Secure Enclave, Secure Element, or Hardware Root of Trust protected against side-channel and perturbation fault attacks. Compliance and Support: The Secure Enclave is compliant with and ready for CC EAL5+ and EMVCo certification. It is delivered with an SDK and pre-certified CryptoLibrary and secure Boot Loader for seamless integration and enhanced security.
Overview: The Secure Boot IP is a turnkey solution that provides a secure boot facility for an SoC. It implements the Post Quantum secure Leighton-Micali Signature (LMS) as specified in NIST SP800-208. The Secure Boot IP operates as a master or slave peripheral to an Application Processor, serving as a secure enclave that securely stores keys to ensure their integrity and the integrity of the firmware authentication process. Features: Post Quantum Secure LMS Signature: Utilizes a robust Post-Quantum secure algorithm for enhanced security. Firmware Updates: Supports up to 32 thousand firmware updates with a minimal signature size of typically less than 5KBytes. SESIP Level 3 Pre-Certification: Pre-certified to SESIP Level 3 for added security assurance. RTL Delivery: Delivered as RTL for ease of integration into SoC designs. Proprietary IP: Based on proprietary IP with no 3rd party rights or royalties. Operation: The Secure Boot IP operates as a master, managing the boot process of the Application Processor to ensure that it only boots from and executes validated and authenticated firmware. The Secure Boot IP also functions as a slave peripheral, where the Application Processor requests validation of the firmware as part of its boot process, eliminating the need for managing keys and simplifying the boot process. Applications: The Secure Boot IP is versatile and suitable for a wide range of applications, including but not limited to: Wearables Smart/Connected Devices Metrology Entertainment Applications Networking Equipment Consumer Appliances Automotive Industrial Control Systems Security Systems Any SoC application that requires executing authenticated firmware in a simple but secure manner.
The Origin E1 is an optimized neural processing unit (NPU) targeting always-on applications in devices like home appliances, smartphones, and security cameras. It provides a compact, energy-efficient solution with performance tailored to 1 TOPS, making it ideal for systems needing low-power and minimal area. The architecture is built on Expedera's unique packet-based approach, which enables enhanced resource utilization and deterministic performance, significantly boosting efficiency while avoiding the pitfalls of traditional layer-based architectures. The architecture is fine-tuned to support standard and custom neural networks without requiring external memory, preserving privacy and ensuring fast processing. Its ability to process data in parallel across multiple layers results in predictive performance with low power and latency. Always-sensing cameras leveraging the Origin E1 can continuously analyze visual data, facilitating smoother and more intuitive user interactions. Successful field deployment in over 10 million devices highlights the Origin E1's reliability and effectiveness. Its flexible design allows for adjustments to meet the specific PPA requirements of diverse applications. Offered as Soft IP (RTL) or GDS, this engine is a blend of efficiency and capability, capitalizing on the full scope of Expedera's software tools and custom support features.
The ADAS and Autonomous Driving solutions from KPIT focus on advancing autonomy in vehicles by addressing key challenges in technology, regulatory compliance, and consumer trust. The solutions include rigorous testing environments and simulation frameworks to explore corner cases and ensure safety. KPIT's autonomous driving solutions aim to enhance feature development, integrate AI-driven decision-making, and provide robust validation environments that empower automakers to deliver safer, reliable autonomous vehicles.
The AHB-Lite APB4 Bridge by Roa Logic represents a pivotal element in connecting different bus standards, essentially acting as a bridge between the AMBA 3 AHB-Lite v1.0 and the AMBA APB v2.0 protocols. This interconnect component is designed to facilitate data transfer and communication between various system components, ensuring efficiency and compatibility across multiple architectures. As a parameterized soft IP core, the bridge allows for extensive customization, tailoring bandwidth and performance requirements to suit specific application demands in both FPGA and ASIC designs. This versatility makes it ideal for use in diverse environments where protocol conversion is necessary. Supporting an array of peripherals, the bridge enables seamless integration and operation within larger, complex architectures. Its design reduces latency and power consumption, making it a preferred choice for creating energy-efficient and high-performance systems. Available for non-commercial licensing, this bridge epitomizes Roa Logic’s commitment to innovation through practical, user-focused IP solutions.
KPIT's iDART platform revolutionizes the diagnostics and after-sales service landscape by integrating advanced software and AI-powered diagnostics. This comprehensive platform offers real-time vehicle data analytics, predictive maintenance, and seamless integration of diagnostic functions, improving first-time fix ratios. By enhancing traditional service models with innovative digital tools, KPIT enables more efficient aftersales processes and improved customer satisfaction.
The RV12 RISC-V Processor from Roa Logic is a highly adaptable, single-issue processor designed to comply with modern RISC-V standards, specifically targeting the embedded systems market. Structured around a 32-bit and 64-bit RISC-V instruction set, the processor employs a Harvard architecture to optimize the bandwidth of instruction and data accesses. It offers enhanced customization and configurability, allowing developers to adapt the processor for a variety of applications. This processor supports modular design approaches and can be efficiently integrated into both FPGA and ASIC designs, making it a versatile choice in the development of cutting-edge technologies. Its industry-standard compliance ensures ease of integration into existing systems that utilize RISC-V specifications, resulting in reduced development time and effort. As part of the broader RISC-V ecosystem promoted by Roa Logic, the RV12 boasts a robust architecture that facilitates experimental and commercial use, providing a solid foundation for innovation. Available for non-commercial purposes through a flexible licensing agreement, it supports the open movement towards collaborative digital innovation.
The AHB-Lite Multilayer Switch from Roa Logic is engineered for high-efficiency performance, serving as an interconnect fabric that supports numerous bus masters and slaves. This architecture is crucial in systems that require low latency data processing and robust bandwidth capacities to handle heavy data traffic between multiple modules. Designed to handle a virtually unlimited number of masters and slaves, this switch enhances system scalability, allowing the seamless expansion of functionalities in complex SOC configurations. Its low latency characteristics ensure data is transmitted with minimal delay, optimizing system performance and stability. Developed for both ASIC and FPGA implementations, this product aligns with AMBA interconnect specifications, ensuring compatibility and simplifying integration into existing designs. Its free non-commercial licensing promotes broader accessibility, encouraging experimentation and adoption in various technological projects.
Post-Quantum Cryptography Processing Engine Adds support for lattice-based cryptographic operations such as ML-KEM and ML-DSA. PQPlatform-Lattice provides post-quantum support for these NIST-standardized algorithms with minimal area, and leverages an existing SHA-3 accelerator, powered by PQShield-supplied firmware. It’s designed for minimal area, and maximum compatibility, and is deployed with optional firmware-backed side-channel resistance.
PUFrt represents PUFsecurity's Hardware Root of Trust solution, delivering essential security functionalities like TRNG, UID, and Secure OTP, all within a robust anti-tamper framework. As the cornerstone of their security offerings, PUFrt is designed to remain tamper-resistant, ensuring that keys and sensitive data stay on the chip, thus binding system integrity to hardware-level security. Utilizing a 1024-bit PUF-based identification, along with the entropic power of a true random number generator, PUFrt creates an unyielding security foundation for varied applications, from simple hardware keys to complex security coprocessors. This technology protects against malicious reverse engineering and counterfeiting, while also offering customization options to fit diverse system requirements, enhancing the security value across industries. Feature-rich and versatile, PUFrt easily integrates into diverse architectures, allowing for its use in a broad array of applications. By partnering with leading chip designers and foundries, PUFsecurity ensures that PUFrt not only meets current security needs but is also prepared to handle future challenges, making it a pivotal component for companies aiming to maintain a secure digital environment.
SphinX is a high-performance AES-XTS encryption and decryption solution known for low latency and uncompromised security. Designed with independent non-blocking channels for encryption and decryption, this product offers robust data protection in real-time applications. Ideal for environments where security and efficiency are critical, SphinX ensures data privacy without affecting system speed.
The Polar ID Biometric Security System is Metalenz's revolutionary solution for face authentication, delivering a new level of biometric security through advanced polarization imaging. Unlike conventional facial recognition systems, Polar ID captures the unique 'polarization signature' of each human face, offering enhanced security by effortlessly differentiating between real faces and potential spoofing attempts with sophisticated 3D masks. This innovative use of meta-optics not only enhances security but also reduces the need for complex optical modules traditionally required in consumer devices. Polar ID stands out in its ability to operate efficiently under varied lighting conditions, from bright sunlight to complete darkness. It achieves this with more than 10 times the resolution of current structured light systems, ensuring reliable and secure facial recognition performance even when users wear glasses or face coverings. By operating in the near-infrared spectrum, Polar ID extends its utility to scenarios previously challenging for facial recognition technology, thus broadening its application range. Designed for mass-market deployment, Polar ID minimizes the footprint and complexity of face unlock systems. By doing away with bulky modules, it offers a compact and cost-effective alternative while maintaining high-security standards. This innovation enables widespread adoption in consumer electronics, allowing a seamless integration into smartphones, tablets, and other mobile devices, potentially replacing less secure biometric methods like fingerprint recognition.
The NaviSoC is a cutting-edge system-on-chip (SoC) that integrates a GNSS receiver and an application processor on one silicon die. Known for its high precision and reliability, it provides users with a compact and energy-efficient solution for various applications. Capable of supporting all GNSS bands and constellations, it offers fast time-to-first-fix, centimeter-level accuracy, and maintains high sensitivity even in challenging environments. The NaviSoC's flexible design allows it to be customized to meet specific user requirements, making it suitable for a wide range of applications, from location-based services to asset tracking and smart agriculture. The incorporation of a RISC-V application microcontroller, along with an array of peripherals and interfaces, introduces expanded functionality, optimizing it for advanced IoT and industrial applications. Engineered for power efficiency, the NaviSoC supports a range of supply voltages, ensuring low power consumption across its operations. The chip's design provides for efficient integration into existing systems with the support of a comprehensive SDK and IDE, allowing developers to tailor solutions to their precise needs in embedded systems and navigation infrastructures.
eSi-Crypto offers a comprehensive suite of encryption and authentication intellectual property tailored for ASIC and FPGA applications. With low resource utilization and high throughput, the package includes True Random Number Generators (TRNGs), adhering to NIST 800-22 standards, available only as hard macros in target technologies. The IP cores can operate independently or interface through AMBA APB/AHB or AXI buses, supporting encryption algorithms such as CRYSTALS Kyber, ECC, RSA, and AES. By focusing on security, eSi-Crypto helps safeguard communications and data integrity, essential in today's digital landscape. The IP suite notably features advanced cryptographic algorithms, ensuring modern applications remain secured against evolving threats.
Roa Logic's Platform-Level Interrupt Controller (PLIC) is a highly parameterized and configurable module that adheres to the RISC-V architecture, intended to manage interrupts in various system designs comprehensively. This component is a critical part of incorporating interactivity and responsiveness in embedded systems, handling a multitude of interrupt sources efficiently. The PLIC's compliance with the RISC-V standard ensures seamless integration into systems using this architecture, enabling straightforward implementation and management of interrupt-related functionality. Its flexible design allows users to customize the number of supported interrupts according to specific needs, making it adaptable to a wide range of applications, from small embedded devices to more complex multicore systems. Overall, Roa Logic’s PLIC offers a scalable solution for systems designers, providing the necessary configurability to tailor the interrupt handling according to platform-specific requirements. Its open-access policy for non-commercial applications further encourages experimentation and innovation within the RISC-V ecosystems.
Akida IP is BrainChip's pioneering neuromorphic processor, crafted to mimic the human brain's analytic capabilities by processing only essential sensor inputs. This localized processing greatly enhances efficiency and privacy, as it significantly reduces the need for cloud data transactions. The processor offers scalable architecture supporting up to 256 nodes interconnected via a mesh network with each node composed of four configurable Neural Network Layer Engines. This event-based technology cuts down operations drastically compared to traditional methods, promoting lower power consumption. With robust support for on-chip learning and incremental learning capabilities, Akida IP is apt for a diverse range of applications and environments. The neural network processor adapts to real-time data seamlessly, creating new avenues for personalized and private on-device AI experiences. The architecture of Akida IP allows it to run complete neural networks, managing various neural network functions in hardware, thus optimizing resource utilization and power efficiency. Integrating Akida IP into systems is straightforward with BrainChip's development ecosystem, facilitating easy evaluation, design, and deployment processes. The Akida PCIe board and additional platform offerings, like the Raspberry Pi kit, promote seamless development and integration for intelligent AI endpoints, perfectly aligning with BrainChip's mission to streamline the implementation of edge AI solutions.
The HDCP Encryption-Decryption Engine developed by Trilinear Technologies is designed to protect digital audio and video content from unauthorized access during transmission. It aligns with the HDCP 2.2 standard, ensuring that all data exchanged between a display source and receiver remains secure and resistant to interception. This solution is vital for industries where content protection is paramount, such as in premium consumer electronics, professional audiovisual setups, and sensitive government or military communication channels. This engine supports the authentication protocols necessary for protected transactions over DisplayPort interfaces, using sophisticated AUX channels to seal data transfer securely. It is engineered to reduce the processing load by offloading encryption tasks from the system processor, thereby enhancing the overall system performance while maintaining robust security. Capable of integrating into a range of devices from set-top boxes to large multimedia systems, the HDCP Encryption-Decryption Engine offers developers a trustworthy method to shield content from piracy and unauthorized dissemination. Its implementation ensures that content providers can operate freely with the assurance that their digital rights are upheld across all endpoints.
Post-quantum cryptography library for memory-constrained platforms PQCryptoLib-Embedded is a version of PQCryptoLib, PQShield’s library of post-quantum cryptographic algorithms, which is designed for microcontrollers or memory-constrained platforms. The library is highly configurable at build time, which means binary size and memory footprint can be minimized, making this product ideal for constrained devices. Efficiency is important in implementing ML-DSA and ML-KEM, especially for devices or networks requiring quantum-safe TLS communication such as in IoT environment. As a standard software library, PQCryptoLib-Embedded is a versatile tool for developing post-quantum protocols in memory-constrained situations.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
The DAES processor is an ultra-secure cryptographic co-processor that efficiently implements the Rijndael encryption algorithm. This processor provides robust support for both 128 and 256-bit key lengths, while also facilitating a variety of block cipher modes such as ECB, CBC, and other standards. It incorporates an internal key expansion module to guarantee prompt and secure data encryption processes, positioning it as a vital asset for environments where data confidentiality is paramount. By integrating smoothly via APB, AHB, and AXI bus interfaces, it adapts seamlessly across differing systems requiring top-tier security.
The Secure OTP (One-Time Programmable) solution by PUFsecurity elevates standard OTP technology by integrating anti-fuse memory and robust encryption techniques, ensuring the high-level protection of sensitive data. This sophisticated approach allows for secure data storage and management, even under duress from advanced attack methodologies. Secure OTP transforms how critical data like encryption keys and configuration states are stored, enabling devices to maintain data integrity during storage and transit. By encapsulating both physical macro implementations and digital RTL designs with intuitive control, Secure OTP allows seamless integration into a host of applications while safeguarding against unauthorized data extraction. The integration of diverse interface protocols makes Secure OTP adaptable to a wide range of industrial requirements. It stands as a robust defensive measure in the face of modern threats, offering reliability in an era where secure data storage solutions are more important than ever.
aiWare stands out as a premier hardware IP for high-performance neural processing, tailored for complex automotive AI applications. By offering exceptional efficiency and scalability, aiWare empowers automotive systems to harness the full power of neural networks across a wide variety of functions, from Advanced Driver Assistance Systems (ADAS) to fully autonomous driving platforms. It boasts an innovative architecture optimized for both performance and energy efficiency, making it capable of handling the rigorous demands of next-generation AI workloads. The aiWare hardware features an NPU designed to achieve up to 256 Effective Tera Operations Per Second (TOPS), delivering high performance at significantly lower power. This is made possible through a thoughtfully engineered dataflow and memory architecture that minimizes the need for external memory bandwidth, thus enhancing processing speed and reducing energy consumption. The design ensures that aiWare can operate efficiently across a broad range of conditions, maintaining its edge in both small and large-scale applications. A key advantage of aiWare is its compatibility with aiMotive's aiDrive software, facilitating seamless integration and optimizing neural network configurations for automotive production environments. aiWare's development emphasizes strong support for AI algorithms, ensuring robust performance in diverse applications, from edge processing in sensor nodes to high central computational capacity. This makes aiWare a critical component in deploying advanced, scalable automotive AI solutions, designed specifically to meet the safety and performance standards required in modern vehicles.
The Dynamic Neural Accelerator II (DNA-II) is an advanced IP core that elevates neural processing capabilities for edge AI applications. It is adaptable to various systems, exhibiting remarkable efficiency through its runtime reconfigurable interconnects, which aid in managing both transformer and convolutional neural networks. Designed for scalability, DNA-II supports numerous applications ranging from 1k MACs to extensive SoC implementations. DNA-II's architecture enables optimal parallelism by dynamically managing data paths between compute units, ensuring minimized on-chip memory bandwidth and maximizing operational efficiency. Paired with the MERA software stack, it provides seamless integration and optimization of neural network tasks, significantly enhancing computation ordering and resource distribution. Its applicability extends across various industry demands, massively increasing the operational efficiency of AI tasks at the edge. DNA-II, the pivotal force in the SAKURA-II Accelerator, brings innovative processing strength in compact formats, driving forward the development of edge-based generative AI and other demanding applications.
Secure Protocol Engines are designed to significantly enhance network and security processing capabilities. This IP offers high-performance processing of network traffic with secure protocol applications. It includes efficient engines for SSL/TLS handshakes and algorithms such as MACsec and IPsec, enabling swift encryption and decryption, thus enhancing security for data centers and similar infrastructures. These engines help in offloading intensive cryptographic operations from CPUs, thereby optimizing performance and resource allocation.
Post-Quantum Software Library General purpose FIPS 140-3 certified cryptographic library for a wide variety of applications. PQCryptoLib is designed to provide the latest standardized post-quantum and classical algorithms in a software environment. With a configurable, secure and easy to use API, it’s optimized for crypto-agility, particularly when it comes to FIPS compliant hybrid solutions and protecting against harvest-now-decrypt-later attacks. The goal of PQCryptoLib is to help organizations transition to quantum resistance in a manageable, easy-to-integrate solution.
The xT CDx is a sophisticated tumor profiling solution designed to advance precision oncology care for solid malignancies. This assay uses next-generation sequencing to assess alterations in 648 genes, identifying single nucleotide variants, multi-nucleotide variants, and insertions/deletions. It also evaluates microsatellite instability status and serves as a companion diagnostic to explore potential treatment avenues according to specific therapeutic product labeling. Uniquely, xT CDx offers mutation profiling through samplings from both formalin-fixed paraffin-embedded tumor tissues and matched normal samples such as blood or saliva, enhancing diagnostic clarity and treatment direction for patients with solid tumors. The comprehensive report generated includes valuable insights that can inform the personalized treatment path for cancer patients.
This innovative system combines voltage droop mitigation with fine-grained DVFS capabilities in a single integrated solution. Its exceptional observability stems from advanced telemetry features that provide critical insights into voltage behavior for optimized silicon management. Utilizing standard-cell design, it effectively responds to droop events with unprecedented speed, reducing voltage margins and enhancing power savings for system-on-chips (SoCs). This solution is robust across different process technologies, ensuring consistency in performance and feature reliability.
802.11 LDPC offers a highly efficient solution for wireless communication systems, ensuring high throughput and dynamic configuration. The design allows frame-to-frame configuration, optimizing the trade-off between throughput and error correction performance. Meeting stringent bit-error-rate and packet-error-rate specifications, this technology is ideal for robust communication systems requiring reliable data transmission.
The AES Key Wrap Core developed by IP Cores, Inc. implements the NIST-approved AES Key Wrap specification, ensuring secure key exchange and management. Utilizing both 128-bit and 256-bit AES keys for wrapping and unwrapping operations, this core fortifies the security infrastructure for communication and encryption-based applications. This IP core excels in scenarios requiring compact size without compromising security, starting from less than 8,000 gates and featuring a fully self-contained design that excludes the need for external memory. This, combined with its flow-through architecture, enhances its simplicity in integration and operation. Available in source code and netlist forms, the core also supports both encryption and decryption-only variants, further offering flexibility to meet varied design needs. Applications include secure key management systems complying with strict security protocols.
The Cramium Personal Hardware Security Module (PHSM) by CrossBar is a cutting-edge security solution designed to enhance the protection and management of digital assets within the crypto industry. Combining microcontroller technology with secure elements, Cramium PHSM delivers a robust security framework that outperforms traditional measures. The module is engineered to offer top-tier tamper-resistance, ensuring that sensitive keys and cryptographic data remain secure against physical and logical threats. Cramium PHSM is pivotal in redefining industry standards by integrating advanced protection mechanisms that cater specifically to the fast-evolving demands of cryptocurrency and blockchain applications. Its architecture is designed for adaptability and high performance, ensuring seamless integration into various systems and promoting secure, decentralized operations. Moreover, CrossBar is committed to providing open-source solutions that foster transparency and reliability in the digital asset space. The PHSM not only bolsters security but also enhances trust, thereby supporting open collaboration and innovation within the industry. By focusing on delivering secure and flexible solutions, the Cramium PHSM is set to play a crucial role in safeguarding digital assets and ensuring the integrity of next-generation secure computing systems. Overall, Cramium PHSM exemplifies CrossBar's forward-thinking approach in addressing the cybersecurity needs of modern technologies, reaffirming their position as leaders in secure memory component design. It supports global security standards, making it indispensable for developers and companies aiming to fortify their digital infrastructure against emerging cyber threats.
The AES Core by Green IP Core is designed for robust encryption standards in digital systems. This core provides advanced encryption standard (AES) operations, implementing secure encryption and decryption processes crucial for protecting sensitive information in today's digital age. With its efficient design, the AES Core ensures data security across various applications, including communications and financial systems. Engineered for flexibility, this core is compatible with a variety of bus systems and interfaces, allowing seamless integration with existing infrastructure. The AES Core can be synthesized across different FPGA platforms, making it an ideal choice for organizations that need reliable encryption solutions adaptable to diverse hardware configurations. Its versatility and compliance with established encryption standards make the AES Core a valuable asset for industries that demand high security. Whether dealing with sensitive data exchanges or protecting intellectual property, the AES Core provides an effective measure against unauthorized access and cyber threats.
The Alcora V-by-One HS FMC daughter card is expertly crafted to bring the high-speed V-by-One HS interface technology to FPGA platforms. This card connects seamlessly to FPGA boards using high-speed transceiver lanes, facilitating video resolutions that reach up to 4K at 120Hz or 8K at 30Hz. Featuring both 51-pin and 41-pin header options, Alcora provides developers with versatile integration capabilities. Its dual clock generators play a crucial role in synthesizing precise transceiver reference clocks while minimizing RX clock jitter, which is pivotal for maintaining video quality and signal integrity. Developed by THine Electronics, V-by-One HS is renowned for its ability to support high-resolution, high-frame-rate video transmission in flat panel displays. This technology's inclusion in Alcora ensures that it meets the rigorous demands of modern video applications, making it a perfect addition for those developing next-generation display solutions.
The HOTLink II core delivers a comprehensive layer 2 hardware implementation tailored for High-Speed Interface (HSI) applications. This core facilitates easy integration through its adept frame interface, supporting full-rate, half-rate, and quarter-rate operations, adhering strictly to established standards. Its design is tailored to seamlessly fit within the F-18 compatible interfaces. Strategically developed for efficiency, it allows precise control processes at the data link layer, reducing latency and optimizing transmission speed. Whether integrated into aerospace systems or complex defense architectures, HOTLink II ensures high-speed, error-free communications crucial for mission-critical scenarios. This solution provides essential functionalities that bolster data exchange in sophisticated environments by minimizing the risk factors inherent in high-velocity data transmissions. With its ability to maintain consistent performance across various rates, HOTLink II stands as a critical solution for modern high-frequency connectivity challenges.
The Securyzr iSSP, or Integrated Security Services Platform, provides a comprehensive security solution for devices throughout their lifecycle. It enables zero-touch security lifecycle services, including provisioning, firmware updates, security monitoring, and device identity management. The platform integrates Secure-IC's Root of Trust, ensuring robust system protection from chip-level threats. By combining strong hardware and software security measures, it ensures end-to-end protection for devices operating in various environments.
PUFsecurity's Flash Protection Series extends the security capabilities of their Hardware Root of Trust across an entire SoC, safeguarding a variety of flash memory resources. This series ensures that embedded and external flash memories, like NAND and NOR, are protected from attacks that jeopardize data integrity and privacy. Utilizing the security mechanisms embedded within their Hardware Root of Trust and Crypto Coprocessor, the Flash Protection Series provides a seamless security barrier for system architectures that rely heavily on flash storage for functionality. This security extends beyond the physical hardware to include software assets, ensuring complete system integrity against increasingly sophisticated threats. By applying PUF-based fingerprints across flash components, the Flash Protection Series establishes an expanded secure perimeter within devices. This approach not only protects firmware and sensitive software embedded in chips but also extends the formidable defense mechanisms of PUFcc across the SoC, demonstrating unparalleled security assurance for high-risk applications.
The FortiPKA-RISC-V is a highly specialized Public Key Algorithm coprocessor designed to streamline cryptographic operations by integrating modular multiplication with protections against side-channel and fault injection threats. It operates without the need for Montgomery domain transformations, optimizing the coprocessor’s performance while reducing area requirements. Tailored for applications demanding high efficiency and security, FortiPKA-RISC-V ensures robust performance in public key operations, suitable for secure communications and data protection scenarios. With a focus on reduced latency and power efficiency, this coprocessor can be implemented in various platforms, enhancing protection in devices and systems The coprocessor is part of FortifyIQ's line of advanced IP solutions, providing a technology-agnostic approach that is adaptable to diverse environments. The FortiPKA-RISC-V offers benefits in applications requiring stringent security and efficiency, making it an ideal solution for developers looking to enhance cryptographic functionalities.
The Aeonic Insight delivers advanced on-die telemetry for SoCs, allowing for actionable insights into power grids, clock health, and silicon security. Suitable for applications ranging from data centers to automotive systems, it features programmability and process portability, ensuring high efficiency and scalability through advanced process technologies. It integrates seamlessly with third-party analytics platforms through industry-standard interfaces.
AndeSoft SW Stack encompasses a comprehensive set of software building blocks and middleware optimized for AndesCore processors. This rich collection includes operating systems, libraries, drivers, and middleware components, all meticulously designed to enhance software development speed and quality. By providing ready-to-use components, AndeSoft enables developers to focus on crafting their application-specific solutions, significantly reducing time-to-market. Its seamless integration with AndeSight IDE further enhances development efficiency, supporting diverse operating systems and being adaptable to various processor configurations for optimal performance.
ArrayNav represents a significant leap forward in navigation technology through the implementation of multiple antennas which greatly enhances GNSS performance. With its capability to recognize and eliminate multipath signals or those intended for jamming or spoofing, ArrayNav ensures a high degree of accuracy and reliability in diverse environments. Utilizing four antennas along with specialized firmware, ArrayNav can place null signals in the direction of unwanted interference, thus preserving the integrity of GNSS operations. This setup not only delivers a commendable 6-18dB gain in sensitivity but also ensures sub-meter accuracy and faster acquisition times when acquiring satellite data. ArrayNav is ideal for urban canyons and complex terrains where signal integrity is often compromised by reflections and multipath. As a patented solution from EtherWhere, it efficiently remedies poor GNSS performance issues associated with interference, making it an invaluable asset in high-reliability navigation systems. Moreover, the system provides substantial improvements in sensitivity, allowing for robust navigation not just in clear open skies but also in challenging urban landscapes. Through this additive capability, ArrayNav promotes enhanced vehicular ADAS applications, boosting overall system performance and achieving higher safety standards.
The Lancero JPEG-LS Encoder IP is a highly efficient FPGA-based implementation of the JPEG-LS standard, designed for superior lossless image compression. This IP core sets a high benchmark for image compression with minimal resource usage and eliminates the need for external memory. JPEG-LS excels in lower complexity and resource demand compared to JPEG-2000, delivering better compression for numerous lossless scenarios. The core is capable of handling image samples ranging from 8 to 16 bits, providing flexibility across various image-processing tasks. Its architecture supports pixel and data FIFO interfaces in addition to the Avalon Streaming interface with back-pressure control, ensuring robust data management and throughput. The IP's design allows one pixel to be encoded per clock cycle, optimizing performance for high-speed image processing applications. Developers can configure output data word widths and adapt image sizes up to ultra-high-definition, accommodating diverse applications from medical imaging to high-end photography.
Post-Quantum Cryptography Processing Engine Adds support for lattice-based cryptographic operations such as ML-KEM and ML-DSA. PQPlatform-Lattice provides post-quantum support for these NIST-standardized algorithms with minimal area, and leverages an existing SHA-3 accelerator, powered by PQShield-supplied firmware. It’s designed for minimal area, and maximum compatibility, and is deployed with optional firmware-backed side-channel resistance.
Post-Quantum Security Subsystem A cryptographic subsystem, designed to provide cryptographic services. These services include post-quantum signature generation, verification, and secure key establishment. PQPlatform-SubSys uses its built-in CPU independently from the surrounding system, allowing cryptographic services to be offloaded efficiently from the system processor.
ParkerVision's D2D® Technology revolutionizes RF communication by enabling direct conversion from RF signals to digital data, bypassing traditional intermediate frequency stages. This technology is instrumental in streamlining signal processing, enhancing speed and efficiency of data handling in various wireless communication devices. The D2D technology supports a broad spectrum of applications, including mobile phones, wireless internet, and IoT devices, delivering high performance and adaptability for current and forthcoming technological needs. D2D® shines in its ability to sustain high data rates necessary for modern applications like 4G and 5G networks, bolstering the capabilities of RF integrated circuits with its advanced conversion techniques. Furthermore, this technology is central to facilitating seamless integration across different communication standards, allowing devices to operate over multiple frequency bands without compromising on data quality or speed. The intellectual property surrounding D2D® is robustly protected with a comprehensive patent portfolio, ensuring its exclusivity and opening avenues for strategic partnerships and licensing. By harnessing this technology, devices gain enhanced power efficiency and broader operational capabilities while lowering manufacturing costs and conserving energy, making it a pivotal innovation for evolving communication landscapes.
Helion Technology's AES-XTS solution offers state-of-the-art encryption for data-at-rest in storage systems, adept at mitigating threats such as copy-paste and dictionary attacks. AES-XTS operates by encrypting disk sector data with blocks of 16-bytes under a secret AES key, incorporating a modifier value corresponding to each block's logical disk location. This method ensures that identical plaintext sectors stored at different positions yield different encrypted outputs. Designed to handle high performance requirements, Helion's AES-XTS cores enable custom levels of throughput scaling from 1Gbps up to over 64Gbps, suitable for diverse scenarios like servers and high-speed SSDs. The product range includes single, twin, quad, and giga variants, aligning closely with specific performance and logic resource parameters, optimizing both hardware usage and security efficacy. This flexibility and adherence to the IEEE 1619 standard make Helion's AES-XTS cores valuable for any application demanding secure disk-level encryption. Available for either ASIC or FPGA platforms, these cores are constructed to leverage the unique capabilities of each technology, achieving the best possible performance across different use cases.
Tailored specifically for AI and machine learning requirements at the edge, the SiFive Intelligence X280 brings powerful capabilities to data-intensive applications. This processor line is part of the high-performance AI data flow processors from SiFive, designed to offer scalable vector computation capabilities. Key features include handling demanding AI workloads, efficient data flow management, and enhanced object detection and speech recognition processing. The X280 is equipped with vector processing capabilities that include a 512-bit vector length, single vector ALU VCIX (1024-bit), plus a host of new instructions optimized for machine learning operations. These features provide a robust platform for addressing energy-efficient inference tasks, driven by the need for high-performance yet low-power computing solutions. Key to the X280's appeal is its ability to interface seamlessly with popular machine learning frameworks, enabling developers to deploy models with ease and flexibility. Additionally, its compatibility with SiFive Intelligence Extensions and TensorFlow Lite enhances its utility in delivering consistent, high-quality AI processing in various applications, from automotive to consumer devices.
SystemBIST is an advanced product offering from Intellitech that provides a plug-and-play solution for flexible FPGA configuration and embedded JTAG testing. It stands out with its proprietary architecture that allows for efficient, codeless configuration of field-programmable gate arrays (FPGAs) as well as built-in system testing capabilities. SystemBIST is designed to be vendor-neutral, supporting any FPGA or CPLD compliant with the IEEE 1532 or IEEE 1149.1 standards. This design enables robust anti-tamper measures and enhances system reliability by embedding JTAG test patterns directly into PCBs.
Monolithic Microsystems from Imec are revolutionizing how electronic integration is perceived by offering a platform that seamlessly combines microelectronics and microsystems. These systems are engineered to provide high functionality while maintaining a compact footprint, making them ideal for applications in areas like sensing, actuation, and control across a variety of sectors including industrial automation, medical devices, and consumer electronics. The Monolithic Microsystems platform enables the integration of various subsystems onto a single semiconductor chip, thereby reducing the size, power consumption, and cost of complex electronic devices. This not only streamlines device architecture but also enhances reliability and performance by mitigating the interconnect challenges associated with multi-chip assemblies. Imec’s comprehensive resources and expertise in semiconductor manufacturing are harnessed to deliver solutions that meet the rigorous demands of cutting-edge applications. From design to production, the Monolithic Microsystems offer a leap in capability for next-generation devices, facilitating innovations that require robust, integrated microsystem technologies.
Post-quantum Software Development Kit Provides easy-to-use software implementations of both post-quantum and classical cryptographic primitives. It’s designed with prototyping and experimentation in mind, consisting of an integration of PQShield’s PQCryptoLib library with two popular high-level cryptography libraries: OpenSSL and mbedTLS. OpenSSL: a widely-adopted secure-communication library mbedTLS: primarily intended for use in embedded system and IoT deployments
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