All IPs > Security IP > Security Protocol Accelerators
Security Protocol Accelerators are crucial components within the realm of semiconductor IP, designed to boost the performance of security protocols in various applications. These accelerators play a pivotal role in enhancing the speed, efficiency, and reliability of data encryption and decryption processes, which are fundamental for secure communications and transactions across networks. By implementing specialized hardware for protocol acceleration, these semiconductor IPs offer significant improvements in processing speed compared to software-only solutions.
One of the primary uses of Security Protocol Accelerators is in network security devices, including routers, firewalls, and VPNs, where they ensure secure communication by accelerating tasks such as data encryption and IPsec processing. As data breaches and cyber threats continue to evolve, the demand for robust and efficient security solutions has never been higher. These accelerators enable the optimization of cryptographic operations, providing enterprises and individuals with the confidence that their sensitive data is well-protected during transmission.
In consumer electronics like smartphones, tablets, and smart home devices, security protocol accelerators are key to maintaining user privacy without compromising on performance. They ensure that devices can handle complex security tasks quickly, extending battery life and maintaining seamless user experiences. Whether it’s ensuring the security of cloud-based services or protecting communications over Wi-Fi and cellular networks, these semiconductor IPs are increasingly vital in an interconnected world.
Moreover, the rise of IoT devices and edge computing has expanded the need for security protocol accelerators. With the massive data exchange happening at the edge of networks, having efficient security IPs ensures not just the safety of the data but also compliance with regulatory standards. As companies continue to push for innovations in AI and machine learning, the integration of security protocol accelerators in their systems helps to safeguard intellectual property and sensitive algorithms, thereby maintaining a secure operational environment. Through leveraging these semiconductor IPs, creators can focus on innovation while relying on proven security foundations.
The 2nd Generation Akida processor introduces groundbreaking enhancements to BrainChip's neuromorphic processing platform, particularly ideal for intricate network models. It integrates eight-bit weight and activation support, improving energy efficiency and computational performance without enlarging model size. By supporting an extensive application set, Akida 2nd Generation addresses diverse Edge AI needs untethered from cloud dependencies. Notably, Akida 2nd Generation incorporates Temporal Event-Based Neural Nets (TENNs) and Vision Transformers, facilitating robust tracking through high-speed vision and audio processing. Its built-in support for on-chip learning further optimizes AI efficiency by reducing reliance on cloud training. This versatile processor fits perfectly for spatio-temporal applications across industrial, automotive, and healthcare sectors. Developers gain from its Configurable IP Platform, which allows seamless scalability across multiple use cases. The Akida ecosystem, including MetaTF, offers developers a strong foundation for integrating cutting-edge AI capabilities into Edge systems, ensuring secure and private data processing.
SphinX offers high-performance and low-latency encryption/decryption through AES-XTS, an industry-standard for data protection. Its independent and non-blocking encryption and decryption channels make it particularly valuable for enhancing data security in high-throughput environments. This technology is crucial for organizations that prioritize data integrity and confidentiality alongside operational efficiency. The SphinX solution ensures that sensitive data is safeguarded without compromising on speed or reliability, making it ideal for applications where both security and performance are critical. Its design allows for seamless integration into existing systems, minimizing the resource drain on processing power while offering robust security features. By focusing on ultra-low latency, SphinX is apt for use in fast-paced environments such as financial services, healthcare, and other sectors dealing with sensitive information. This highlights ZeroPoint Technologies’ commitment to providing cutting-edge solutions that navigate the complexities of modern data security demands, catering to both integrity and speed requirements.
PUFrt serves as a foundational hardware root of trust, featuring advanced key generation and storage capabilities inherent to the chip. It integrates a true random number generator (TRNG) and hardcore anti-tamper protections. With a built-in secure OTP, PUFrt provides unrivaled security for sensitive data, ensuring encryption and decryption processes are secured at the hardware level. This IP is adept at securing the semiconductor supply chain, countering the risks of reverse engineering and ensuring device authenticity through its robust identification systems. PUFrt features extensive customization options and interfaces for integration across diverse architectures, aiming to minimize user effort in embedding security functions within complex systems.
The xT CDx is an advanced FDA-approved assay designed for tumor and normal DNA sequencing. Incorporating a comprehensive 648-gene panel, this assay provides critical insights for diagnosing and treating solid tumors, with specific functions in guiding targeted therapies in colorectal cancer patients. The test includes a thorough mutation profiling system that allows healthcare professionals to analyze substitutions, insertions, and deletions, delivering a powerful means to refine treatment options. Beyond the standard, the xT CDx offers tumor and normal matched sequencing to distinguish somatic alterations, reducing false-positive results and improving accuracy in clinical assessments. Its integration into clinical practices is supported by its compatibility with various companion diagnostic claims, making it an essential tool for aligning treatment decisions with approved therapeutic products. By utilizing next-generation sequencing technologies, the xT CDx supports the optimization of treatment pathways and enhances patient care through detailed molecular insights. With the capacity to perform detailed analyses on formalin-fixed paraffin-embedded tumor tissues and matched normal samples, this assay promises high specificity and sensitivity in tumor profiling. Leveraging Tempus' cutting-edge bioinformatics infrastructure, the xT CDx ensures healthcare providers can make informed decisions supported by rich genetic data, setting a transformative benchmark in precision oncology.
Secure Protocol Engines by Secure-IC are designed to offload network and security processing tasks in high-performance computing environments. These engines provide specialized IP blocks that can handle complex cryptographic protocols efficiently. The solution optimizes system performance by allowing primary processors to focus on core functionalities while the protocol engines manage the security operations. This capability is crucial for systems requiring robust security without compromising on speed or efficiency, such as in telecommunication or data center applications.
The AES Encrypt/Decrypt module offers robust security features, accommodating 128/192/256-bit keys for both encryption and decryption tasks. This module is engineered for low latency and minimal power consumption, making it suitable for high-demand environments where security and performance are critical. The design implements Galois Field calculations using an 8-bit primitive polynomial, enabling parallel processing of key calculation and data encryption to minimize clock cycle use. The flexibility of the module is evident in its runtime programmability, ensuring that each operation can be tailored to meet specific security and performance criteria. Applications span across secure communications and any data exchange requiring high encryption standards, with the system delivering verified RTL against a broad suite of scenarios to guarantee functional integrity.
Efinix's Topaz FPGA series is engineered for mass-market applications, delivering a perfect mix of efficiency and adaptability. These FPGAs encapsulate a highly efficient architecture, combined with the industry's essential features and protocols, such as PCIe Gen3, MIPI, and LPDDR4. This configuration allows users to harness substantial performance while maintaining ample room for future innovations. Topaz FPGAs are optimized for high-volume production environments where cost-effectiveness and swift integration are paramount. Their design promotes ease of implementation in various applications, spanning from automotive to deeply embedded systems, where reliability and robustness are key. Featuring a streamlined architecture, Topaz series FPGAs support modern connectivity standards and data processing capabilities. These devices are tailored for industries requiring scalable solutions that can adapt to evolving technological landscapes, ensuring that Efinix customers remain competitive in their respective fields.
PUFcc is an advanced crypto coprocessor that combines a hardware root of trust with a full spectrum of cryptographic algorithms. Equipped with the latest security engines, PUFcc is ideal for integrating complex security protocols across various architectures, including IoT and fintech applications. Its design supports TLS communication protocols and features upgraded algorithms for robust performance and augmented security. PUFcc's architecture includes multiple subprocessors and memory access controls, making it a go-to solution for ensuring secure boot and data protection. As a drop-in security IP, it simplifies SoC design processes, ensuring comprehensive, integrated security from the chip to software layers.
FortiCrypt is FortifyIQ's premier product focused on providing ultra-high-level security with unprecedented efficiency. It encompasses a suite of AES solutions that protect against side-channel and fault injection attacks, including SIFA, without compromising on speed, performance, or physical dimensions. The technology harnesses finite field arithmetic for masking methods, safeguarding against attacks while maintaining low latency and high performance, evidenced by its ability to perform at hundreds of Gbps rates. This IP core supports a wide array of configurations, including ultra-low power and ultra-compact modes, making it versatile for battery-powered and space-constrained applications. Tested rigorously using the TVLA methodology, FortiCrypt ensures robust protection across diverse environments, from IoT devices to critical infrastructure.
The 100 Gbps Polar Encoder and Decoder is engineered for the next-generation communication systems demanding ultra-high data rates and reliability. It employs Polar coding, a recent advancement in code theory, which provides a capacity achieving solution to enhance data transfer efficiency in modern networks, particularly suitable for 5G technologies. This IP core supports data rates up to 100 Gbps, enabling rapid data encoding and decoding essential for high-speed communication backbones. The technology ensures robust error correction and maximal utilization of spectral resources by leveraging the power of Polar code combined with optimized algorithmic implementations. Strategically designed for industry-leading performance, this Polar Encoder and Decoder is applicable in systems where bandwidth efficiency and processing speed are critical. It is highly applicable to the telecommunication industries involved in mobile networks, data centers, and any large-scale data streaming operations.
Trilinear Technologies offers an HDCP Encryption-Decryption Engine that ensures secure transmission of digital content, aligning with the demands of digital rights management in modern electronics. This engine plays a crucial role in protecting high-definition multimedia data from unauthorized access and duplication. By safeguarding digital pathways, it preserves confidentiality and integrity, vital for maintaining intellectual property rights across various platforms. The engine is effective in encrypting and decrypting content with minimal latency, thus preserving the original data's quality and delivery speed. This engine is versatile and built to seamlessly integrate into a wide range of devices, from personal media players to large-scale digital networks. It supports cutting-edge encryption standards, testifying to Trilinear's prowess in engineering secure and reliable solutions for the digital world. Its application-focused design assures stakeholders of its capability to shield content effectively within the complex landscapes of today’s digital ecosystem.
Sofics' TakeCharge Electrostatic Discharge (ESD) Solutions are designed to protect delicate semiconductor components from potentially damaging electrostatic discharges. These solutions are applicable across various technology nodes, including the most advanced ones like TSMC's 3nm FinFET processes. Sofics employs innovative design techniques to ensure these ESD protections are both area-efficient and performance-optimized, making them integral to semiconductor products aimed at high-speed, high-performance applications. Sofics' TakeCharge IP is not only aimed at protecting high-speed interfaces such as SerDes but also at enhancing the robustness of die-to-die connections, ensuring secure operation without compromising on speed or functionality. Furthermore, TakeCharge addresses challenges inherent in narrow ESD design windows of FinFET technologies, which are traditionally difficult to manage with conventional approaches. By leveraging proprietary technologies like Silicon Control Rectifiers (SCRs), Sofics' ESD solutions enable more reliable and compact protection strategies, further bolstering their suitability for complex electronics design challenges. Their offerings also extend robustness in applications varying from automotive to data center communications, illustrating a versatile applicability and ensuring consistent device reliability across different industrial sectors. Through its affiliation with various IP alliances and its collaborative approach, Sofics ensures that its ESD solutions are well-integrated into different foundry processes, including those of Intel and TSMC, reflecting its commitment to maintaining a high standard of integration and performance efficiency across diverse fabrication environments.
The eSi-Crypto suite from EnSilica encompasses a comprehensive range of cryptographic IPs targeted for ASIC and FPGA designs. This suite features low resource consumption and high throughput, crucial for secure and efficient cryptographic solutions. A key component is a robust True Random Number Generator (TRNG) compliant with NIST 800-22, available only as a hard macro. This IP provides essential cryptographic functions such as encryption, decryption, and authentication using algorithms like AES, RSA, ECC/ECDSA, and many more. Designed to cater to the evolving threat of quantum computing, this IP supports post-quantum cryptographic algorithms to future-proof data security. These cryptographic tools are integrated as standalone IPs or come with AMBA AHB/AXI bus interfaces, enabling seamless incorporation into a wide range of customized or standardized security applications across industries.
The Post-Quantum Cryptography (PQC) IP from Secure-IC offers solutions resilient against quantum computing threats. The PQC IP includes a hybrid hardware-software model that enables scalable security across various applications. It forms part of Secure-IC's forward-looking approach to cybersecurity that emphasizes both hardware accelerators and software libraries, which execute key generation and encapsulation with protection against side-channel attacks. This kind of versatility in cryptography makes it an excellent choice for next-generation secure communication platforms.
The Xinglian-500 Interconnect Fabric is a self-developed solution by StarFive that focuses on providing consistent memory coherence in multicore CPU and SoC implementations. This IP solution is pivotal in constructing multicore systems by connecting various CPU clusters, I/O devices, and DDR, ensuring efficient data management and communication within high-performance systems. It introduces a network-on-chip (NoC) mechanism that supports multiple CPU clusters, enhancing the overall system performance through streamlined communication paths. The Xinglian-500 is engineered to maintain memory coherence across the SoC environment, making it an invaluable component for developers looking to optimize multicore processing solutions. Due to its scalable architecture, the Xinglian-500 offers flexibility in configuration, readily adapting to the growing demands of computational efficiency. It is designed to support both consumer and enterprise-level applications, enabling lengthy and complex operations with enhanced bandwidth management and reduced latency.
The AES-XTS solution by Helion is tailored for disk encryption, leveraging the Tweakable block cipher algorithm to provide enhanced data security at the sector level on storage devices. The AES-XTS mode is designed to prevent threats like copy-and-paste or dictionary attacks and can independently encrypt and decrypt data in sector-sized blocks. This encryption core is crucial for safeguarding sensitive data on storage arrays, ensuring that identical plaintext blocks placed at different sectors result in distinct ciphertext. Helion offers a variety of AES-XTS cores to address differing data throughput needs, with capabilities ranging from less than 1Gbps to over 64Gbps, making it suitable for singular hard disks to large server arrays. Helion's AES-XTS solutions can be deployed on both ASIC and FPGA platforms, ensuring maximum performance and resource efficiency across varied technological landscapes. They support key sizes of 128-bit and 256-bit, with options for Ciphertext Stealing, adapting to diverse encryption protocols and operational environments.
The Cramium Personal Hardware Security Module (PHSM) from Crossbar is an advanced security solution designed to safeguard digital assets with unparalleled protection. With a unique architecture that combines high-security with ease of use, this module is an integrated single-chip platform capable of executing complex cryptographic computations while ensuring the utmost security of sensitive data like private keys. The PHSM is engineered to perform Multi-Party Computation (MPC) within its secure element, thereby avoiding exposure of key shares, and supports Zero-Knowledge Proof (ZKP) to enhance data protection without unnecessary compromise. Designed to fit into various usage scenarios, from institutional cryptocurrency management to personal security devices, the Cramium PHSM offers a range of key management configurations, including BIP32/39, Multi-Signature wallets, and FIDO2 passkey support. By remaining offline when not actively used, it provides robust safeguarding against unauthorized accesses, marking it as an ideal choice for high-stakes custodianship and secure storage needs. Beyond its traditional usage, the PHSM's capacity for customization and compliance with various protocols places it as a versatile choice for protecting digital identities and assets, suitable for both end-user applications and enterprise-level security systems. This reliability makes it an essential tool for organizations seeking to bolster their defenses amidst increasing cyber threats, particularly those necessitating two-factor authentication and cryptographic safeguards.
FortiMac provides a reliable HMAC SHA2 IP core solution with advanced resistance against DPA and FIA, utilizing a minimal number of digital gates for an efficient security measure. Its underlying protection is built on the Threshold Implementation strategy, which offers formidable resistance against SCA and FI attacks. This IP stands out as the sole market component offering pure software solutions with robust algorithmic safeguards. FortiMac effectively supports various SHA schemes and ensures SCA and FIA protection on multiple processor architectures, making it adaptable for a range of applications including secure communications and automotive systems.
FortiPKA-RISC-V is a specialized public key accelerator that enhances the performance of complex cryptographic operations while ensuring protection against SCA and FIA threats. Designed for embedded systems and IoT devices, this IP employs modular multiplication and eliminates the need for Montgomery domain transformations, thereby streamlining operations and optimizing area usage. It offers an extensive support for a variety of cryptographic algorithms, including RSA and ECC, providing a comprehensive cryptographic capability suitable for a range of security-intense applications. This product is engineered to enhance data protection while improving system performance, crucial for compliance with demanding industry standards.
Securyzr Integrated Security Services Platform (iSSP) is a comprehensive lifecycle management solution. This platform allows Secure-IC's clients to monitor, manage, and secure their embedded devices throughout their operational lifecycle. It enables provisioning, firmware updates, security monitoring, and device identity management with high ease and trustworthiness. This solution facilitates zero-touch lifecycle services, significantly enhancing the security posture of device fleets in dynamic environments, thus demanding minimal interruption in ongoing operations.
The AES Encryption for RFID applications is engineered to provide robust security for data in RFID communications. Utilizing Advanced Encryption Standard (AES) techniques, it offers a secure and efficient mechanism for protecting sensitive information transmitted in RFID systems. This encryption solution is ideal for applications where data integrity and confidentiality are paramount, protecting against unauthorized access and ensuring secure wireless transactions.
The JPEG-LS Encoder by Parretto is a powerful implementation aimed at providing superior lossless image compression. Known for its efficient use of resources, this encoder only requires minimal system memory and operates with less than one line of latency. Focusing on high-quality image compression, the JPEG-LS outperforms traditional JPEG-2000 standards, supporting depths of 8 to 16 bits per image sample. It ensures rapid performance by encoding one pixel per clock cycle, facilitating swift integration into streaming data interfaces. Configurable for various image sizes, even reaching ultra-high definition levels, this encoder supports customizable output data word width. It can be flexibly employed to maintain image fidelity in a diverse range of applications, from medical imaging to security systems.
The Quantum Resistant Encryption Core is designed to offer robust security against emerging quantum threats. It features algorithms curated to withstand quantum computing capabilities, thus ensuring that sensitive information remains safeguarded. The solution forms an integral part of Crypto Quantique’s security architecture, leveraging their deep understanding of cryptographic principles to fortify device security. This core employs high-level encryption standards and is developed to support rapid integration into existing digital infrastructures. One of its standout features is its adaptability, meaning it can be implemented across a range of devices and platforms with minimal disruption. This versatility is crucial given the diverse nature of devices within the IoT ecosphere. Moreover, the Quantum Resistant Encryption Core is engineered with performance in mind, efficiently managing resources to ensure that security does not come at the expense of processing speed or energy consumption. Incredible resilience against future threats is provided by the integration of post-quantum cryptographic standards. Traditional cryptographic methods face significant risks as quantum computing technology becomes more prevalent, making quantum-resistant solutions imperative for long-term security strategy. This core solution by Crypto Quantique thus ensures devices remain protected well into the future, maintaining the integrity and confidentiality of data.
The AES (standard modes) product from Helion offers a robust encryption solution featuring the Advanced Encryption Standard (AES) algorithm, a 128-bit block cipher known for its efficiency and security. With key sizes of 128, 192, and 256 bits, the AES algorithm complies with NIST standards and is recognized globally for securing sensitive information. This product caters to applications necessitating rapid data processing and heightened security, such as in IPsec, wireless communication, and storage encryption. Helion's AES cores are crafted to deliver optimal performance across a vast array of settings, including both ASIC and FPGA implementations. The cores are designed with scalability in mind, accommodating applications from minimal data rates up to multi-gigabit transmission speeds. Thanks to their architecture, these cores maintain high usability, enabling easy adoption and integration into user systems without excessive resource allocation. Helion's AES suite includes numerous versions tailored to meet varying data transmission needs, ensuring adaptability in resource-constrained environments. Users benefit from the choice of low-power, space-efficient, and high-speed solutions, supporting a wide range of encryption requirements. These cores are also compatible with an array of programmable technologies, reaffirming their utility across diverse platforms, from commercial applications to government-level data protection setups.
The FPGA Lock Core is designed to secure FPGA designs and prevent IP theft, utilizing a Microchip ATSHA204A hardened crypto authentication IC. This small FPGA core, which communicates via a single FPGA pin, aims to block unlicensed access to FPGA functionalities by leveraging crypto-authentication. It operates by executing a secure hashing sequence that ensures only authorized hardware is used, thus safeguarding against counterfeiting and unauthorized duplication. When activated, the core sends a unique 256-bit challenge to the ATSHA204A which, along with its unique ID and a secret key, generates a SHA256 hash. This result is then checked against an internally computed hash within the FPGA Lock core, enabling full functionality of the FPGA only if the hashes match. This method ensures hardware integrity across various applications, including Military, Defense, and Medical fields. The hardware implementation is minimalist, requiring only the ATSHA204A, a pull-up resistor, and a capacitor, offering a low-cost solution. The core, which occupies about 720 registers, is provided in clear VHDL, ensuring full functional transparency. Adaptable to Intel and Xilinx FPGAs, the lock mechanism can be integrated into existing projects with ease, and example designs for Cyclone10 and Artix evaluation boards demonstrate its application.
The L5-Direct GNSS Receiver by oneNav is a groundbreaking solution that focuses on acquiring advanced L5-band signals for positioning with unparalleled accuracy and reliability. This receiver breaks free from the limitations inherent in traditional L1-first GNSS systems by directly tracking L5 signals, which are crucial for reducing vulnerabilities to interference and improving positioning performance in complex urban landscapes. With L5, users benefit from features such as rapid acquisition, reduced power consumption, and immunity to signal disruption, which are crucial for modern navigation devices. This GNSS receiver's design is optimized for the diverse spectrum of modern devices including smartphones, smartwatches, IoT devices, and automotive applications. It leverages a single RF chain for multi-constellation L5-band signals, thereby minimizing the complexity and footprint of RF components. Moreover, the innovative use of AI and machine learning models significantly enhances multipath mitigation and positioning accuracy by utilizing the unique characteristics of the GNSS signals available. Designed to be portable and flexible, oneNav's L5-Direct solution can be integrated into a wide range of semiconductor processes, making it a versatile and efficient GNSS solution. Its digital IP core is scalable, easily programmable, and comes with a comprehensive test bench for rapid deployment. Proving its practicality and effectiveness, this technology has been successfully synthesized at leading manufacturing nodes such as TSMC 12nm and GlobalFoundries 22FDX, ensuring reliability and high performance across various environments.
Calibrator for AI-on-Chips is designed to enhance precision and performance in AI System-on-Chips using post-training quantization techniques. By employing architecture-aware algorithms, this calibrator maintains high accuracy levels even in fixed-point architectures such as INT8. It supports heterogeneous multicore devices, ensuring compatibility with various processing engines and bit-width configurations. The product utilizes a sophisticated precision simulator for accurate quantization across data paths, leveraging hardware-specific controls for precise calibration. The included calibration workflow efficiently produces a quantization table that seamlessly integrates with compilers to fine-tune model precision without altering neural network topologies. Supporting interoperability with popular frameworks, the Calibrator for AI-on-Chips enhances performance without necessitating retraining. Users benefit from expedited quantization processes, which reduce the precision drop to minimal levels, thus ensuring high-quality outputs even for complex AI models.
The DAES is a versatile cryptographic processor designed to implement the AES encryption algorithm efficiently. It supports key lengths of 128 and 256 bits, providing flexibility across various cryptographic requirements. The processor is compatible with multiple block cipher modes, including ECB, CBC, CFB, OFB, and CTR. Enhanced by an internal key expansion feature, the DAES ensures robust data security, making it suitable for applications requiring high levels of encryption reliability, such as secure communications and data protection in embedded systems.
The ONNC Compiler is an advanced suite of C++ libraries and tools designed to enhance the development of compilers for deep learning accelerators (DLAs). Targeting diverse system-on-chip (SoC) architectures, from single-core systems to complex heterogeneous setups, it transforms neural networks into machine instructions for various processing elements. This versatility allows for seamless integration across different SoC architectures with varied memory and bus configurations. Supported by major deep learning frameworks like PyTorch and TensorFlow, the ONNC Compiler provides significant flexibility in handling multiple machine instruction streams concurrently. Utilizing both single and multiple backend modes, it caters to a broad spectrum of IC designs. The comprehensive compiler flow, divided into frontend, middle-end, and backend stages, ensures optimal performance while minimizing the memory footprint through strategic data bandwidth and resource scheduling. Enhancing AI SoCs with a robust hardware/software co-optimization approach, the ONNC Compiler employs advanced strategies like software pipelining and DMA allocation. It effectively manages complex memory hierarchies and bus systems, ensuring efficient data movement and reducing overhead. This results in substantial RAM savings and higher processing efficacy in AI-centric systems.
The AES Core is a high-performance encryption solution tailored for securing digital data. Designed to meet modern security standards, this core offers robust encryption capabilities suitable for various applications, ranging from consumer devices to industrial systems. It supports a scalable key size, providing flexibility and enhanced security. With its optimized architecture, the AES core ensures quick data processing while maintaining low power consumption, making it ideal for battery-operated systems. Additionally, the core is easily configurable to adapt to different system requirements, making it a versatile choice for developers looking to integrate state-of-the-art encryption into their products.
The DSHA2-256 is a cryptographic co-processor tailored to efficiently compute the SHA-256 hash function. Compliant with FIPS PUB 180-4 and supporting additional modes like SHA-224, it provides robust security solutions compatible with advanced secure communications standards. Its integration capabilities with APB, AHB, and AXI bus systems ensure widespread applicability across various hardware configurations. The processor's optimized design accentuates performance in data integrity and verification tasks, making it indispensable for high-security applications such as digital signature protocol implementations.
The Securyzr Key Management System offers a comprehensive environment for managing authentication keys, ensuring their secure distribution and maintenance. This system is engineered to protect data integrity and privacy in widespread IoT networks. By incorporating features like secure key bootstrapping and updates, the system ensures robust protection against unauthorized access and misuse of secure keys, making it ideal for deployments that demand high levels of trust and secrecy.
The SHA-3 Crypto Engine is a sophisticated hardware accelerator designed for cryptographic hashing functions. It stands out as an area-efficient and high-throughput design, fully compliant with the NIST FIPS 202 standard. This IP core supports all SHA-3 hash functions including SHA-3-224, SHA-3-256, SHA-3-384, and SHA-3-512, in addition to extendable output functions (XOF) such as SHAKE-128 and SHAKE-256. Its design includes robust protection against time-based side channel attacks (SCA) and features automatic byte padding. Operating within a single clock domain, the SHA-3 Crypto Engine has been meticulously verified to ensure reliability. It serves as a versatile solution for maintaining data integrity, enabling authentication, and supporting various security protocols. Its applications are extensive, finding use in Message Authentication Codes (MAC), IPsec and TLS/SSL protocol engines, secure boot mechanisms, encrypted storage, e-commerce, financial systems, blockchain, and pseudo-random bit generation. Deliverables with the SHA-3 Crypto Engine include System Verilog RTL source code, testbenches, integration examples, and software example source code, accompanied by comprehensive documentation. It is available under a one-time licensing fee, suitable for both single and multi-project licenses. The IP core offers impressive resource utilization and performance across several device families, ensuring efficient integration in diverse system environments.
The Xinglian-700 Interconnect Fabric extends the capabilities of its predecessor by offering high scalability and exceptional performance tailored for extensive multicore systems. Supporting up to 256 CPU cores, this fabric IP is pivotal in building high-density computational infrastructures capable of handling intensive data processing tasks across various domains such as AI, analytics, and enterprise computing. Engineered to facilitate rapid connectivity and improved throughput, the Xinglian-700 enhances system efficiency by ensuring consistent data flow between CPU clusters, I/O, and DDR components. This interconnect fabric employs a sophisticated network-on-chip (NoC) approach that prioritizes memory coherence and system reliability, even under heavy load conditions. The fabric's design allows it to support a wide array of technological applications, from large-scale data centers to AI-driven analysis, making it a versatile tool for enterprises aiming to scale their processing capabilities. By optimizing data paths and reducing latency, the Xinglian-700 sets a benchmark for interconnect systems, bolstering the efficiency of complex computational environments.
Helion's AES-GCM core provides a high-performance implementation of the AES in Galois Counter Mode (GCM), which is renowned for offering both encryption and authentication functionalities. This mode is specifically engineered to achieve high throughput rates while maintaining robust security, suitable for applications such as secure networking and high-speed data transfers. The GCM mode allows pipelining and parallelism, making it ideal for environments where latency and throughput are critical. Helion's AES-GCM implementations support a wide range of processing requirements, with throughput options from less than 50Mbps up to over 40Gbps, thus accommodating both lightweight applications and those demanding extensive data handling capabilities. Available for various technologies like ASICs and FPGAs, including platforms from Xilinx and Altera, Helion's AES-GCM cores are designed to deliver fast, efficient encryption and authentication. Its adaptability and performance efficiency make the Helion AES-GCM solution a strong candidate for any system requiring secure data encryption combined with swift response times.
This accelerator is pivotal in enhancing the performance of cryptographic protocols, significantly offloading the computational demand from primary processors. Designed with advanced threat models in mind, it supports a wide range of security operations, ensuring fast and secure data handling. The accelerator is built to accommodate both current standards and potential future adaptations, particularly in environments susceptible to high-risk operations. Its integration into existing systems offers a seamless upgrade path, providing robust solutions against evolving cryptographic threats.
DCRP1A, branded as CryptOne, represents a leading-edge cryptographic solution derived from two decades of expertise at Digital Core Design. This IP core is engineered to deliver unparalleled security by providing a 100% secure cryptographic environment, specifically designed to be resilient against the computational challenges posed by quantum computing advancements. It boasts a minimal silicon footprint while offering superior processing speeds, making it ideal for applications requiring robust security mechanisms.
Side-channel Attack Resistance from FortifyIQ offers a comprehensive solution to side-channel threats through both hardware and software components. Primarily, it focuses on SCA-protected implementations, leveraging novel algorithmic techniques to shield sensitive data without degrading system performance. This technology is pivotal in applications where information security is paramount, such as in financial systems, automotive systems, and secure communications, providing rigorous validation processes compliant with industry standards. The Side-channel solution offers adaptability across various hardware platforms, enhancing security while maintaining compatibility with legacy systems.
The Keccak Hash Engine IP core is a versatile cryptographic function component known for its adaptability beyond just hashing. Based on the innovative sponge construction, Keccak powers not only hash functions but also serves roles in authentication, encryption, and pseudo-random number generation. Among its notable features is the Keccak-f cryptographic permutation, which offers an easy-to-implement flexible solution that caters to varying security requirements. Standardized under 3GPP TS 35.231 for mobile telephony and NIST’s FIPS 202 and SP 800-185, Keccak assures dependability by undergoing rigorous public scrutiny and third-party analysis. It provides an easy integration path, operating within a single clock domain, and it can be configured to suit different output lengths and security strengths. This flexibility ensures its applicability in a broad spectrum of applications, from maintaining hash functions to complex encryption tasks. When licensing the Keccak Hash Engine, KiviCore provides System Verilog RTL source code, along with testbenches, software examples, and documentation. Licensing is available with single and multi-project options, ensuring accessibility and implementation for various project scopes. Its efficient design and robust security make it a critical component for those developing secure systems across numerous platforms.
Designed to enhance cryptographic operations, Synopsys' Security Protocol Accelerators deliver high-performance security functions for various SoC applications. This IP supports a range of algorithms and standards, ensuring secure data transactions and communications across platforms. These accelerators are built to handle intensive cryptographic processing, offering speed and efficiency for secure operations in data transfer, encryption, and integrity validation. With the growing demand for security in connected devices and networks, Synopsys' security accelerators are poised to provide robust protection against emerging threats. Implementing Synopsys' Security Protocol Accelerators means integrating a flexible solution that can be tailored to specific security requirements, supporting applications in automotive systems, payment technologies, and secure communications infrastructure. The design ensures easy integration and interoperability with other IPs, facilitating rapid deployment in a range of secure applications.
The ECDSA Sign core from Digital Core Design offers a cutting-edge solution for digital signatures using elliptic curve cryptography (ECC). Known for its optimal size-to-performance ratio, this core implements essential standards such as NIST and Brainpool, across a variety of elliptic curves. Offering a NAND gate range from 30k to 110k, it provides a high-efficiency option for implementing secure digital signatures in electronic communication and authentication systems.
ECDSA Verify by Digital Core Design ensures secure digital communication through elliptic curve signature verification. Supporting key elliptic curves, this core is engineered to achieve the best possible performance-to-size ratio, guaranteeing exceptional safety and reliability. It is instrumental in authentication processes where digital signatures are critical, providing robust verification that withstands contemporary security challenges.
PhantomBlu is Blu Wireless's tactical communication solution tailored for the demanding needs of military and defense sectors. Utilizing mmWave technology, it offers robust connectivity across land, sea, and air operations, facilitating critical mission-tasked applications with stealthy, high-speed connectivity. Designed to support tactical networks, PhantomBlu provides versatile and reliable communications through its anti-jam resistant mesh networks, ensuring data integrity and secure connectivity even in the most challenging environments.\n\nThe PhantomBlu system is designed with flexibility and adaptability at its core, making it suitable for various defense applications, from vehicle convoys to high-altitude platforms. Its mmWave network offers a 10x increase in data rates compared to conventional Wi-Fi or 5G technologies, without relying on fixed fiber networks. This adaptability extends to integration with existing defense systems, offering a seamless upgrade path while maintaining interoperability with future technologies.\n\nFeaturing smart functionality, PhantomBlu supports long-range communications up to 4km, with real-time processing capabilities integrated into its design. Its strong emphasis on security features is highlighted by the low probability of interception and detection, making it an ideal solution for secure military communications. Furthermore, its innovative network management tools ensure optimal network performance and reliability by seamlessly managing network linkages both on the ground and airborne.
The CCSDS LDPC IP Core implements LDPC (Low-Density Parity-Check) codes as per the Consultative Committee for Space Data Systems (CCSDS) standards, specifically catering to the complex needs of space communication systems. This IP core optimizes data transmission over long distances by providing reliable error correction and enhancing the signal integrity. With its attributes tailored for space applications, the CCSDS LDPC IP Core is highly effective in environments where bandwidth and processing power are limited, yet high reliability is mandatory. It employs efficient coding strategies to minimize data loss and improve the clarity of received signals, a critical factor for satellite and interstellar communications. The core design supports a wide range of platform deployments, offering scalable performance for diverse space missions. Its implementation can adapt to both low-latency links and high-throughput requirements, ensuring communication consistency and institutional reliability across varying signal conditions.
The Fault Resistant AES Core provides a fortified solution for secure data encryption with enhanced fault tolerance. This core is specifically engineered to maintain functionality in environments prone to transient faults or soft errors. Its design incorporates fault detection and correction mechanisms that ensure continuous and reliable data encryption, even in the presence of hardware disruptions. The core is ideal for critical applications that demand high reliability, such as aerospace and automotive systems, ensuring that unauthorized data breaches are prevented while maintaining system integrity. Additionally, this core offers customizable security parameters, allowing developers to tailor the encryption strength and fault resistance to their specific needs.
The CANsec Controller Core serves as a cybersecurity enhancement for controller area networks used in various applications. This core provides essential cryptographic functions for protecting messages transmitted via the CAN bus, mitigating risks associated with unauthorized data access and manipulation. Its architecture allows for seamless integration with existing CAN infrastructures, providing an upgrade path for enhancing security without overhauling legacy systems. This feature-rich core is tailored for industries where data integrity and confidentiality are paramount, ensuring robust protection of sensitive communications. Optimized for performance, the CANsec Controller Core balances high security with low latency, enhancing the reliability of secure message transmission across networked devices.
The Customizable Cryptography Accelerator is designed to provide tailored cryptographic solutions, aligning precisely with client requirements. It supports full compliance with NIST's PQC standards, integrating algorithms like Dilithium, Kyber, XMSS, and Sphinx+ and allowing for the extension of customer-specific algorithms. The accelerator emphasizes performance variability, which is tunable according to size necessities, and upholds strong resistance against Differential Power Analysis (DPA), timing, and Side-Channel Attacks (SCA). This highly flexible accelerator platform offers advanced functionalities suitable for various applications, including secure communications and data protection, needing adaptable cryptographic capabilities. Currently, it incorporates essential PQC standards and allows integration with customizable algorithms, facilitating unmatched versatility and bespoke security approaches. Its readiness for AXI 4 protocols makes it structurally adaptable to evolving technological landscapes. Notably, the accelerator continues to be a robust choice for organizations aiming to maintain a step ahead of potential security challenges posed by emergent quantum computing threats. Its adaptability and strength in cryptographic performance elevate it as a cornerstone for enterprises pursuing advanced security infrastructures.
The Individual IP Core Modules package offers a comprehensive range of post-quantum cryptographic standards in a modular fashion, allowing users to incorporate what specifically aligns with their project requirements. These modules integrate core algorithms such as Dilithium, Kyber, XMSS/SPHINCS+, AES variations (ECB, CBC, GCM), and the SHA2 and SHA3 families, ensuring users have robust tools for secure application development. By incorporating these rigorously tested modules, the risk of security breaches due to outdated encryption practices within your systems is significantly reduced. The robust cryptographic capabilities ensure high resilience to potential quantum computing threats, empowering organizations to maintain security integrity across data-intensive operations. These modules are deliberately crafted to extend further to potentially accommodate more algorithms informed by future tech evolution, enabling users to maintain sophisticated security postures easily. As anticipated threats advance, IP Core Modules remain essential for those participating in protective updates, consistently enhancing system security without extensive downtime.
This IP core provides an advanced implementation of LDPC (Low-Density Parity-Check) coding for IEEE 802.11 WLAN WiFi systems. Designed to support high-throughput and efficient error correction, this core is crucial for maintaining the speed and stability of wireless local area networks (WLANs). The core enhances the performance of WiFi connectivity by reducing packet errors and improving data transfer rates, thereby ensuring seamless user experiences in environments with high network demand. Using LDPC coding, it significantly advances the error correction efficiency, resulting in fewer retransmissions and lower latency. Ideal for deployment in consumer and enterprise networking products, this core is an excellent fit for routers, access points, and other critical networking infrastructure. It supports various 802.11 standards, ensuring compatibility with a range of networking protocols while maintaining robust performance levels.
This True Random Number Generator core offers a seamless solution for generating true random numbers in compliance with stringent NIST and Diehard Random Test requirements. With applications across ASICs and FPGAs, this core combines an internal entropy source with robust randomness tests to deliver outputs suitable for high-security applications. The TRNG1 core excels in scenarios demanding genuine randomness for encryptionkeys, secure communications, and more. Its compact and efficient design ensure minimal power usage while maintaining high throughput, making it indispensable for environments that require unfailing security assured by true random data.