All IPs > Wireless Communication
The Wireless Communication category at Silicon Hub encompasses a diverse array of semiconductor IPs designed to facilitate seamless wireless connectivity in today's rapidly evolving technological landscape. As the demand for higher data rates and uninterrupted connectivity grows, these IPs play a vital role in enabling devices to communicate efficiently across various protocols and standards. This category includes highly specialized IPs that support the implementation and enhancement of wireless communication technologies in a variety of applications ranging from consumer electronics to industrial systems.
Within this category, semiconductor IPs cover a wide spectrum of wireless standards and protocols. This includes evolving mobile communication standards like 3GPP-5G and LTE, which are essential for cellular networks' operation and are pivotal in the deployment of the latest 5G networks. For localized wireless communication, standards such as 802.11 (commonly referred to as Wi-Fi), Bluetooth, NFC, and Wireless USB are covered, facilitating device interconnectivity and data exchange in numerous consumer electronics, IoT devices, and more. Industrial and professional applications may utilize IPs related to standards like WiMAX (802.16), CPRI, OBSAI, which are crucial for network infrastructure and robust communication systems.
In addition to these, the Wireless Communication category includes IPs for satellite navigation systems like GPS, ensuring accurate geolocation services essential for navigation devices in both personal and commercial use. Standards like UWB (Ultra-Wideband) offer high-speed data transmission over short ranges, beneficial for applications demanding rapid short-range communication. Furthermore, for high-definition broadcasting, IPs supporting Digital Video Broadcast standards offer necessary capabilities to meet market demands for clear and reliable video content transmission.
This extensive category of semiconductor IPs under Wireless Communication not only provides the architectural needs for state-of-the-art communication devices but also accommodates future technological advancements. By integrating these IPs, semiconductor product designers and engineers can efficiently develop solutions tailored for enhanced connectivity, ensuring their products remain at the forefront of technological innovation and meet the ever-growing expectations of modern consumers for instant and reliable wireless communication. Whether you are developing next-gen smartphones, IoT solutions, or advanced networking systems, these IPs are critical components in achieving superior performance and connectivity.
The 2nd Generation Akida builds upon BrainChip's neuromorphic legacy, broadening the range of supported complex network models with enhancements in weight and activation precision up to 8 bits. This generation introduces additional energy efficiency, performance optimizations, and greater accuracy, catering to a broader set of intelligent applications. Notably, it supports advanced features like Temporal Event-Based Neural Networks (TENNs), Vision Transformers, and extensive use of skip connections, which elevate its capabilities within spatio-temporal and vision-based applications. Designed for a variety of industrial, automotive, healthcare, and smart city applications, the 2nd Generation Akida boasts on-chip learning which maintains data privacy by eliminating the need to send sensitive information to the cloud. This reduces latency and secures data, crucial for future autonomous and IoT applications. With its multipass processing capabilities, Akida addresses the challenge of limited hardware resources smartly, processing complex models efficiently on the edge. Offering a flexible and scalable IP platform, it is poised to enhance end-user experiences across various industries by enabling efficient real-time AI processing on compact devices. The introduction of long-range skip connections further supports intricate neural networks like ResNet and DenseNet, showcasing Akida's potential to drive deeper model efficiencies without excessive host CPU calculation dependence.
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
The ADQ35 offers a dual-channel, 12-bit configuration with a sampling rate of up to 10 GSPS. This digitizer is designed for high-performance applications, featuring up to 2.5 GHz input bandwidth and a programmable DC-offset. With 8 Gbyte onboard memory and an open FPGA, it allows custom real-time digital signal processing. It supports peer-to-peer streaming at rates up to 14 Gbyte/s, making it ideal for scientific and industrial applications.
The ORC3990 SoC is a state-of-the-art solution designed for satellite IoT applications within Totum's DMSS™ network. This low-power sensor-to-satellite system integrates an RF transceiver, ARM CPUs, memories, and PA to offer seamless IoT connectivity via LEO satellite networks. It boasts an optimized link budget for effective indoor signal coverage, eliminating the need for additional GNSS components. This compact SoC supports industrial temperature ranges and is engineered for a 10+ year battery life using advanced power management.
The HOTLink II Product Suite is a powerful video transmission solution that enables secure and rapid data exchange for avionics applications. This suite by Great River Technology is designed to facilitate seamless high-speed digital communications, minimizing latency while enhancing the system's reliability in demanding environments. The suite encompasses a range of tools that streamline the development and deployment of HOTLink II systems, which are crucial for managing high-bandwidth data flows. It offers extensive support mechanisms through well-crafted documentation and robust simulation tools, aiding engineers in achieving optimized system performance and regulatory compliance. By leveraging the HOTLink II Product Suite, users can achieve improved data integrity and support for multiple video interfaces, ensuring the readiness of systems for various missions. This makes the suite a vital component for both military and civilian aerospace projects, offering extensive scalability and customization to suit specific operational needs.
The Polar ID Biometric Security System is Metalenz's revolutionary solution for face authentication, delivering a new level of biometric security through advanced polarization imaging. Unlike conventional facial recognition systems, Polar ID captures the unique 'polarization signature' of each human face, offering enhanced security by effortlessly differentiating between real faces and potential spoofing attempts with sophisticated 3D masks. This innovative use of meta-optics not only enhances security but also reduces the need for complex optical modules traditionally required in consumer devices. Polar ID stands out in its ability to operate efficiently under varied lighting conditions, from bright sunlight to complete darkness. It achieves this with more than 10 times the resolution of current structured light systems, ensuring reliable and secure facial recognition performance even when users wear glasses or face coverings. By operating in the near-infrared spectrum, Polar ID extends its utility to scenarios previously challenging for facial recognition technology, thus broadening its application range. Designed for mass-market deployment, Polar ID minimizes the footprint and complexity of face unlock systems. By doing away with bulky modules, it offers a compact and cost-effective alternative while maintaining high-security standards. This innovation enables widespread adoption in consumer electronics, allowing a seamless integration into smartphones, tablets, and other mobile devices, potentially replacing less secure biometric methods like fingerprint recognition.
The TW330 Image Warping IP utilizes advanced GPU processing technology to offer high-performance image distortion correction. It features extensive capabilities including coordinate transformation, any-shape image transformations, and supports resolutions up to 16K x 16K for both RGB and YUV formats. Ideal for digitally correcting images distorted by wide-angle or fish-eye lenses on various devices, this technology is key in fields such as automotive display systems, VR/AR devices, and high-definition projectors. It makes real-time, on-the-fly image correction feasible, elevating the quality of visual outputs for demanding applications. Through its flexible and efficient design, TW330 enables seamless integration into systems requiring dynamic and precise image modification capabilities, paving the way for developing more interactive and immersive visual experiences.
The NaviSoC is a cutting-edge system-on-chip (SoC) that integrates a GNSS receiver and an application processor on one silicon die. Known for its high precision and reliability, it provides users with a compact and energy-efficient solution for various applications. Capable of supporting all GNSS bands and constellations, it offers fast time-to-first-fix, centimeter-level accuracy, and maintains high sensitivity even in challenging environments. The NaviSoC's flexible design allows it to be customized to meet specific user requirements, making it suitable for a wide range of applications, from location-based services to asset tracking and smart agriculture. The incorporation of a RISC-V application microcontroller, along with an array of peripherals and interfaces, introduces expanded functionality, optimizing it for advanced IoT and industrial applications. Engineered for power efficiency, the NaviSoC supports a range of supply voltages, ensuring low power consumption across its operations. The chip's design provides for efficient integration into existing systems with the support of a comprehensive SDK and IDE, allowing developers to tailor solutions to their precise needs in embedded systems and navigation infrastructures.
XDS serves as an all-encompassing platform for RF and microwave circuit design, unifying schematic and layout simulations across different scales. This software features extensive RF libraries and integrates linear circuit, spice, and MoM electromagnetic field solvers to handle diverse engineering needs. Its advanced technology supports automatic LC filter synthesis, optimizing the design of RF passive components. By managing third-party device libraries and facilitating efficient field-circuit simulations, XDS is a preferred choice for both preliminary and advanced stages of RF circuit development, ensuring high-precision and high-reliability results.
EnSilica's eSi-Comms brand houses a versatile communications IP portfolio, fundamental for supporting communications-driven ASIC designs. It includes highly parameterized OFDM-based MODEM and DFE IPs, applicable to a variety of modern air interface standards such as Wi-Fi, LTE, 5G, and DVB. This IP suite integrates advanced DSP algorithms and hardware accelerators for seamless wireless communication. By employing eSi-Comms, clients can utilize proven modem architectures to develop efficient transceivers tailored to specific communications requirements, drastically reducing development time. The adaptability of these IPs to handle data across multiple antennae systems enhances wireless sensor networks and broadcast products with robust connectivity solutions.
The CANmodule-IIIx module enhances the foundation of Inicore's CAN IP offerings, supporting a substantial 32 receive and 32 transmit buffers. This controller meets the stringent requirements of the international CAN standard ISO 11898-1 and is built to accommodate demanding applications like automotive and industrial controls, where expanded message handling and prioritization are critical. The module's design utilizes technology-neutral HDL, ensuring broad compatibility with both FPGA and ASIC implementations. It benefits from on-chip SRAM utilization, optimizing memory handling processes and enabling efficient system integration with ARM-based SoCs through its AMBA 3 APB interface. This comprehensive integration support facilitates seamless integration with minimal latency and high throughput. Debugging and testing are reinforced with advanced features, including various looping modes and an error capture register, which provides insights into communication errors and message states. The mailbox-oriented architecture and provision for message filtering in the first two data bytes make the CANmodule-IIIx particularly advantageous for applications requiring reliable, high-volume data exchanges.
Hermes Layered stands as a leading solution for electromagnetic field simulations, particularly for complex systems needing board-level, IC, and package simulations. Developed with a full-wave high-precision EM simulation engine, it supports extensive simulations of every conceivable 3D structure from nanometer to centimeter scales. Hermes Layered's distributed parallel computing capabilities allow users to leverage powerful computing resources for fast, detailed model simulations. This tool is indispensable for industries that require accurate and quick iterations of design, supporting a variety of simulations from signal integrity to full system integrity.
AccelerComm presents the Polar encoding and decoding suite for the 3GPP NR, featuring a comprehensive chain that enables quick integration and minimizes additional developmental efforts. This advanced IP utilizes PC and CRC-aided SCL decoding methods to deliver uncompromising error correction performance, adeptly handling the intricacies of 5G applications.\n\nThe Polar IP supports an extensive range of block sizes, tightly integrating each component to optimize performance while reducing latency and resource use. Its flexibility is further highlighted by its highly configurable parameters, which allow users to tailor its implementation to specific performance demands and power efficiency expectations.\n\nBy offering support for prevalent FPGA platforms like AMD and Intel, alongside ASIC optimizations, this Polar solution is a versatile option for developers seeking robust and integral solutions for burgeoning 5G networks. With ease of integration and superior performance metrics, it remains a leading solution in comprehensive 5G data processing.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
The EW6181 is a cutting-edge multi-GNSS silicon solution offering the lowest power consumption and high sensitivity for exemplary accuracy across a myriad of navigation applications. This GNSS chip is adept at processing signals from numerous satellite systems including GPS L1, Glonass, BeiDou, Galileo, and several augmentation systems like SBAS. The integrated chip comprises an RF frontend, a digital baseband processor, and an ARM microcontroller dedicated to operating the firmware, allowing for flexible integration across devices needing efficient power usage. Designed with a built-in DC-DC converter and LDOs, the EW6181 silicon streamlines its bill of materials, making it perfect for battery-powered devices, providing extended operational life without compromising on performance. By incorporating patent-protected algorithms, the EW6181 achieves a remarkably compact footprint while delivering superior performance characteristics. Especially suited for dynamic applications such as action cameras and wearables, its antenna diversity capabilities ensure exceptional connectivity and positioning fidelity. Moreover, by enabling cloud functionality, the EW6181 pushes boundaries in power efficiency and accuracy, catering to connected environments where greater precision is paramount.
Functioning as a comprehensive cross-correlator, the XCM_64X64 facilitates efficient and precise signal processing required in synthetic radar receivers and advanced spectrometers. Designed on IBM's 45nm SOI CMOS technology, it supports ultra-low power operation at about 1.5W for the entire array, with a sampling performance of 1GSps across a bandwidth of 10MHz to 500MHz. The ASIC is engineered to manage high-throughput data channels, a vital component for high-energy physics and space observation instruments.
The CANmodule-III is a comprehensive CAN controller module that offers mailbox-based architecture. It meets the international CAN standard ISO 11898-1 and includes 16 receive buffers, each equipped with its own message filter, and 8 transmit buffers with a priority-based arbitration scheme. This configuration ensures optimal support for Higher Layer Protocols (HLP) like DeviceNet and SDC, which demand intricate application-specific features. Built with technology-independent HDL, the CANmodule-III integrates seamlessly into both ASIC and FPGA frameworks, fully utilizing on-chip SRAM structures for enhanced performance. An AMBA 3 Advanced Peripheral Bus (APB) interface simplifies the integration into ARM-based systems-on-chip (SoCs), guaranteeing zero wait-state interface performance. This module supports advanced features such as automatic remote transmission request (RTR) handling and configurable interrupt generation mechanisms. The design is fully synchronous and includes robust test and debugging capabilities—such as various loopback modes and an SRAM test mode—ensuring high reliability and ease of development. This versatile CAN controller offers a sophisticated solution for implementing reliable, high-performance CAN communications in diverse embedded systems.
The GNSS VHDL Library from GNSS Sensor Ltd is designed to streamline satellite navigation system integration into FPGA platforms. This versatile library includes numerous modules such as configurable GNSS engines and fast search engines catering to GPS, GLONASS, and Galileo systems. Complementing these are special components like a Viterbi decoder and RF front-end control, ensuring comprehensive system integration support. Engineered to achieve maximum independence from CPU platforms, the GNSS VHDL Library is built upon a simple configuration file to deliver flexibility and ease of use. Users benefit from pre-built FPGA images compatible with both 32-bit SPARC-V8 and 64-bit RISC-V architectures. The library enables GNSS operations as a co-processor with SPI interface, supporting diverse external bus interfaces without requiring changes in the core library structure. The GNSS VHDL Library incorporates Simplified Core Bus (SCB) for interfacing, enabling interactions through a system-defined bridge module. This provides flexibility in design and ensures efficient data processing and integration with existing systems, simplifying the development process for both new and existing FPGA platforms. Whether enhancing current designs or developing new navigation solutions, this library equips developers with the tools needed for effective GPS, GLONASS, and Galileo integration.
The Hyperspectral Imaging System from Imec offers unparalleled capabilities in capturing spectral data, enabling detailed analysis and identification of materials based on their spectral signatures. This system is designed to provide high-resolution imaging across a range of wavelengths, making it an invaluable tool for industries such as agriculture, mining, and environmental monitoring. By integrating cutting-edge sensor technology, the system facilitates advanced analytics that support decision-making in various applications requiring precise material composition detection. This advanced imaging solution leverages Imec’s proprietary sensor innovations, which inherently allow for real-time data acquisition and processing. The compact nature of the system makes it adaptable for field deployments, allowing users to conduct in-situ analyses efficiently. Moreover, its robust design ensures consistent performance in diverse environmental conditions, thus broadening its application scope. Core to the Hyperspectral Imaging System is Imec’s commitment to enhancing the functionality of their semiconductor technology. With its ability to seamlessly integrate into existing infrastructures, it offers users a cost-effective upgrade path for significantly improving the precision of their diagnostic capabilities. As industries look for integrated solutions, this imaging system stands out by offering a high degree of customization to meet specific operational needs.
ASPER is a 79 GHz short-range radar sensor designed to exceed the capabilities of traditional ultrasonic parking assist technologies. With a 180-degree field of view, ASPER provides unparalleled coverage with a single module. This ensures that vehicles ranging from passenger cars to AGVs benefit from complete side coverage without blind spots. The sensor's ability to detect low-lying objects like curbs enhances safety and situational awareness for drivers across a variety of contexts. ASPER integrates seamlessly into vehicle systems, allowing for effective monitoring of front, rear, and side zones for enhanced collision avoidance and traffic awareness. Its robust design optimizes it for urban blind spot detection, providing critical alerts to drivers regarding potential hazards. This technology is crucial for improving both safety and driver confidence in busy urban environments. Designed for scalability, the ASPER radar sensor can be employed in a variety of vehicles, including motorcycles and larger transportation vehicles. Its adaptability ensures comprehensive monitoring, contributing to more effective navigation and obstacle avoidance in all weather conditions. With edge-processing technology, ASPER boasts a host of features that maximize performance while maintaining affordability.
802.11 LDPC offers a highly efficient solution for wireless communication systems, ensuring high throughput and dynamic configuration. The design allows frame-to-frame configuration, optimizing the trade-off between throughput and error correction performance. Meeting stringent bit-error-rate and packet-error-rate specifications, this technology is ideal for robust communication systems requiring reliable data transmission.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The DVB-S2-LDPC-BCH system provides a formidable forward error correction platform crucial for satellite communication. Utilizing LDPC coupled with BCH codes, this IP ensures quasi-error-free operation, pushing system performance near the Shannon limit. Compliant with ETSI standards, it offers robust error correction capabilities with varied throughput rates, facilitated by its synthesizable Verilog model, making it adaptable for ASIC implementations.
The PCD03D Turbo Decoder is adept at handling multiple state decoding for standards such as DVB-RCS and IEEE 802.16 WiMAX. Its core design features an 8-state duobinary decoding structure, facilitating precise and quick signal deconstruction. Additionally, the optional inclusion of a 64-state Viterbi decoder enhances versatility and performance in various environments. This decoder is tailored for applications where agility and high data throughput are critical, making it an invaluable asset in wireless communication infrastructures. The decoder’s architecture supports expansive VHDL core integration, providing durable solutions across FPGA platforms.
The ADQ35-WB stands out as a versatile and high-performance data acquisition module, featuring either a dual-channel setting at 5 GSPS or a single-channel mode at 10 GSPS. It boasts a substantial 9 GHz usable analog input bandwidth, rendering it suitable for high-frequency applications. Integrated with an open FPGA, the device enables custom real-time digital signal processing, supports peer-to-peer streaming up to 14 Gbyte/s, and is equipped with hardware triggers for a variety of advanced applications.
In the realm of smartphones, ActLight introduces its Dynamic PhotoDetector (DPD) technology, which significantly optimizes various aspects of phone functionality. The integration of DPD in smartphone applications, such as proximity sensing, ambient light detection, and 3D sensing, paves the way for enhanced user interactions and efficient operation. This sensor technology uses advanced 3D Time-of-Flight (ToF) camera technology to ensure precise detection and measurement of light intensity for a variety of uses. By delivering high sensitivity to even the smallest changes in light, ActLight's DPD transforms how smartphones manage power efficiency, allowing for better battery conservation. Its low-voltage operation reduces overall power consumption, a crucial factor in mobile devices that need to maintain long battery life for uninterrupted use. Moreover, the DPD technology enables new functionalities such as enhanced eye-tracking for augmented and virtual reality, providing insights into user behavior and improving the immersive experience. In addition to gaming and media, these advancements support the evolving needs of data-driven applications and interactive consumer technologies.
The LDPC solution by AccelerComm is meticulously optimized for the 5G NR standard, ensuring superior efficiency and performance. This encoder and decoder IP triumphantly addresses the pivotal needs of the 5G network by combining maximal hardware efficiency with enhanced power efficiency. It is adeptly designed to fulfill the rigorous throughput and error correction targets outlined by 3GPP standards.\n\nIntended for integration into both FPGA and ASIC environments, the LDPC IP is highly configurable, providing numerous settings to cater to a broad array of applications. Its capability to support maximum data rates while minimizing latency makes it an indispensable element in advanced communication infrastructures.\n\nWith enhanced BLER performance and an innovative design that outstrips generic LDPC solutions, this implementation significantly reduces latency and resource utilization. Offering low power consumption and half the energy per bit compared to competitors, it provides a balanced approach to meeting both diverse operational demands and stringent power budgets.
The mmWave PLL is a sophisticated Phase Locked Loop designed for ultra-precision wireless communications and radar applications. This fractional-N PLL synthesizer provides low phase noise performance suitable for demanding carrier and fast chirp FMCW waveforms, critical in modern communication networks. Its operational range corresponds to fundamental frequencies of 19.00-20.15 GHz, scalable to radar bands of 38-40.5 GHz and 76-81 GHz through frequency multipliers, highlighting its versatility across applications. The mmWave PLL supports a customizable frequency range from 19 GHz to 81 GHz, ensuring tailored application requirements can be achieved. Integrated design features include a built-in sequencer, calibration, and self-test capabilities, all of which contribute to the PLL's robustness. The unit is compliant with automotive standards like AEC-Q100 Grade 1, making it suitable for rigorous environments, such as automotive radar systems. Technical specifications reveal its operational proficiency with power consumption at under 120 mA and operating temperatures from -40 to +125 °C (ambient) and -40 to +150 °C (junction). This is supported by SPI control interfaces for precise manageability, ensuring integration efforts align seamlessly within varied system architectures.
The RWM6050 baseband modem from Blu Wireless underpins their mmWave solutions, providing a powerful platform for high-bandwidth, multi-gigabit connectivity. Co-developed with Renesas, this modem pairs seamlessly with mmWave RF chipsets to offer a configurable radio interface, capable of scaling data across sectors requiring both access and backhaul services. This modem features flexible channelization and modulation coding schemes, enabling it to handle diverse data transmission needs with remarkable efficacy. Integrated dual modems and a mixed-signal front-end allow for robust performance in varying deployment scenarios. The RWM6050 supports multiple frequency bands, and its modulation capabilities enable it to adapt dynamically to optimize throughput under different operational conditions. The modem includes advanced beamforming support and digital front-end processing, which facilitates enhanced data routing and network synchronization. These features are pivotal for managing shifting network loads and ensuring resilient performance amidst irregular traffic and environmental variances. A real-time scheduler further augments its capabilities, enabling dynamic response to complex connectivity challenges faced in modern communication landscapes.
AccelerComm's High PHY Accelerators offer an impressive portfolio of IP accelerators tailored for 5G NR, enhancing O-RAN deployments with advanced signal processing capabilities. These accelerators emphasize maximum throughput and minimal power and latency, leveraging scalable technology for ASIC, FPGA, and SoC applications.\n\nCentral to these accelerators are patented high-performance signal processing algorithms, which enhance throughput significantly, making them crucial in scenarios demanding rapid data processing and low latency. The offering is ideal for improving the speed and efficiency of high-demand networks, reinforced by extensive research led by industry experts from Southampton University.\n\nMoreover, the accelerators encompass a wide variety of signal processing techniques such as LDPC and advanced equalization, to optimize the entire data transmission process. The result is a remarkable boost in spectral efficiency and overall network performance, making these accelerators indispensable for cutting-edge wireless technologies and their future-forward deployments.
IRIS is a robust solution for RF and analog IC electromagnetic simulations, crucial for addressing parasitic effects at high frequencies. Integrated with Cadence Virtuoso, IRIS ensures designers can execute precise electromagnetic field simulations within their design environment. It employs advanced 3D planar EM solvers based on the method of moments (MoM) to accurately model materials' skin and proximity effects. Additionally, IRIS facilitates design cycle reduction through parallel processing capabilities and unparalleled integration of front-end and back-end design environments, optimizing both synthesis and verification processes for RF circuits.
NeuroVoice is a powerful ultra-low-power neuromorphic front-end chip engineered for voice processing in environments plagued by irregular noises and privacy concerns. This chip, built on the NASP framework, improves real-time voice recognition, reducing reliance on cloud processing and providing heightened privacy. It is ideal for applications in hearables, smart home devices, and other AI-driven voice control systems, capable of efficiently processing human voice amidst noise. The NeuroVoice chip addresses key challenges faced by existing digital solutions, such as excessive power consumption and low latency in real-time scenarios. Its brain-inspired architecture processes voice commands independently of the cloud, which minimizes Internet dependency and enhances privacy. Furthermore, the chip's ability to manage voice detection and extraction makes it suitable for diverse environments ranging from urban noise to quiet domestic settings. Advanced features of the NeuroVoice chip include its ultra-fast inference capability, processing all data locally and ensuring user privacy without compromising performance. By supporting applications like smart earbuds and IoT devices, NeuroVoice optimizes energy efficiency while maintaining superior voice processing quality. This innovative technology not only empowers users with clearer communication abilities but also encourages adoption across multiple consumer electronics.
The 802.11ah HaLow Transceiver is a high-performance connectivity solution from Palma Ceia SemiDesign, tailored for the latest IoT and mobile applications. The device is designed to meet the IEEE 802.11ah standard, offering optimized bandwidth and power management, which are critical for advanced IoT implementations. This transceiver excels with its low power consumption, making it ideal for battery-powered devices. It includes a low noise, direct conversion receiver with integrated DC offset correction and I/Q calibration schemes. These features ensure minimal latency in signal processing and allow the transceiver to process signals effectively over a wide dynamic range. Additionally, the transceiver supports multiple interfaces including SPI, JTAG, and UART, simplifying its integration into broad IoT systems. Its robust design allows it to function either as an independent unit or as part of a system-on-chip (SoC), providing flexibility in usage across various applications like asset tracking, building security, and industrial automation.
The ntLDPC_DVBS2X IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2X decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the DVB-S2 and DVB-S2X standards. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2X encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. Actual encoding is performed as a three part recursive computation process, where row sums, checksums of all produced rows column-wise and finally transposed parity bit sums are calculated. The ntLDPC_DVBS2X decoder IP implements a 360-bit parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. The decoder IP permutes each block’s parity LLRs to become compatible with the layered decoding scheme and stores channel LLRs to processes them in layered format. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity submatrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit.
The XCM_64X64_A is a powerful array designed for cross-correlation operations, integrating 128 ADCs each capable of 1GSps. Targeted at high-precision synthetic radar and radiometer systems, this ASIC delivers ultra-low power consumption around 0.5W, ensuring efficient performance over a wide bandwidth range from 10MHz to 500MHz. Built on IBM's 45nm SOI CMOS technology, it forms a critical component in systems requiring rapid data sampling and intricate signal processing, all executed with high accuracy, making it ideal for airborne and space-based applications.
With its superior resolution and high sampling rate, the ADQ7DC digitizer is designed to improve application performance tremendously. It offers 14 bits of vertical resolution and can operate in a dual-channel mode at 5 GSPS, or a single-channel arrangement at 10 GSPS, with a wide 3 GHz input bandwidth. The digitizer supports a diverse range of applications including mass spectrometry and LiDAR, thanks to its versatile modular setup and peer-to-peer streaming capabilities to GPUs and CPUs.
ArrayNav represents a significant leap forward in navigation technology through the implementation of multiple antennas which greatly enhances GNSS performance. With its capability to recognize and eliminate multipath signals or those intended for jamming or spoofing, ArrayNav ensures a high degree of accuracy and reliability in diverse environments. Utilizing four antennas along with specialized firmware, ArrayNav can place null signals in the direction of unwanted interference, thus preserving the integrity of GNSS operations. This setup not only delivers a commendable 6-18dB gain in sensitivity but also ensures sub-meter accuracy and faster acquisition times when acquiring satellite data. ArrayNav is ideal for urban canyons and complex terrains where signal integrity is often compromised by reflections and multipath. As a patented solution from EtherWhere, it efficiently remedies poor GNSS performance issues associated with interference, making it an invaluable asset in high-reliability navigation systems. Moreover, the system provides substantial improvements in sensitivity, allowing for robust navigation not just in clear open skies but also in challenging urban landscapes. Through this additive capability, ArrayNav promotes enhanced vehicular ADAS applications, boosting overall system performance and achieving higher safety standards.
The Digital PreDistortion (DPD) Solution by Systems4Silicon is a cutting-edge technology developed to maximize the power efficiency of RF power amplifiers. Known as FlexDPD, this solution is vendor-independent, allowing it to be compiled across various FPGA or ASIC platforms. It's designed to be scalable, optimizing resources according to bandwidth, performance, and multiple antennae requirements. One of the key benefits of FlexDPD is its substantial efficiency improvements, reaching over 50% when used with modern GaN devices in Doherty configurations, surpassing distortion improvements of 45 dB. FlexDPD is versatile, operating with communication standards including multi-carrier, multi-standard, and various generations from 2G to 5G. It supports both time division and frequency division duplexing, and can accommodate wide Tx bandwidths, limited only by equipment capabilities. The technology is also agnostic to amplifier topology and transistor technology, providing broad applicability across different setups, whether class A/B or Doherty, and different transistor types like LDMOS, GaAs, or GaN. This technology integrates seamlessly with Crest Factor Reduction (CFR) and envelope tracking techniques, ensuring a low footprint on resources while maximizing efficiency. With complementary integration and performance analysis tools, Systems4Silicon provides comprehensive support and documentation, ensuring that clients can maximize the benefits of their DPD solution.
The FCM3801-BD Power Amplifier enhances Falcomm's powerful offerings in the realm of high-performance digital power amplification. Functioning at an impressive 38 GHz center frequency, this device is engineered for ultra-efficient energy solutions in the field of advanced telecommunications. With a design that underscores energy efficiency and reliability, the FCM3801-BD is a key player for telecom operators aiming to optimize power resources. This amplifier's intelligent construction ensures unwavering performance even in challenging conditions, reflecting Falcomm's commitment to sustainability and operational excellence. Ideal for applications such as high-speed data transmission and enhanced signal processing, the FCM3801-BD promises to reduce power demands while delivering high output. This enables telecom providers to pursue eco-friendlier paths in their operations without compromising on service quality or connectivity capabilities.
Ubi.cloud is an innovative geolocation solution designed to minimize the typical limitations of GPS and Wi-Fi trackers in IoT applications. This software shifts energy-intensive processing from devices to the cloud, significantly reducing power consumption and hardware costs. The technology supports both outdoor GPS and indoor Wi-Fi geolocation, making it versatile for various environments. The solution features ultra-low power consumption, cutting the energy usage of receiver chipsets by up to tenfold compared to traditional devices. This is achieved by utilizing leading hardware components effectively, which accelerates time-to-market for IoT devices. Ubi.cloud is ideal for asset tracking, providing accurate geolocation services with enhanced efficiency. By leveraging the cloud, Ubi.cloud reduces the data payload to a mere 10 bytes per position, operating seamlessly with low-power wide-area networks such as Sigfox, LoRa, NB-IoT, and LTE-M. The flexible business model, offering pay-as-you-go or lifetime licenses, makes it accessible and adaptable to various commercial needs. Evaluation kits and SDKs are available, supporting easy integration and customization for specific applications.
ParkerVision's D2D® Technology revolutionizes RF communication by enabling direct conversion from RF signals to digital data, bypassing traditional intermediate frequency stages. This technology is instrumental in streamlining signal processing, enhancing speed and efficiency of data handling in various wireless communication devices. The D2D technology supports a broad spectrum of applications, including mobile phones, wireless internet, and IoT devices, delivering high performance and adaptability for current and forthcoming technological needs. D2D® shines in its ability to sustain high data rates necessary for modern applications like 4G and 5G networks, bolstering the capabilities of RF integrated circuits with its advanced conversion techniques. Furthermore, this technology is central to facilitating seamless integration across different communication standards, allowing devices to operate over multiple frequency bands without compromising on data quality or speed. The intellectual property surrounding D2D® is robustly protected with a comprehensive patent portfolio, ensuring its exclusivity and opening avenues for strategic partnerships and licensing. By harnessing this technology, devices gain enhanced power efficiency and broader operational capabilities while lowering manufacturing costs and conserving energy, making it a pivotal innovation for evolving communication landscapes.
LTE Lite is engineered for user equipment compliance with CAT 0/1 PHY standards, offering a flexible solution for varied channel bandwidths. This IP is designed to work seamlessly with standard RF tuners, providing automated demodulation and robust frequency offset compensation. Through parallel and serial output configurations, it ensures precision in timing and frequency corrections across its operational bandwidth.
In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used in the decoder to eliminate the channel noise. The error correction capability of a FEC system strongly depends on the amount of redundancy as well as on the coding algorithm itself. TPCs perform well in the moderate to high SNRs because the effect of error floor is less. As TPCs have more advantage when a high rate code is used, they are suitable for commercial applications in wireless and satellite communications. The ntTPC Turbo Product Codec IP core is consisted of the Turbo Product Encoder (ntTPCe) and the Turbo Product Decoder (ntTPCd) blocks. The product code C is derived from two/three constituent codes, namely C1, C2 and optionally C3. The information data is encoded in two/three dimensions. Every row of C is a code of C2 and every column of C is a code of C1. When the third coding dimension is enabled, then there are C3 C1*C2 data planes. The ntTPC core supports both e-Hamming and Single Parity Codes as the constituent codes. The core also supports shortening of rows or columns of the product table, as well as turbo shortening. Shortening is a way of providing more powerful codes by removing information bits from the code. The ntTPCe core receives the information bits row by row from left to right and transmits the encoded bits in the same order. It consists of a row, column and 3D encoder. The ntTPCd decoder receives soft information from the channel in the 2’s complement number system and the input samples are received row by row from left to right. The implemented decoding algorithm computes the extrinsic information for every dimension C1, C2, C3 by iteratively decoding words that are near the soft-input word. An advanced scalable and parametric design approach produces custom design versions tailored to end customer applications design tradeoffs.
The Software-Defined High PHY from AccelerComm is designed for adaptability and high efficiency across ARM processor architectures. This product brings flexibility in software-defined radio applications by facilitating easy optimization for different platforms, considering power and capacity requirements. It allows integration without hardware acceleration based on the needs of specific deployments.\n\nA key feature of the Software-Defined High PHY is its capability for customization. Users can tailor this IP to work optimally across various platforms, either independently or coupled with hardware-accelerated functionalities. This ensures the high-performance needed for modern network demands is met without unnecessary resource consumption.\n\nPerfect for scenarios needing O-RAN compliance, this PHY solution supports high adaptability and scalability for different use cases. It is ideal for developers who require robust communication solutions tuned for efficient execution in varying environmental conditions, contributing to lower latency and higher throughput in network infrastructures.
Our UHS-II solution is crafted to enhance data transfer speeds significantly, especially in environments where low voltage is required. This technology is essential for transmitting high-definition content, making it a crucial component in mobile devices. The modular design approach ensures a high degree of configurability, allowing seamless integration into existing infrastructures. This solution supports mobile environments by optimizing the data path for low power consumption, ensuring efficient and rapid communications. Beyond its basic functionality, the UHS-II solution brings an architectural flexibility that allows it to meet various data requirements in different applications. It can maintain robust data transmission rates under varying conditions, making it versatile for multiple scenarios. The solution is aimed at addressing the need for high-definition video and image transmission, supporting the demand for better visual content on mobile platforms. By adopting industry standards, the UHS-II solution offers compatibility with a wide range of devices and platforms. This compatibility ensures that it can deliver the required high-speed data service in low-voltage scenarios, crucial for modern mobile devices that need to handle large multimedia files. With support for modular integration, device manufacturers can utilize this solution to enhance their product offerings, delivering higher performance and satisfaction to end-users.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The PCS2100 is a sophisticated Wi-Fi HaLow modem chip specifically designed for use in IoT network client devices. It is part of the IEEE 802.11ah family, ensuring it aligns seamlessly with modern-day IoT standards. By operating in the sub-gigahertz frequency range, it extends communication ranges to cover up to 1 km, thus ensuring efficient connectivity in sprawling IoT deployments. This modem supports operations suited to IoT devices that use narrowband transmission to achieve extensive battery life. It includes various IoT network management extensions such as Target Wake Time (TWT) and Resource Allocation Windowing (RAW), crucial in managing device efficiency and battery usage. Notably, its receiver's sensitivity allows it to maintain reliable connections even at extensive ranges. Designed with security in mind, the PCS2100 employs advanced wireless encryption protocols such as WPA3, making it highly secure for IoT uses. Integration is straightforward, thanks to support for multiple interfaces like SPI and UART, along with comprehensive software support for calibration, production testing, and signal path compensation in IoT networks.
Wireless IP developed by Analog Circuit Works provides essential capabilities for portable, medical, and sensor application domains. These IP blocks are critical in enabling wireless power and data transmission, thereby supporting the autonomy and versatility of modern devices that rely heavily on wireless technologies. The solutions offered are designed with a focus on maximizing frequency capabilities while ensuring efficiency across various environmental scenarios. This adaptability ensures that these IPs meet the rigorous demands of applications where wireless communication and power provisioning are at the forefront of user expectations. Analog Circuit Works' wireless solutions are fine-tuned to provide enhanced robustness and reliability, facilitating seamless integration within devices that require stable and sustained wireless operations. As a result, they are perfectly suited for innovations in IoT and other rapidly evolving technology landscapes requiring high-quality wireless interface and communication solutions.
The Dual-Drive™ Power Amplifier FCM1401 stands out for its exceptional energy efficiency and advanced two-stage architecture. Operating at a center frequency of 14 GHz, it embodies industry-leading innovation in power amplifiers by offering a significant leap in power efficiency. This product is ideal for mobile connected devices and telecommunication applications that demand lower energy consumption without sacrificing performance. With its robust design, the FCM1401 ensures that operators can enhance operational efficiency while reducing the environmental footprint of power consumption. The design caters to high-frequency applications by maximizing performance and maintaining the reliability expected in modern telecom infrastructures. It therefore offers a practical solution for enhancing device longevity with reduced operational expenses. This amplifier is tailored to support both space communications and mobile technology applications, offering unparalleled power handling capabilities. Whether enriching the battery life or scaling up the signal strength, it aligns with green energy initiatives by providing significant output without increased energy use.
CLOP Technologies' 60GHz Wireless Solution offers businesses an impressive alternative to traditional networking systems. Leveraging the IEEE 802.11ad WiFi standard and Wireless Gigabit Alliance MAC/PHY specifications, this solution achieves a peak data rate of up to 4.6Gbps. This makes it particularly suited for applications that require significant bandwidth, such as real-time, uncompressed HD video streaming and high-speed data transfers — operations that are notably quicker compared to current WiFi systems. The solution is engineered to support 802.11ad IP networking, providing a platform for IP-based applications like peer-to-peer data transfer and serving as a router or access point. Its architecture includes a USB 3.0 host interface and mechanisms for RF impairment compensation, ensuring both ease of access for host compatibility and robust performance even under high data rate operations. Operating on a frequency band ranging from 57GHz to 66GHz, the wireless solution utilizes modulation modes such as BPSK, QPSK, and 16QAM. It incorporates forward error correction (FEC) with LDPC codes, providing various coding rates for enhanced data integrity. Furthermore, the system boasts AES-128 hardware security, with quality of service maintained through IEEE 802.11e standards.
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