All IPs > Wireless Communication
The Wireless Communication category at Silicon Hub encompasses a diverse array of semiconductor IPs designed to facilitate seamless wireless connectivity in today's rapidly evolving technological landscape. As the demand for higher data rates and uninterrupted connectivity grows, these IPs play a vital role in enabling devices to communicate efficiently across various protocols and standards. This category includes highly specialized IPs that support the implementation and enhancement of wireless communication technologies in a variety of applications ranging from consumer electronics to industrial systems.
Within this category, semiconductor IPs cover a wide spectrum of wireless standards and protocols. This includes evolving mobile communication standards like 3GPP-5G and LTE, which are essential for cellular networks' operation and are pivotal in the deployment of the latest 5G networks. For localized wireless communication, standards such as 802.11 (commonly referred to as Wi-Fi), Bluetooth, NFC, and Wireless USB are covered, facilitating device interconnectivity and data exchange in numerous consumer electronics, IoT devices, and more. Industrial and professional applications may utilize IPs related to standards like WiMAX (802.16), CPRI, OBSAI, which are crucial for network infrastructure and robust communication systems.
In addition to these, the Wireless Communication category includes IPs for satellite navigation systems like GPS, ensuring accurate geolocation services essential for navigation devices in both personal and commercial use. Standards like UWB (Ultra-Wideband) offer high-speed data transmission over short ranges, beneficial for applications demanding rapid short-range communication. Furthermore, for high-definition broadcasting, IPs supporting Digital Video Broadcast standards offer necessary capabilities to meet market demands for clear and reliable video content transmission.
This extensive category of semiconductor IPs under Wireless Communication not only provides the architectural needs for state-of-the-art communication devices but also accommodates future technological advancements. By integrating these IPs, semiconductor product designers and engineers can efficiently develop solutions tailored for enhanced connectivity, ensuring their products remain at the forefront of technological innovation and meet the ever-growing expectations of modern consumers for instant and reliable wireless communication. Whether you are developing next-gen smartphones, IoT solutions, or advanced networking systems, these IPs are critical components in achieving superior performance and connectivity.
The Akida Neural Processor is a sophisticated AI processing unit designed to handle complex neural network tasks with unmatched precision and efficiency. Utilizing an event-based processing model, Akida exploits data sparsity to minimize operations and hence decrease power usage significantly while enhancing throughput. This processor is built around a mesh network interconnect, with each node equipped with configurable Neural Network Engines that can handle convolutional and fully connected neural networks. With these capabilities, Akida can process data at the edge, maintaining high-speed, low-latency responses ideal for real-time applications. Akida maintains seamless functionality in diverse use cases, from predictive maintenance to streaming analytics in sensors. By supporting on-chip learning and providing strong privacy controls, this processor ensures data security by reducing cloud data exchanges, making it a trusted component for sensitive applications.
The 2nd Generation Akida processor introduces groundbreaking enhancements to BrainChip's neuromorphic processing platform, particularly ideal for intricate network models. It integrates eight-bit weight and activation support, improving energy efficiency and computational performance without enlarging model size. By supporting an extensive application set, Akida 2nd Generation addresses diverse Edge AI needs untethered from cloud dependencies. Notably, Akida 2nd Generation incorporates Temporal Event-Based Neural Nets (TENNs) and Vision Transformers, facilitating robust tracking through high-speed vision and audio processing. Its built-in support for on-chip learning further optimizes AI efficiency by reducing reliance on cloud training. This versatile processor fits perfectly for spatio-temporal applications across industrial, automotive, and healthcare sectors. Developers gain from its Configurable IP Platform, which allows seamless scalability across multiple use cases. The Akida ecosystem, including MetaTF, offers developers a strong foundation for integrating cutting-edge AI capabilities into Edge systems, ensuring secure and private data processing.
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
CoreVCO is a sophisticated voltage-controlled oscillator specifically designed to endure harsh environments and applications like space and military operations. This VCO comprises two distinct, radiation-hardened wideband SiGe designs, optimized for ultra-low phase noise over an extensive frequency range. This design enhances reliability and functionality in environments with high radiation levels, making CoreVCO a leading choice for high-performance applications.\nThe VCO operates efficiently in frequencies ranging from 0.7 GHz to 6.6 GHz, offering different configurations for optimal phase noise across varied uses. The integration of bandgap references and LDOs supports operational flexibility, with a single power supply voltage of 5.0V facilitating uniform performance across applications.\nEnd users will benefit from its digital calibration capabilities, which provide stability against temperature and process variations, and its small form factor, packaged in a 6mm x 6mm footprint. CoreVCO suits a spectrum of applications from satellite communications to advanced military systems, demonstrating CoreHW's commitment to high-quality, durable design.
The ORC3990 SoC is a state-of-the-art solution designed for satellite IoT applications within Totum's DMSS™ network. This low-power sensor-to-satellite system integrates an RF transceiver, ARM CPUs, memories, and PA to offer seamless IoT connectivity via LEO satellite networks. It boasts an optimized link budget for effective indoor signal coverage, eliminating the need for additional GNSS components. This compact SoC supports industrial temperature ranges and is engineered for a 10+ year battery life using advanced power management.
The NaviSoC, a flagship product of ChipCraft, combines a GNSS receiver with an on-chip application processor, providing an all-in-one solution for high-precision navigation and timing applications. This product is designed to meet the rigorous demands of industries such as automotive, UAVs, and smart agriculture. One of its standout features is the ability to support all major global navigation satellite systems, offering versatile functionality for various professional uses. The NaviSoC is tailored for high efficiency, delivering performance that incorporates low power consumption with robust computational capabilities. Specifically tailored for next-generation applications, NaviSoC offers flexibility through its ability to be adapted for different tasks, making it a preferred choice for many industries. It integrates seamlessly into systems requiring precision and reliability, providing developers with a wide array of programmable peripherals and interfaces. The foundational design ethos of the NaviSoC revolves around minimizing power usage while ensuring high precision and accuracy, making it an ideal component for battery-powered and portable devices. Additionally, ChipCraft provides integrated software development tools and navigation firmware, ensuring that clients can capitalize on fast time-to-market for their products. The design of the NaviSoC takes a comprehensive approach, factoring in real-world application requirements such as temperature variation and environmental challenges, thus providing a resilient and adaptable product for diverse uses.
The RT990 TIA is uniquely tailored for optical Cable Television (CATV) applications, where high performance in signal amplification is required. Integrated with a wide dynamic range, the RT990 handles input signals proficiently, converting them efficiently with minimal noise. This feature makes it ideal for maintaining signal clarity over long distances, essential in the delivery of high-quality television content. With its high linear gain and advanced automatic gain control, the RT990 ensures broadcast reliability even in fluctuating signal environments.
Cortus's Automotive AI Inference SoC is a breakthrough solution tailored for autonomous driving and advanced driver assistance systems. This SoC combines efficient image processing with AI inference capabilities, optimized for city infrastructure and mid-range vehicle markets. Built on a RISC-V architecture, the AI Inference SoC is capable of running specialized algorithms, akin to those in the Yolo series, for fast and accurate image recognition. Its low power consumption makes it suitable for embedded automotive applications requiring enhanced processing without compromising energy efficiency. This chip demonstrates its adequacy for Level 2 and Level 4 autonomous driving systems, providing a comprehensive AI-driven platform that enhances safety and operational capabilities in urban settings.
The ADQ35 model is designed to provide flexible data acquisition with a two-channel configuration operating at a 5 GSPS sampling rate or a single-channel at 10 GSPS. Its programmable DC-offset capability makes this digitizer suitable for sampling unipolar signals. It boasts an open onboard Xilinx Kintex Ultrascale KU115 FPGA which accommodates real-time digital signal processing, ensuring that users can customize their operations seamlessly.
The eSi-Comms solution provides a highly parameterisable and configurable suite for communication ASIC designs. This comprehensive collection includes OFDM-based modem and DFE IPs supporting a vast array of contemporary air interface standards such as 4G, 5G, Wi-Fi, and DVB among others. It offers robust and efficient solutions for modulation, equalization, and error correction using advanced digital signal processing algorithms. With its capabilities specific to synchronization and demodulation across multiple standards, it equips systems for optimal data flow management. The adaptable DFE features support precision in digital frequency conversion and other enhancements, fortifying both the transmitting and receiving ends of communication systems. This IP empowers wireless sensors, remote metering, and cellular devices, ensuring seamless integration into a diverse range of communication applications.
The HOTLink II Product Suite from Great River Technology is tailored for high-speed data transmission in demanding aerospace environments. This solution integrates seamlessly into avionics systems, providing robust performance for data-intensive applications. Known for its efficiency and reliability, the HOTLink II suite is ideal for organizations requiring consistent and high-speed data transfer capabilities. Designed for maximum compatibility, the HOTLink II suite supports various hardware configurations and software interfaces, ensuring smooth transitions between system components. The suite offers a comprehensive array of tools that facilitate the integration and management of high-speed data links within sophisticated avionics architectures. Whether in development or deployment, the HOTLink II suite provides unparalleled support and flexibility. In addition to its core functionalities, the HOTLink II suite assists in optimizing data integrity and system robustness throughout the system's lifecycle. Its design reflects Great River Technology's expertise in data solutions, promising long-term reliability and performance in mission-critical applications.
The Titanium Ti375 FPGA from Efinix boasts a high-density, low-power configuration, ideal for numerous advanced computing applications. Built on the well-regarded Quantum compute fabric, this FPGA integrates a robust set of features including a hardened RISC-V block, SerDes transceiver, and LPDDR4 DRAM controller, enhancing its versatility in challenging environments. The Ti375 model is designed with an intuitive I/O interface, allowing seamless communication and data handling. Its innovative architecture ensures minimal power consumption without compromising on processing speed, making it highly suitable for portable and edge devices. The inclusion of MIPI D-PHY further expands its applications in image processing and high-speed data transmission tasks. This FPGA is aligned with current market demands, emphasizing efficiency and scalability. Its architecture allows for diverse design challenges, supporting applications that transcend traditional boundaries. Efinix’s commitment to delivering sophisticated yet energy-efficient solutions is embodied in the Titanium Ti375, enabling new possibilities in the realm of computing.
The Matchstiq™ X40 by Epiq Solutions is a compact, high-performance software-defined radio (SDR) system designed to harness the power of AI and machine learning at the RF edge. Its small form factor makes it suitable for payloads with size, weight, and power constraints. The unit offers RF coverage up to 18GHz with an instantaneous bandwidth up to 450MHz, making it an excellent choice for demanding environments requiring advanced signal processing and direction finding. One of the standout features of the Matchstiq™ X40 is its integration of Nvidia's Orin NX for CPU/GPU operations and an AMD Zynq Ultrascale+ FPGA, allowing for sophisticated data processing capabilities directly at the point of RF capture. This combination offers enhanced performance for real-time signal analysis and machine learning implementations, making it suited for a variety of high-tech applications. The device supports a variety of input/output configurations, including 1 GbE, USB 3.0, and GPSDO, ensuring compatibility with numerous host systems. It offers dual configurations that support up to four receivers and two transmitters, along with options for phase-coherent multi-channel operations, thereby broadening its usability across different mission-critical tasks.
The RWM6050 baseband modem by Blu Wireless represents a highly efficient advancement in mmWave technology, offering an economical and energy-saving option for high bandwidth and capacity applications. Developed alongside Renesas, the modem is configured to work with mmWave RF chipsets to deliver scalable multi-gigabit throughput across access and backhaul networks. This modem is ideal for applications requiring substantial data transfer across several hundred meters.\n\nThe RWM6050 leverages flexible channelization and advanced modulation support to enhance data rates with dual modems and integrated mixed-signal front-end processing. This ensures that the modem can effectively handle diverse use cases with varying bandwidth demands. Its versatile subsystems, including PHY, MAC, ADC/DAC, and beamforming, facilitate adaptive solutions for complex networking environments.\n\nA standout feature of the RWM6050 is its integrated network synchronization, ensuring high precision in data delivery. Designed to meet the futuristic needs of communication networks, it helps end-users achieve superior performance through its programmable real-time scheduler and digital front-end processing. Additionally, the modem's highly digital design supports robust, secure connections needed for next-generation connectivity solutions.
Certus Semiconductor specializes in advanced RF/Analog IP solutions, tackling the intricate needs of high-performance wireless communication systems. Their cutting-edge technology provides ultra-low power wireless front-end integration, verified across a range of silicon contexts to ensure reliability and excellence. These solutions cover a comprehensive spectrum of RF configurations from silicon-proven RF IPs to fully integrated RF transceivers used in state-of-the-art wireless devices. Features of Certus's RF/Analog solutions include finely tuned custom PLLs and LNAs with frequencies reaching up to 6GHz, tailored for superior phase noise performance and minimal jitter. This level of precision ensures optimized signal integrity and power efficiency, crucial for maintaining peak operations in wireless systems like LTE, WiFi, and GNSS. Furthermore, the innovative next-generation wireless IPs cater to ultra-low latency operations necessary for modern communication protocols, demonstrating Certus Semiconductor's commitment to driving forward-thinking technology in RF design. With an inclusive approach covering custom designs and off-the-shelf IP offerings, Certus ensures that each product meets specific project demands with exceptional precision and efficiency.
The Software-Defined High PHY from AccelerComm is an adaptable solution designed for ARM processor architectures, providing versatile platform support. This PHY can function with or without hardware acceleration, catering to varying demands in capacity and power for diverse applications. It seamlessly integrates into O-RAN environments and can be tailored to optimize performance, aligning with specific network requirements. This versatile solution capitalizes on the strengths of ARM processors and offers additional flexibility through optional hardware accelerations. By providing a scalable framework, the Software-Defined High PHY supports efficient deployment, regardless of the network size or complexity. This adaptability ensures that network managers can configure the PHY to meet specific performance objectives, maximizing throughput while minimizing power consumption. Esteemed for its flexibility and ease of integration, this solution exemplifies AccelerComm's commitment to delivering high-caliber, platform-independent PHY solutions. It empowers network developers to tailor their setups, thus enhancing performance metrics like latency and spectral efficiency.
The 802.11 LDPC core facilitates high-throughput decoding in wireless communication systems. It supports dynamic frame-by-frame configuration, allowing adaptations between throughput and error correction performance. The core boasts configurable decoding iterations, aligning with required throughput and error rate specifications, delivering seamless performance for robust wireless designs.
AccelerComm's Polar coding solution is a state-of-the-art offering tailored for the 5G NR control channel, providing efficiencies that redefine how fast data can be accurately processed and transmitted. This IP is groundbreaking due to its ability to enable higher degrees of parallelism and scalability, essential for high-demand network uses. The architecture stands out due to its high degree of resource efficiency, significantly lessening the use of computational resources while ensuring top-tier performance. Its compliance with 3GPP standards ensures smooth integration within existing frameworks, making it an invaluable asset for operators focusing on control channel integrity. Particularly advantageous for its configurability, the Polar solution scales to meet exacting BLER performance parameters. This level of adaptability underpins the capability to achieve superior spectral efficiency gains, crucial for modern wireless communications.
Creonic delivers advanced Polar Encoders/Decoders that offer high flexibility and efficiency for cutting-edge communications. The company’s Polar solutions capitalize on polar code technology, which is recognized for its channel capacity achievement capabilities in the field of communications. These encoders and decoders are particularly input for Ultra Reliable Low Latency Communications (URLLC), with applications extending to 5G networks and beyond. Creonic’s solution supports various coding rates and code lengths, providing a robust framework for creating customized configurations based on customer specifications. Compatibility with major FPGA platforms allows for seamless integration into existing systems, ensuring optimal performance and scalability across numerous applications. The Polar Encoder/Decoder IP is designed to handle both short and long frames, providing enhanced reliability and ensuring data is efficiently and accurately transmitted over different communication channels.
Creonic's Turbo Encoders/Decoders offer advanced error correction features for modern digital communication systems. Originating from iterative decoding theory, the turbo codes provided are known for their efficiency and performance close to Shannon’s limit. These encoders and decoders come in various configurations to suit both existing and emergent network standards such as DVB-RCS2 and 4G LTE. Engineered with scalability in mind, Creonic's Turbo solutions support a wide range of data rates and frame sizes, making them a flexible choice for operators targeting satellite or terrestrial networks. Their modular design ensures easy integration and adaptability across various digital platforms and communication technologies. The products maintain high data integrity, enabling reliable data delivery even in high-noise environments. Creonic ensures that each turbo code solution is compliant with international standards, providing a seamless interoperability experience across diverse network architectures.
The TW330 Image Warping IP utilizes advanced GPU processing technology to offer high-performance image distortion correction. It features extensive capabilities including coordinate transformation, any-shape image transformations, and supports resolutions up to 16K x 16K for both RGB and YUV formats. Ideal for digitally correcting images distorted by wide-angle or fish-eye lenses on various devices, this technology is key in fields such as automotive display systems, VR/AR devices, and high-definition projectors. It makes real-time, on-the-fly image correction feasible, elevating the quality of visual outputs for demanding applications. Through its flexible and efficient design, TW330 enables seamless integration into systems requiring dynamic and precise image modification capabilities, paving the way for developing more interactive and immersive visual experiences.
Creonic's LDPC Encoders/Decoders are engineered to deliver high throughput and low latency for communications and data applications. The exceptional performance of these encoders and decoders ensures that they are ideally suited for applications such as satellite communications, broadband wireless, and high-speed networking. Creonic provides a comprehensive range of LDPC solutions that can be customized to match various standards, including DVB-S2X, 5G NR, IEEE, and CCSDS. Each LDPC solution is robustly engineered, offering maximum flexibility to adapt to different code rates and frame sizes. These cores are implemented to ensure compatibility with diverse FPGA platforms like Xilinx and Intel. Customers benefit from a solid framework that integrates efficient encoding and decoding mechanisms, ensuring reliable data transfer across challenging communication environments. The LDPC products stand out for their superior error correction capabilities, which help in mitigating the adverse effects of signal degradation. Creonic's solutions target both existing and emerging communications standards, ensuring future-proof reliability and performance enhancement.
The CANmodule-III is a highly advanced Controller Area Network (CAN) controller designed for sophisticated applications that require full CAN2.0B compliance. This IP module optimizes communication on the CAN bus by efficiently handling message transactions with support for FIFO and mailbox-based architectures. With a focus on system reliability, the CANmodule-III ensures seamless data flow and is versatile for various industry applications such as automotive and aerospace networks. The CANmodule-III supports an expansive set of features including enhanced diagnostic capabilities, making it ideal for applications that demand high reliability and advanced fault-tolerant functionalities. Its modular design is key for dynamic environments where scalability and flexibility are paramount. By utilizing a robust design approach based on Bosch's fundamental CAN architecture, this controller ensures compatibility and conformance with international standards, streamlining integration into existing systems. Inicore's commitment to excellence is embodied in the CANmodule-III’s design, which not only simplifies the integration process but also provides users the ability to customize functionalities. Whether the need is for rapid prototyping using FPGAs or volume production with ASICs, the CANmodule-III stands out as a preferred choice owing to its proven performance and adaptability.
The CANmodule-IIIx represents an evolution in CAN controller IP, offering an advanced set of features and capabilities for high-demand applications. This module builds upon the strengths of its predecessor with extended mailbox support, featuring 32 receive and 32 transmit mailboxes which enhance message handling capacity and ensure higher data throughput and reduced latency. For industries such as industrial automation and telecommunications, where complex data transactions are constant, the CANmodule-IIIx provides a robust platform capable of managing these requirements with efficiency and reliability. The IP module supports customization and can be seamlessly integrated into larger system architectures, enabling greater functionality and performance tuning for specific application needs. Designed with a focus on flexibility, this module adheres to CAN2.0B standards while offering unique enhancements for user-defined add-ons. These features allow for superior adaptability and scalability, making CANmodule-IIIx a versatile solution across various sectors requiring sophisticated CAN bus communications.
ArrayNav represents a significant leap forward in navigation technology through the implementation of multiple antennas which greatly enhances GNSS performance. With its capability to recognize and eliminate multipath signals or those intended for jamming or spoofing, ArrayNav ensures a high degree of accuracy and reliability in diverse environments. Utilizing four antennas along with specialized firmware, ArrayNav can place null signals in the direction of unwanted interference, thus preserving the integrity of GNSS operations. This setup not only delivers a commendable 6-18dB gain in sensitivity but also ensures sub-meter accuracy and faster acquisition times when acquiring satellite data. ArrayNav is ideal for urban canyons and complex terrains where signal integrity is often compromised by reflections and multipath. As a patented solution from EtherWhere, it efficiently remedies poor GNSS performance issues associated with interference, making it an invaluable asset in high-reliability navigation systems. Moreover, the system provides substantial improvements in sensitivity, allowing for robust navigation not just in clear open skies but also in challenging urban landscapes. Through this additive capability, ArrayNav promotes enhanced vehicular ADAS applications, boosting overall system performance and achieving higher safety standards.
Inicore's CANmodule-IIx is a FIFO-based Controller Area Network (CAN) controller IP that provides efficient and reliable communication solutions for less complex systems that still require robust CAN functionality. With the flexibility of FIFO architecture, this module is designed for systems where message ordering and buffering are crucial yet straightforward. The CANmodule-IIx facilitates seamless data exchange over the CAN bus, ensuring that all message transactions comply with the CAN2.0B standard. This makes it particularly well-suited for automotive applications, as well as industrial systems needing basic to intermediate communication capabilities while maintaining a cost-effective footprint. As part of Inicore’s vast IP portfolio, the CANmodule-IIx is engineered with a focus on simplifying integration and reducing design complexity. Its FIFO architecture provides not only reliable communication but also enhanced data handling capabilities, allowing seamless implementation in various FPGA and ASIC environments, supporting rapid development and deployment.
The LDPC Decoder tailored for 5G New Radio (NR) applications offers robust decoding capabilities with the implementation of the Min-Sum algorithm. This decoder's architecture includes advanced features such as early iteration termination, programmable bit widths, and support for HARQ-related functionalities, all aimed at optimizing decoding performance. It is a key component in managing link reliability and efficiency, suitable for advanced wireless communication systems.
The mmWave PLL provided by CoreHW is a high-precision fractional-N PLL designed for use in demanding wireless communication systems and radar applications. Operating primarily between 19 and 81 GHz, it features an adaptable frequency synthesizer with low phase noise, suitable for fast frequency chirp generation in FMCW radar systems. The design itself is frequency-scalable, allowing for customization over a wide range of mmWave frequencies.\nThe PLL integrates several key components, such as frequency multipliers that extend the range to radar frequency bands between 38-40.5 GHz and 76-81 GHz. CoreHW's mmWave PLL also offers the capability of Linear Frequency Modulation, essential for applications needing reliable chirp modulation, alongside a built-in sequencer for calibration and testing.\nThe technology used in this PLL falls under GlobalFoundries' 22FDX™ process, which ensures low power consumption, operating from voltages of 0.8V for IO and 1.2V for the RF sectors, supporting an ambient temperature spectrum of -40 to 125 degrees Celsius. The compact design ensures minimization of the area required on silicon, enhancing its applicability in advanced automotive and communication infrastructure.
The THOR Toolbox by Presto Engineering is a specialty toolbox that integrates NFC and UHF connectivity, designed to expedite the development and testing of wireless communication interfaces within ASIC designs. This IP supports wireless sensor connectivity and effective RF interfacing through a combination of analog and digital interface methodologies, providing a versatile platform for rapid prototyping and proof-of-concept creation. Engineered to facilitate direct NFC communication and UHF signal reception, the THOR Toolbox allows for efficient data transmission in demanding environments, offering flexibility for integration into various communication protocols and systems. Its design encompasses features aimed at lowering power consumption while maintaining robust connectivity capabilities, which are critical in evolving IoT applications and modern electronic systems. By leveraging the THOR Toolbox, developers can benefit from an accelerated pathway to test, verify, and implement high-performance NFC and UHF solutions. This toolbox serves as a powerful resource in enabling swift adaptation to market needs and is particularly well-suited for applications requiring dependable wireless interaction, such as asset tracking and contactless payment systems.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
CLOP Technologies' 60GHz Wireless Solution offers businesses an impressive alternative to traditional networking systems. Leveraging the IEEE 802.11ad WiFi standard and Wireless Gigabit Alliance MAC/PHY specifications, this solution achieves a peak data rate of up to 4.6Gbps. This makes it particularly suited for applications that require significant bandwidth, such as real-time, uncompressed HD video streaming and high-speed data transfers — operations that are notably quicker compared to current WiFi systems. The solution is engineered to support 802.11ad IP networking, providing a platform for IP-based applications like peer-to-peer data transfer and serving as a router or access point. Its architecture includes a USB 3.0 host interface and mechanisms for RF impairment compensation, ensuring both ease of access for host compatibility and robust performance even under high data rate operations. Operating on a frequency band ranging from 57GHz to 66GHz, the wireless solution utilizes modulation modes such as BPSK, QPSK, and 16QAM. It incorporates forward error correction (FEC) with LDPC codes, providing various coding rates for enhanced data integrity. Furthermore, the system boasts AES-128 hardware security, with quality of service maintained through IEEE 802.11e standards.
The ADQ35-WB is a versatile data acquisition module that offers a dual-channel configuration with a 5 GSPS sampling rate or a single-channel configuration at 10 GSPS. It features an impressive 9.0 GHz usable analog input bandwidth, making it ideal for high-frequency applications. This digitizer is equipped with an open onboard Xilinx Kintex Ultrascale KU115 FPGA, providing ample resources for custom real-time digital signal processing (DSP). Additionally, it supports peer-to-peer streaming at speeds of up to 14 Gbyte/s, enabling efficient data transfer to GPU, CPU, or SSD.
Circuit Porting in the AMALIA suite provides an accurate solution for migrating complex analog, mixed-signal, and RF circuits across various process nodes. It is designed to preserve design integrity and optimize the transition process by identifying and solving potential layout issues ahead of time. With its intuitive user interface, Circuit Porting minimizes the risks of deviations and enhances design reliability by maintaining original placement and floorplans.\n\nThe tool streamlines design cycle times and cost efficiency by automating several steps of the migration process, significantly cutting down the duration needed for projects to reach the market. It also includes features that facilitate smart routing and provide robust database checks to ensure quality before and after circuit porting.\n\nFor engineers, Circuit Porting offers a familiar design environment that simplifies complex tasks like instance replacement and rerouting while enabling direct simulations of original and modified designs. This ensures that the final ported design faithfully replicates the functionality of its original version, ensuring a faster and smoother migration to new technological environments.
Wireless Sensor Modules by Granite SemiCom are designed to provide high flexibility and extended range for IoT applications. Utilizing LoRa transceivers, these modules operate over long distances, making them suitable for environments where connectivity over vast areas is required. Their design is optimized for battery efficiency, ensuring long operational lifetimes with low power consumption. These modules also support over-the-air updates, enhancing their functionality and adaptability in dynamic settings. With built-in encryption, they offer secure wireless communication, crucial for safeguarding data integrity across networks.
Palma Ceia SemiDesign's 802.11ah HaLow Transceiver is expertly crafted to support IoT applications that require extended range and battery efficiency. Adhering to the IEEE 802.11ah standard, this transceiver caters to the specific demands of modern IoT and mobile devices—namely, lower power draw and substantial network reach. Designed to operate with modulation bandwidths of 1 MHz, 2 MHz, and 4 MHz, this transceiver offers integrated features such as DC offset correction and an I/Q calibration scheme. Its balanced, direct conversion receiver assists in maintaining excellent noise levels—a pivotal factor for reliable signal processing. Furthermore, the transceiver's architecture supports external power amplification to deliver increased output, crucial for wide expanses like industrial setups. Implementing interfaces such as SPI, UART, and GPIO, the 802.11ah HaLow Transceiver is highly adaptable, allowing it to seamlessly integrate into standalone systems or broader System-on-Chip solutions. Its ability to support a wide operating frequency range from 755 MHz to 928 MHz expands application versatility, making it apt for various IoT deployments from asset tracking to remote security monitoring.
Creonic’s Miscellaneous FEC and DSP IP Cores are an essential toolkit for enhancing digital signal processing capabilities across various fields. These include solutions like Viterbi Decoders, FFT/IFFT processors, and advanced BCH code implementations, which are cornerstones in data correction and signal processing. These DSP cores are engineered for high performance and efficiency, vital for applications demanding robust signal integrity and processing speed. From Doppler Channel processing found in satellite and radio communications to sophisticated stream processing in broadband networks, every core is fine-tuned for specific performance requirements. Creonic provides adaptable designs that are geared for seamless integration into existing platforms, ensuring continued enhancement of network efficiency and data reliability. The flexibility of these cores means they can be tailored to fit diverse operational standards, making them invaluable in meeting complex communication challenges.
The ADQ7DC digitizer pushes the boundaries with its 14-bit, 10 GSPS performance. Designed for high-sampling rate applications, it provides improved resolution, facilitated by its DC-coupled front-end with variable DC-offset capabilities. This digitizer supports a 3 GHz analog input bandwidth and is equipped to handle a diverse array of sensors and applications, making it a reliable tool for sophisticated data acquisition needs.
The EW6181 is a cutting-edge multi-GNSS silicon solution offering the lowest power consumption and high sensitivity for exemplary accuracy across a myriad of navigation applications. This GNSS chip is adept at processing signals from numerous satellite systems including GPS L1, Glonass, BeiDou, Galileo, and several augmentation systems like SBAS. The integrated chip comprises an RF frontend, a digital baseband processor, and an ARM microcontroller dedicated to operating the firmware, allowing for flexible integration across devices needing efficient power usage. Designed with a built-in DC-DC converter and LDOs, the EW6181 silicon streamlines its bill of materials, making it perfect for battery-powered devices, providing extended operational life without compromising on performance. By incorporating patent-protected algorithms, the EW6181 achieves a remarkably compact footprint while delivering superior performance characteristics. Especially suited for dynamic applications such as action cameras and wearables, its antenna diversity capabilities ensure exceptional connectivity and positioning fidelity. Moreover, by enabling cloud functionality, the EW6181 pushes boundaries in power efficiency and accuracy, catering to connected environments where greater precision is paramount.
The ntLDPC_DVBS2X IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2X decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the DVB-S2 and DVB-S2X standards. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2X encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. Actual encoding is performed as a three part recursive computation process, where row sums, checksums of all produced rows column-wise and finally transposed parity bit sums are calculated. The ntLDPC_DVBS2X decoder IP implements a 360-bit parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. The decoder IP permutes each block’s parity LLRs to become compatible with the layered decoding scheme and stores channel LLRs to processes them in layered format. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity submatrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit.
The PCS2500 by Palma Ceia SemiDesign is an Access Point system-on-chip designed for Wi-Fi HaLow networks, following the IEEE 802.11ah protocol. Functioning in the sub-gigahertz spectrum, it supports the construction of expansive IoT networks, offering strong connectivity even at distances reaching up to 1 km. Serving as a gateway, it connects multiple PCS2100 STA units, facilitating a comprehensive IoT infrastructure. Supporting channel bandwidths of 1 MHz and 2 MHz, the PCS2500 is engineered for minimal power consumption while ensuring robust data transfer. Its ability to manage up to 500 devices at reduced duty cycles minimizes network congestion and optimizes operational efficiency. This AP is ideal for long-range IoT applications where power saving and reliability are essential. The PCS2500's versatile architecture includes features such as Target Wake Time (TWT) and dynamic bandwidth management (RAW). These innovations reduce power demands by efficiently scheduling data transmission, while its advanced security protocols, including WPA3, offer secure communication. Supporting the latest encryption standards, it is well-suited for sensitive applications in sectors like industrial control and smart sensors.
The LTE Lite offers a high-performance PHY layer for user equipment with compliance to CAT 0/1 standards. Supporting flexible channel bandwidths, it works seamlessly with standard RF tuners. The design features automated demodulation via a controlling state machine and includes frequency and timing correction, ensuring accuracy even in high-offset environments. Synthesizable in Verilog-2001, it's highly adaptable for various telecommunication needs.
Palma Ceia's PCS2100 is a Wi-Fi HaLow STA modem chip designed for the client side of IoT networks. Built on the IEEE 802.11ah specification, it forms part of a complete Wi-Fi HaLow network alongside the PCS2500 AP, maximizing range and efficiency. This transceiver operates in the sub-gigahertz range, achieving exceptional connectivity over extended distances while maintaining low power consumption—a key factor for IoT devices. Among its standout features, the PCS2100 supports advanced protocols like Target Wake Time (TWT) and Resource Allocation Windowing (RAW), minimizing contention and reducing power usage. Thanks to its comprehensive modulation capabilities, it handles a variety of data rates and ensures high reliability, making it ideal for IoT environments that demand constant connectivity. With outstanding phase noise and linearity performance, it ensures strict adherence to error vector magnitude specifications for both transmission and reception. The chip's robust design includes digital functionalities for calibration and signal path adjustments, ensuring consistent operation across a variety of conditions. Its security features are cutting-edge as well, with WPA3 and OWE support ensuring strong encryption and network protection. This makes the PCS2100 suitable for a variety of applications from industrial automation to smart metering solutions.
The Post-Quantum Cryptography (PQC) IP from Secure-IC offers solutions resilient against quantum computing threats. The PQC IP includes a hybrid hardware-software model that enables scalable security across various applications. It forms part of Secure-IC's forward-looking approach to cybersecurity that emphasizes both hardware accelerators and software libraries, which execute key generation and encapsulation with protection against side-channel attacks. This kind of versatility in cryptography makes it an excellent choice for next-generation secure communication platforms.
AccelerComm's High PHY Accelerators are advanced solutions featuring a library of IP cores that cater to a range of 5G NR needs, including key signal processing algorithms. These accelerators are aimed at maximizing efficiency in data throughput and reducing latency, which are essential for modern communication standards. Providing enhancements such as LDPC that improves BLER significantly, these accelerators deliver reduced spectral costs and power consumption. They are available in several forms - ASICs, FPGAs, or software-only configurations - and can be deployed in varied hardware environments. The integration of complex algorithms like Hybrid Automatic Repeat reQuest (HARQ) and channel estimation signify their role in enhancing the robustness and reliability of 5G communications. Born from rigorous academic research, the High PHY Accelerators are highly configurable, adapting to specific network demands. Their success is validated by compliance with key 3GPP standards, making them a cornerstone technology for achieving superior network performance and efficiency.
The Hyperspectral Imaging System developed by IMEC revolutionizes the observation capabilities of a wide spectrum of wavelengths in just one frame. This system taps into the potential of spectral imaging, advancing Earth and space exploration through its ability to capture detailed environmental data. The hyperspectral imaging system, being chip-based, ensures enhanced efficiency and precision while lowering the energy footprint compared to traditional methods. This cutting-edge technology is capable of transcending applications from Earth monitoring, where it aids in identifying and assessing natural resources, to next-generation satellite observation. By employing advanced methodologies for data acquisition and processing, the hyperspectral imaging system enhances the quality and accuracy of images captured from diverse environments. Moreover, its compact and efficient form factor makes it adaptable for integration into various imaging platforms, providing unparalleled insights with high fidelity. Furthering the realm of optical imaging, IMEC's system is designed for broad adaptability across sectors like agriculture, forestry, and urban planning, facilitating an in-depth understanding of ecological and environmental dynamics. The seamless integration with machine learning algorithms allows for the conversion of vast spectral data into actionable insights, providing users with the tools needed to make informed decisions on conservation, resource management, and urban development. Combining state-of-the-art sensor technologies with robust computing abilities, IMEC's Hyperspectral Imaging System stands as a cornerstone of modern observational science.
AccelerComm offers an LDPC solution meticulously crafted for 5G NR channels that promises efficient error correction and superior throughput. This solution represents the best of block-parallel and row-parallel decode architectures, enhancing efficiency while maintaining top-notch performance. Widely recognized for its hardware efficiency, the LDPC enhances signal integrity in the data channel, ensuring minimal latency. It adheres to the complete 3GPP standardization, supporting code and transport block processing. The architecture's configurability supports diverse deployment needs, allowing seamless integration into existing network environments. Delivered in ASIC, FPGA, or software-only form factors, AccelerComm's LDPC block is ideal for operators seeking to maximize reliability and performance in their communications infrastructures. This IP stands as a testament to AccelerComm's innovation, marrying tradition with modern demands for enhanced digital communications.
Perfect for advanced parking solutions, the ASPER radar sensor operates at 79GHz, providing superior performance compared to traditional ultrasonic systems. Designed to deliver a 180° coverage with a single module, it offers enhanced detection capabilities for both passenger and commercial vehicles. ASPER's edge processing and domain-specific features make it ideal for automotive applications like blind spot detection and tailgate protection, while ensuring accuracy unaffected by environmental conditions.
The Convolutional Encoder and Viterbi Decoder are integral components of modern digital communication systems, specifically designed to enhance error correction capabilities. This setup is aimed at achieving superior Bit Error Rates (BER) with sustained Signal-to-Noise Ratios (SNRs), leveraging forward error correction mechanisms. The Convolutional Encoder established here operates with a configuration of (3, 1, 4), optimally structuring data for robust transmission by applying a series of generator polynomials. On the decoding end, the Viterbi algorithm is employed, a maximum likelihood convolutional decoder known for its efficacy in decoding convolutional codes. The integration of these components into wireless communication systems affords improved reliability and performance, especially crucial in maintaining data integrity over unstable or noisy communication channels. This solution is highly adaptable, supporting various polynomial configurations and customization needs per customer requirements. Such technology serves wireless applications that demand efficient correction and recovery of transmitted data, and it is suitable for systems where minimal intervention is desired while maintaining high data integrity. This systematic approach integrates support for complex encryption methods, allowing secure and reliable data transfer across multiple communication protocols.
The Digital PreDistortion (DPD) Solution by Systems4Silicon is a cutting-edge technology developed to maximize the power efficiency of RF power amplifiers. Known as FlexDPD, this solution is vendor-independent, allowing it to be compiled across various FPGA or ASIC platforms. It's designed to be scalable, optimizing resources according to bandwidth, performance, and multiple antennae requirements. One of the key benefits of FlexDPD is its substantial efficiency improvements, reaching over 50% when used with modern GaN devices in Doherty configurations, surpassing distortion improvements of 45 dB. FlexDPD is versatile, operating with communication standards including multi-carrier, multi-standard, and various generations from 2G to 5G. It supports both time division and frequency division duplexing, and can accommodate wide Tx bandwidths, limited only by equipment capabilities. The technology is also agnostic to amplifier topology and transistor technology, providing broad applicability across different setups, whether class A/B or Doherty, and different transistor types like LDMOS, GaAs, or GaN. This technology integrates seamlessly with Crest Factor Reduction (CFR) and envelope tracking techniques, ensuring a low footprint on resources while maximizing efficiency. With complementary integration and performance analysis tools, Systems4Silicon provides comprehensive support and documentation, ensuring that clients can maximize the benefits of their DPD solution.
The DVB-RCS and IEEE 802.16 WiMAX Turbo Decoder is expertly crafted for decoding tasks in high-speed data networks, particularly those using satellite and broadband wireless communication standards. This 8 state Duobinary Turbo Decoder features an optional 64 state Viterbi decoder, highlighting its capacity for intricate data throughput and error correction. Functional in a multitude of data environments, this decoder can handle a variety of signal paths, ensuring robust data recovery and integrity. Its architecture is especially suited for dynamic network conditions, offering adaptability and reliability-critical factors in maintaining service quality in challenging communication scenarios. This Decoder is ideal for systems operating under diverse protocols, ensuring seamless interoperability and efficient error detection and correction. By optimizing data processing technologies, it supports high-speed data exchanges across broader channels, catering to the growing demand for superior network performance in modern telecommunication infrastructures.