All IPs > Wireless Communication > 3GPP-5G
The evolution of mobile communication technology has reached a pivotal stage with the introduction of 3GPP-5G, a standard that promises to transform wireless communications. In the realm of semiconductor IP, 3GPP-5G solutions encompass a wide range of technologies that are integral to developing and deploying next-generation communication networks. These semiconductor IPs provide the foundational architecture required for high-speed data transfer, ultra-reliable low latency, and massive connectivity, supporting the diverse and demanding use cases of modern mobile and IoT applications.
3GPP-5G semiconductor IP solutions are crucial for manufacturers and developers looking to design cutting-edge communication systems. These IPs enable the seamless integration of 5G capabilities into a variety of devices, from smartphones and smart home appliances to industrial IoT sensors and autonomous vehicles. They are designed to handle complex signal processing, support multiple frequency bands, and deliver enhanced performance metrics such as increased bandwidth and improved energy efficiency. By leveraging these semiconductor IPs, companies can significantly reduce time-to-market and development costs while ensuring that the end devices meet stringent 5G standards.
Within this category, you'll find a broad array of semiconductor IP products tailored to meet the specific challenges and opportunities posed by 5G networks. These include baseband processors, RF transceivers, and advanced modulation solutions, all of which are engineered to support the high demands of 5G technology. Furthermore, these IPs often come with software support and development kits that facilitate faster adoption and implementation into existing systems.
As the world moves towards more interconnected and intelligent systems, 3GPP-5G semiconductor IPs provide the essential building blocks for future innovations. By enabling the next generation of wireless communication, these IPs not only enhance current technologies but also pave the way for new applications and services that were previously unimaginable. Whether you are developing solutions for consumer electronics, automotive, healthcare, or smart cities, the 3GPP-5G semiconductor IP category offers the tools and technologies to bring your vision to life.
The ORC3990 SoC is a state-of-the-art solution designed for satellite IoT applications within Totum's DMSS™ network. This low-power sensor-to-satellite system integrates an RF transceiver, ARM CPUs, memories, and PA to offer seamless IoT connectivity via LEO satellite networks. It boasts an optimized link budget for effective indoor signal coverage, eliminating the need for additional GNSS components. This compact SoC supports industrial temperature ranges and is engineered for a 10+ year battery life using advanced power management.
The eSi-Comms solution provides a highly parameterisable and configurable suite for communication ASIC designs. This comprehensive collection includes OFDM-based modem and DFE IPs supporting a vast array of contemporary air interface standards such as 4G, 5G, Wi-Fi, and DVB among others. It offers robust and efficient solutions for modulation, equalization, and error correction using advanced digital signal processing algorithms. With its capabilities specific to synchronization and demodulation across multiple standards, it equips systems for optimal data flow management. The adaptable DFE features support precision in digital frequency conversion and other enhancements, fortifying both the transmitting and receiving ends of communication systems. This IP empowers wireless sensors, remote metering, and cellular devices, ensuring seamless integration into a diverse range of communication applications.
The Matchstiq™ X40 by Epiq Solutions is a compact, high-performance software-defined radio (SDR) system designed to harness the power of AI and machine learning at the RF edge. Its small form factor makes it suitable for payloads with size, weight, and power constraints. The unit offers RF coverage up to 18GHz with an instantaneous bandwidth up to 450MHz, making it an excellent choice for demanding environments requiring advanced signal processing and direction finding. One of the standout features of the Matchstiq™ X40 is its integration of Nvidia's Orin NX for CPU/GPU operations and an AMD Zynq Ultrascale+ FPGA, allowing for sophisticated data processing capabilities directly at the point of RF capture. This combination offers enhanced performance for real-time signal analysis and machine learning implementations, making it suited for a variety of high-tech applications. The device supports a variety of input/output configurations, including 1 GbE, USB 3.0, and GPSDO, ensuring compatibility with numerous host systems. It offers dual configurations that support up to four receivers and two transmitters, along with options for phase-coherent multi-channel operations, thereby broadening its usability across different mission-critical tasks.
The RWM6050 baseband modem by Blu Wireless represents a highly efficient advancement in mmWave technology, offering an economical and energy-saving option for high bandwidth and capacity applications. Developed alongside Renesas, the modem is configured to work with mmWave RF chipsets to deliver scalable multi-gigabit throughput across access and backhaul networks. This modem is ideal for applications requiring substantial data transfer across several hundred meters.\n\nThe RWM6050 leverages flexible channelization and advanced modulation support to enhance data rates with dual modems and integrated mixed-signal front-end processing. This ensures that the modem can effectively handle diverse use cases with varying bandwidth demands. Its versatile subsystems, including PHY, MAC, ADC/DAC, and beamforming, facilitate adaptive solutions for complex networking environments.\n\nA standout feature of the RWM6050 is its integrated network synchronization, ensuring high precision in data delivery. Designed to meet the futuristic needs of communication networks, it helps end-users achieve superior performance through its programmable real-time scheduler and digital front-end processing. Additionally, the modem's highly digital design supports robust, secure connections needed for next-generation connectivity solutions.
Certus Semiconductor specializes in advanced RF/Analog IP solutions, tackling the intricate needs of high-performance wireless communication systems. Their cutting-edge technology provides ultra-low power wireless front-end integration, verified across a range of silicon contexts to ensure reliability and excellence. These solutions cover a comprehensive spectrum of RF configurations from silicon-proven RF IPs to fully integrated RF transceivers used in state-of-the-art wireless devices. Features of Certus's RF/Analog solutions include finely tuned custom PLLs and LNAs with frequencies reaching up to 6GHz, tailored for superior phase noise performance and minimal jitter. This level of precision ensures optimized signal integrity and power efficiency, crucial for maintaining peak operations in wireless systems like LTE, WiFi, and GNSS. Furthermore, the innovative next-generation wireless IPs cater to ultra-low latency operations necessary for modern communication protocols, demonstrating Certus Semiconductor's commitment to driving forward-thinking technology in RF design. With an inclusive approach covering custom designs and off-the-shelf IP offerings, Certus ensures that each product meets specific project demands with exceptional precision and efficiency.
The Software-Defined High PHY from AccelerComm is an adaptable solution designed for ARM processor architectures, providing versatile platform support. This PHY can function with or without hardware acceleration, catering to varying demands in capacity and power for diverse applications. It seamlessly integrates into O-RAN environments and can be tailored to optimize performance, aligning with specific network requirements. This versatile solution capitalizes on the strengths of ARM processors and offers additional flexibility through optional hardware accelerations. By providing a scalable framework, the Software-Defined High PHY supports efficient deployment, regardless of the network size or complexity. This adaptability ensures that network managers can configure the PHY to meet specific performance objectives, maximizing throughput while minimizing power consumption. Esteemed for its flexibility and ease of integration, this solution exemplifies AccelerComm's commitment to delivering high-caliber, platform-independent PHY solutions. It empowers network developers to tailor their setups, thus enhancing performance metrics like latency and spectral efficiency.
The 802.11 LDPC core facilitates high-throughput decoding in wireless communication systems. It supports dynamic frame-by-frame configuration, allowing adaptations between throughput and error correction performance. The core boasts configurable decoding iterations, aligning with required throughput and error rate specifications, delivering seamless performance for robust wireless designs.
AccelerComm's Polar coding solution is a state-of-the-art offering tailored for the 5G NR control channel, providing efficiencies that redefine how fast data can be accurately processed and transmitted. This IP is groundbreaking due to its ability to enable higher degrees of parallelism and scalability, essential for high-demand network uses. The architecture stands out due to its high degree of resource efficiency, significantly lessening the use of computational resources while ensuring top-tier performance. Its compliance with 3GPP standards ensures smooth integration within existing frameworks, making it an invaluable asset for operators focusing on control channel integrity. Particularly advantageous for its configurability, the Polar solution scales to meet exacting BLER performance parameters. This level of adaptability underpins the capability to achieve superior spectral efficiency gains, crucial for modern wireless communications.
Creonic delivers advanced Polar Encoders/Decoders that offer high flexibility and efficiency for cutting-edge communications. The company’s Polar solutions capitalize on polar code technology, which is recognized for its channel capacity achievement capabilities in the field of communications. These encoders and decoders are particularly input for Ultra Reliable Low Latency Communications (URLLC), with applications extending to 5G networks and beyond. Creonic’s solution supports various coding rates and code lengths, providing a robust framework for creating customized configurations based on customer specifications. Compatibility with major FPGA platforms allows for seamless integration into existing systems, ensuring optimal performance and scalability across numerous applications. The Polar Encoder/Decoder IP is designed to handle both short and long frames, providing enhanced reliability and ensuring data is efficiently and accurately transmitted over different communication channels.
Creonic's Turbo Encoders/Decoders offer advanced error correction features for modern digital communication systems. Originating from iterative decoding theory, the turbo codes provided are known for their efficiency and performance close to Shannon’s limit. These encoders and decoders come in various configurations to suit both existing and emergent network standards such as DVB-RCS2 and 4G LTE. Engineered with scalability in mind, Creonic's Turbo solutions support a wide range of data rates and frame sizes, making them a flexible choice for operators targeting satellite or terrestrial networks. Their modular design ensures easy integration and adaptability across various digital platforms and communication technologies. The products maintain high data integrity, enabling reliable data delivery even in high-noise environments. Creonic ensures that each turbo code solution is compliant with international standards, providing a seamless interoperability experience across diverse network architectures.
Creonic's LDPC Encoders/Decoders are engineered to deliver high throughput and low latency for communications and data applications. The exceptional performance of these encoders and decoders ensures that they are ideally suited for applications such as satellite communications, broadband wireless, and high-speed networking. Creonic provides a comprehensive range of LDPC solutions that can be customized to match various standards, including DVB-S2X, 5G NR, IEEE, and CCSDS. Each LDPC solution is robustly engineered, offering maximum flexibility to adapt to different code rates and frame sizes. These cores are implemented to ensure compatibility with diverse FPGA platforms like Xilinx and Intel. Customers benefit from a solid framework that integrates efficient encoding and decoding mechanisms, ensuring reliable data transfer across challenging communication environments. The LDPC products stand out for their superior error correction capabilities, which help in mitigating the adverse effects of signal degradation. Creonic's solutions target both existing and emerging communications standards, ensuring future-proof reliability and performance enhancement.
ArrayNav represents a significant leap forward in navigation technology through the implementation of multiple antennas which greatly enhances GNSS performance. With its capability to recognize and eliminate multipath signals or those intended for jamming or spoofing, ArrayNav ensures a high degree of accuracy and reliability in diverse environments. Utilizing four antennas along with specialized firmware, ArrayNav can place null signals in the direction of unwanted interference, thus preserving the integrity of GNSS operations. This setup not only delivers a commendable 6-18dB gain in sensitivity but also ensures sub-meter accuracy and faster acquisition times when acquiring satellite data. ArrayNav is ideal for urban canyons and complex terrains where signal integrity is often compromised by reflections and multipath. As a patented solution from EtherWhere, it efficiently remedies poor GNSS performance issues associated with interference, making it an invaluable asset in high-reliability navigation systems. Moreover, the system provides substantial improvements in sensitivity, allowing for robust navigation not just in clear open skies but also in challenging urban landscapes. Through this additive capability, ArrayNav promotes enhanced vehicular ADAS applications, boosting overall system performance and achieving higher safety standards.
The mmWave PLL provided by CoreHW is a high-precision fractional-N PLL designed for use in demanding wireless communication systems and radar applications. Operating primarily between 19 and 81 GHz, it features an adaptable frequency synthesizer with low phase noise, suitable for fast frequency chirp generation in FMCW radar systems. The design itself is frequency-scalable, allowing for customization over a wide range of mmWave frequencies.\nThe PLL integrates several key components, such as frequency multipliers that extend the range to radar frequency bands between 38-40.5 GHz and 76-81 GHz. CoreHW's mmWave PLL also offers the capability of Linear Frequency Modulation, essential for applications needing reliable chirp modulation, alongside a built-in sequencer for calibration and testing.\nThe technology used in this PLL falls under GlobalFoundries' 22FDX™ process, which ensures low power consumption, operating from voltages of 0.8V for IO and 1.2V for the RF sectors, supporting an ambient temperature spectrum of -40 to 125 degrees Celsius. The compact design ensures minimization of the area required on silicon, enhancing its applicability in advanced automotive and communication infrastructure.
The LDPC Decoder tailored for 5G New Radio (NR) applications offers robust decoding capabilities with the implementation of the Min-Sum algorithm. This decoder's architecture includes advanced features such as early iteration termination, programmable bit widths, and support for HARQ-related functionalities, all aimed at optimizing decoding performance. It is a key component in managing link reliability and efficiency, suitable for advanced wireless communication systems.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
CLOP Technologies' 60GHz Wireless Solution offers businesses an impressive alternative to traditional networking systems. Leveraging the IEEE 802.11ad WiFi standard and Wireless Gigabit Alliance MAC/PHY specifications, this solution achieves a peak data rate of up to 4.6Gbps. This makes it particularly suited for applications that require significant bandwidth, such as real-time, uncompressed HD video streaming and high-speed data transfers — operations that are notably quicker compared to current WiFi systems. The solution is engineered to support 802.11ad IP networking, providing a platform for IP-based applications like peer-to-peer data transfer and serving as a router or access point. Its architecture includes a USB 3.0 host interface and mechanisms for RF impairment compensation, ensuring both ease of access for host compatibility and robust performance even under high data rate operations. Operating on a frequency band ranging from 57GHz to 66GHz, the wireless solution utilizes modulation modes such as BPSK, QPSK, and 16QAM. It incorporates forward error correction (FEC) with LDPC codes, providing various coding rates for enhanced data integrity. Furthermore, the system boasts AES-128 hardware security, with quality of service maintained through IEEE 802.11e standards.
Circuit Porting in the AMALIA suite provides an accurate solution for migrating complex analog, mixed-signal, and RF circuits across various process nodes. It is designed to preserve design integrity and optimize the transition process by identifying and solving potential layout issues ahead of time. With its intuitive user interface, Circuit Porting minimizes the risks of deviations and enhances design reliability by maintaining original placement and floorplans.\n\nThe tool streamlines design cycle times and cost efficiency by automating several steps of the migration process, significantly cutting down the duration needed for projects to reach the market. It also includes features that facilitate smart routing and provide robust database checks to ensure quality before and after circuit porting.\n\nFor engineers, Circuit Porting offers a familiar design environment that simplifies complex tasks like instance replacement and rerouting while enabling direct simulations of original and modified designs. This ensures that the final ported design faithfully replicates the functionality of its original version, ensuring a faster and smoother migration to new technological environments.
Palma Ceia SemiDesign's 802.11ah HaLow Transceiver is expertly crafted to support IoT applications that require extended range and battery efficiency. Adhering to the IEEE 802.11ah standard, this transceiver caters to the specific demands of modern IoT and mobile devices—namely, lower power draw and substantial network reach. Designed to operate with modulation bandwidths of 1 MHz, 2 MHz, and 4 MHz, this transceiver offers integrated features such as DC offset correction and an I/Q calibration scheme. Its balanced, direct conversion receiver assists in maintaining excellent noise levels—a pivotal factor for reliable signal processing. Furthermore, the transceiver's architecture supports external power amplification to deliver increased output, crucial for wide expanses like industrial setups. Implementing interfaces such as SPI, UART, and GPIO, the 802.11ah HaLow Transceiver is highly adaptable, allowing it to seamlessly integrate into standalone systems or broader System-on-Chip solutions. Its ability to support a wide operating frequency range from 755 MHz to 928 MHz expands application versatility, making it apt for various IoT deployments from asset tracking to remote security monitoring.
The EW6181 is a cutting-edge multi-GNSS silicon solution offering the lowest power consumption and high sensitivity for exemplary accuracy across a myriad of navigation applications. This GNSS chip is adept at processing signals from numerous satellite systems including GPS L1, Glonass, BeiDou, Galileo, and several augmentation systems like SBAS. The integrated chip comprises an RF frontend, a digital baseband processor, and an ARM microcontroller dedicated to operating the firmware, allowing for flexible integration across devices needing efficient power usage. Designed with a built-in DC-DC converter and LDOs, the EW6181 silicon streamlines its bill of materials, making it perfect for battery-powered devices, providing extended operational life without compromising on performance. By incorporating patent-protected algorithms, the EW6181 achieves a remarkably compact footprint while delivering superior performance characteristics. Especially suited for dynamic applications such as action cameras and wearables, its antenna diversity capabilities ensure exceptional connectivity and positioning fidelity. Moreover, by enabling cloud functionality, the EW6181 pushes boundaries in power efficiency and accuracy, catering to connected environments where greater precision is paramount.
The PCS2500 by Palma Ceia SemiDesign is an Access Point system-on-chip designed for Wi-Fi HaLow networks, following the IEEE 802.11ah protocol. Functioning in the sub-gigahertz spectrum, it supports the construction of expansive IoT networks, offering strong connectivity even at distances reaching up to 1 km. Serving as a gateway, it connects multiple PCS2100 STA units, facilitating a comprehensive IoT infrastructure. Supporting channel bandwidths of 1 MHz and 2 MHz, the PCS2500 is engineered for minimal power consumption while ensuring robust data transfer. Its ability to manage up to 500 devices at reduced duty cycles minimizes network congestion and optimizes operational efficiency. This AP is ideal for long-range IoT applications where power saving and reliability are essential. The PCS2500's versatile architecture includes features such as Target Wake Time (TWT) and dynamic bandwidth management (RAW). These innovations reduce power demands by efficiently scheduling data transmission, while its advanced security protocols, including WPA3, offer secure communication. Supporting the latest encryption standards, it is well-suited for sensitive applications in sectors like industrial control and smart sensors.
The LTE Lite offers a high-performance PHY layer for user equipment with compliance to CAT 0/1 standards. Supporting flexible channel bandwidths, it works seamlessly with standard RF tuners. The design features automated demodulation via a controlling state machine and includes frequency and timing correction, ensuring accuracy even in high-offset environments. Synthesizable in Verilog-2001, it's highly adaptable for various telecommunication needs.
Palma Ceia's PCS2100 is a Wi-Fi HaLow STA modem chip designed for the client side of IoT networks. Built on the IEEE 802.11ah specification, it forms part of a complete Wi-Fi HaLow network alongside the PCS2500 AP, maximizing range and efficiency. This transceiver operates in the sub-gigahertz range, achieving exceptional connectivity over extended distances while maintaining low power consumption—a key factor for IoT devices. Among its standout features, the PCS2100 supports advanced protocols like Target Wake Time (TWT) and Resource Allocation Windowing (RAW), minimizing contention and reducing power usage. Thanks to its comprehensive modulation capabilities, it handles a variety of data rates and ensures high reliability, making it ideal for IoT environments that demand constant connectivity. With outstanding phase noise and linearity performance, it ensures strict adherence to error vector magnitude specifications for both transmission and reception. The chip's robust design includes digital functionalities for calibration and signal path adjustments, ensuring consistent operation across a variety of conditions. Its security features are cutting-edge as well, with WPA3 and OWE support ensuring strong encryption and network protection. This makes the PCS2100 suitable for a variety of applications from industrial automation to smart metering solutions.
The Post-Quantum Cryptography (PQC) IP from Secure-IC offers solutions resilient against quantum computing threats. The PQC IP includes a hybrid hardware-software model that enables scalable security across various applications. It forms part of Secure-IC's forward-looking approach to cybersecurity that emphasizes both hardware accelerators and software libraries, which execute key generation and encapsulation with protection against side-channel attacks. This kind of versatility in cryptography makes it an excellent choice for next-generation secure communication platforms.
AccelerComm's High PHY Accelerators are advanced solutions featuring a library of IP cores that cater to a range of 5G NR needs, including key signal processing algorithms. These accelerators are aimed at maximizing efficiency in data throughput and reducing latency, which are essential for modern communication standards. Providing enhancements such as LDPC that improves BLER significantly, these accelerators deliver reduced spectral costs and power consumption. They are available in several forms - ASICs, FPGAs, or software-only configurations - and can be deployed in varied hardware environments. The integration of complex algorithms like Hybrid Automatic Repeat reQuest (HARQ) and channel estimation signify their role in enhancing the robustness and reliability of 5G communications. Born from rigorous academic research, the High PHY Accelerators are highly configurable, adapting to specific network demands. Their success is validated by compliance with key 3GPP standards, making them a cornerstone technology for achieving superior network performance and efficiency.
AccelerComm offers an LDPC solution meticulously crafted for 5G NR channels that promises efficient error correction and superior throughput. This solution represents the best of block-parallel and row-parallel decode architectures, enhancing efficiency while maintaining top-notch performance. Widely recognized for its hardware efficiency, the LDPC enhances signal integrity in the data channel, ensuring minimal latency. It adheres to the complete 3GPP standardization, supporting code and transport block processing. The architecture's configurability supports diverse deployment needs, allowing seamless integration into existing network environments. Delivered in ASIC, FPGA, or software-only form factors, AccelerComm's LDPC block is ideal for operators seeking to maximize reliability and performance in their communications infrastructures. This IP stands as a testament to AccelerComm's innovation, marrying tradition with modern demands for enhanced digital communications.
The Digital PreDistortion (DPD) Solution by Systems4Silicon is a cutting-edge technology developed to maximize the power efficiency of RF power amplifiers. Known as FlexDPD, this solution is vendor-independent, allowing it to be compiled across various FPGA or ASIC platforms. It's designed to be scalable, optimizing resources according to bandwidth, performance, and multiple antennae requirements. One of the key benefits of FlexDPD is its substantial efficiency improvements, reaching over 50% when used with modern GaN devices in Doherty configurations, surpassing distortion improvements of 45 dB. FlexDPD is versatile, operating with communication standards including multi-carrier, multi-standard, and various generations from 2G to 5G. It supports both time division and frequency division duplexing, and can accommodate wide Tx bandwidths, limited only by equipment capabilities. The technology is also agnostic to amplifier topology and transistor technology, providing broad applicability across different setups, whether class A/B or Doherty, and different transistor types like LDMOS, GaAs, or GaN. This technology integrates seamlessly with Crest Factor Reduction (CFR) and envelope tracking techniques, ensuring a low footprint on resources while maximizing efficiency. With complementary integration and performance analysis tools, Systems4Silicon provides comprehensive support and documentation, ensuring that clients can maximize the benefits of their DPD solution.
The PUSCH Equalizer by AccelerComm is designed to enhance spectral efficiency in wireless solutions employing multiple antennas. It utilizes sophisticated equalization algorithms, implemented directly in hardware to efficiently tackle signal interference and noise, thus improving overall data transmission quality. This Equalizer is integral to the Push Decoder, supplementing its functionality with advanced decoding capabilities, including LDPC and Polar, while maintaining alignment with 3GPP NR specifications such as TS 38.211 and 38.212. By doubling spectral efficiency depending on deployment conditions, the PUSCH Equalizer reduces operational expenditures and power requirements significantly. AccelerComm's PUSCH Equalizer is available for both FPGA and ASIC platforms, ensuring flexibility for future-proof deployment in diverse environments. Its implementation shortens time-to-market by enabling high-quality signal processing, which results in enhanced network performance.
This front-end module is engineered to support the advanced communication standards of WiFi6, LTE, and 5G, operating within a frequency range of 2.4 to 7 GHz. Designed for integration in mobile and cellular devices, it combines a switch, low-noise amplifier (LNA), and power amplifier (PA), ensuring optimal performance across various communication protocols. The module's architecture is crafted to deliver superior connectivity and high-speed data transfer capabilities, bolstering the signal's integrity through each stage of processing. It provides excellent linearity and low noise figures, crucial for maintaining the high quality of service required in today's communication networks. Furthermore, this front-end module is noted for its power-efficient design, which is vital for extending device battery life while managing the demands of new generation communication technologies. These features make it a fundamental component for devices aiming to offer state-of-the-art wireless connectivity.
The Digital Radio (GDR) from GIRD Systems is an advanced software-defined radio (SDR) platform that offers extensive flexibility and adaptability. It is characterized by its multi-channel capabilities and high-speed signal processing resources, allowing it to meet a diverse range of system requirements. Built on a core single board module, this radio can be configured for both embedded and standalone operations, supporting a wide frequency range. The GDR can operate with either one or two independent transceivers, with options for full or half duplex configurations. It supports single channel setups as well as multiple-input multiple-output (MIMO) configurations, providing significant adaptability in communication scenarios. This flexibility makes it an ideal choice for systems that require rapid reconfiguration or scalability. Known for its robust construction, the GDR is designed to address challenging signal processing needs in congested environments, making it suitable for a variety of applications. Whether used in defense, communications, or electronic warfare, the GDR's ability to seamlessly switch configurations ensures it meets the evolving demands of modern communications technology.
Ubi.cloud represents a transformative leap in IoT tracking innovation, targeting the reduction of power consumption by transferring GPS and Wi-Fi processing to the cloud. This strategic shift helps in creating compact, efficient IoT tracking devices that boast a reduced footprint and minimized cost. By enhancing power efficiency, Ubi.cloud supports improved device longevity and operational cost, positioning itself as a vital element for device and chipset manufacturers seeking to manage IoT tracking efficiently. The Ubi.cloud platform integrates two core technologies: UbiGNSS and UbiWiFi. UbiGNSS manages outdoor geolocation through GPS, providing impressive savings by reducing the positioning time drastically compared to traditional methods. Meanwhile, UbiWiFi facilitates indoor urban geolocation through efficient Wi-Fi sniffing, ensuring performance that rivals native Wi-Fi solutions. Beyond its technological advantages, Ubi.cloud enables flexible business models with options for pay-as-you-go or lifetime licenses, catering to diverse market needs. Compatibility with low-power wide area network technologies such as Sigfox, LoRa, NB-IoT, and LTE-M offers users versatile use-cases in asset tracking and enhances the effectiveness of connected solutions in various sectors.
The hellaPHY Positioning Solution by PHY Wireless utilizes cutting-edge technology for high precision and secure location tracking over cellular networks. It is particularly designed to cater to massive IoT applications, providing low-power and cost-efficient solutions that work seamlessly indoors and outdoors. Leveraging 5G and advanced edge computing, this solution ensures maximum privacy and scalability, making it ideal for diverse applications ranging from smart labels to logistics tracking. This solution dramatically outperforms traditional GNSS systems by using far less data, reducing costs, and enhancing spectral efficiency. Its innovative approach involves device-based processing of standardized 5G signals, which means the device's location is calculated locally. This not only improves speed and accuracy but also maintains a high level of data security, as the location information is encrypted and not shared with third-party servers. Designed with practicality and adaptability in mind, the hellaPHY Positioning Solution integrates effortlessly into existing hardware through a simple API, supporting a range of devices without the need for extensive modifications. With PHY Wireless's patented algorithms, operators can optimize their spectrum use, and users enjoy a robust location service that meets various operational demands. The technology underlying the hellaPHY Positioning Solution stands as evidence of PHY Wireless's commitment to innovation, ensuring that their products meet the growing needs of the IoT landscape. With support for existing LTE and 5G networks, this solution offers businesses a future-proof method to enhance operational efficiencies and service offerings.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
Dyumnin's RISCV SoC is built around a robust 64-bit quad-core server class RISC-V CPU, offering various subsystems that cater to AI/ML, automotive, multimedia, memory, and cryptographic needs. This SoC is notable for its AI accelerator, including a custom CPU and tensor flow unit designed to expedite AI tasks. Furthermore, the communication subsystem supports a wide array of protocols like PCIe, Ethernet, and USB, ensuring versatile connectivity. As for the automotive sector, it includes CAN and SafeSPI IPs, reinforcing its utility in diverse applications such as automotive systems.
The 3GPP LTE Turbo Decoder is engineered to enhance data processing in high-performance mobile networks. With an 8 state configuration and options for 1, 2, 4, or 8 parallel MAP decoders, it is designed to significantly improve error correction, ensuring reliable and high-speed data transmission in LTE environments. This decoder is optimized for networks where bandwidth efficiency is crucial, achieving peak performance while effectively handling the noise and interference prevalent in mobile networks. The option to integrate multiple parallel decoders allows for customized implementations, aligning with specific mobile network demands and optimizing overall system throughput and reliability. Deploying this decoder can vastly improve application responsiveness and network resource management. It plays a pivotal role in the tech infrastructure necessary to support 4G LTE services, meeting the high expectations for connectivity and data integrity demanded by users and service providers alike.
Designed for multi-standard networks, the 3GPP LTE and 3GPP2 1xEV-DO Turbo Decoder excels in environments requiring flexibility and advanced error correction. It features an 8 state turbo decoding system, utilizing ping-pong input and output memories for enhanced data processing and throughput. This decoder ensures consistency in data communication, a necessity for networks that support LTE and 1xEV-DO standards. It is engineered for efficient operation across different network types, supporting varied communication protocols and improving signal integrity and data correctness. Optimizing both data transfer speeds and network reliability, this decoder supports robust implementations for telecom operators, facilitating smoother transitions and reduced error rates within network infrastructure. It significantly contributes to improved user experiences and reliable data exchanges, even under heavy network demands.
Built for the Matter smart home standard, the RT583 System on Chip (SoC) merges Bluetooth Low Energy with Thread protocol, facilitating robust communication in home automation systems. With a built-in ARM Cortex M3 core, this SoC supports a versatile range of connectivity tasks while maintaining energy efficiency. The integration within a Matter framework allows for seamless interoperation between different device brands and platforms, crucial for the burgeoning home automation market. Its design prioritizes user-friendly integration while optimizing performance for connected device ecosystems.
The LightningBlu solution by Blu Wireless is an innovative track-to-train multi-gigabit solution specifically engineered for high-speed rail connectivity. This cutting-edge system ensures seamless, high-speed communication for moving trains, making it ideal for future gigabit trains. The trackside node is optimized for deployment every kilometer, serving as a bridge between wireless links to trains and a fixed trackside fiber network. Offering unparalleled efficiency, it features two-sector radios that provide continuous 3 Gbps aggregate throughput. Having been deployed across major railways such as South Western Rail and Caltrain, it has greatly enhanced connectivity and commuter experience.\n\nBlu Wireless emphasizes mobile connectivity with its mmWave solution, operating at significantly lower power levels compared to 4G or 5G, yet is capable of data speeds nearly 100 times faster than 5G. This ensures operational efficiencies, safety, and a superior passenger experience. Through consistent gigabit throughput, passengers can access substantial data volumes in real-time, a stark contrast to current capabilities offering minimal capacity. The LightningBlu represents a transformative leap in train travel connectivity by meeting contemporary data needs and establishing a groundwork for future advancements.
UWB Technology & IP offers cutting-edge ultra-wideband solutions ideal for applications requiring precise indoor positioning and short-range communication. This IP is versatile and supports integration into a variety of applications, from consumer electronics to industrial systems, providing robust data transmission capabilities with minimal interference. Thanks to its unique propagation properties, UWB is particularly well-suited for real-time location services, offering exceptional accuracy and reliability. TES's UWB IP cores are designed to be energy-efficient, making them a top choice for modern wireless communication challenges.
Saankhya Labs' 5G Remote Radio Unit is an ORAN 7.2x compliant device, designed to provide multiband support for next-generation 5G networks. This unit plays a pivotal role in facilitating advanced wireless communications by connecting cellular base stations to the core network efficiently and seamlessly. Its support for multiple frequency bands allows it to cater to diverse communication needs, making it a versatile solution for modern cellular infrastructure. This adaptability is coupled with robust performance capabilities, ensuring reliable connections across varied geographies and network conditions. Specially built to enhance network capacity and data throughput, the 5G Remote Radio Unit enhances interoperability with existing and upcoming network technologies, ensuring smooth transitions and backward compatibility. It is especially suitable for deployment in dense urban environments and underserved rural locations, aiding in bridging the communication divide.
The J1 core cell is a remarkably small and efficient audio decoder that manages Dolby Digital, AC-3, and MPEG audio decompression. With a design that occupies only 1.0 sqmm of silicon area using 0.18u CMOS technology, it delivers a robust solution for decoding 5.1 channel dolby bitstreams and supports data rates up to 640kb/s. The J1 produces high-quality stereo outputs, both normal and Pro-Logic compatible, from Dolby Digital and MPEG-encoded audio, ideal for set-top boxes and DVD applications.
The NB-IoT (LTE Cat NB1) Transceiver by Palma Ceia SemiDesign is tailored for IoT operations under Release 13 and 14 standards from 3GPP. It offers a comprehensive feature set designed for cellular IoT, providing robust and efficient connectivity by accommodating a variety of bandwidth and modulation requirements. Built with state-of-the-art RF design principles, this transceiver facilitates low power consumption while maintaining high performance. It features a well-balanced receive path and integrates seamless DC offset correction mechanisms. For enhanced interoperability, the transceiver offers various interfaces such as SPI, UART, and I2C, ensuring it can seamlessly fit into a wide range of electronic designs. Its versatility extends to the supported frequency range, covering diverse global channels. This, combined with advanced calibration and low latency, makes it ideal for mission-critical applications. Furthermore, its security and integration capabilities make it a preferred choice for developers seeking robust design and ease of implementation.
Digital Down Conversion (DDC) is essential in the realm of digital communications for effectively converting high-frequency RF signals into lower frequency signals for processing. A DDC system comprises components like a carrier selector, frequency down converter, filer, and decimator to achieve optimal conversion. This conversion process is crucial for enabling digital systems to manage and interpret incoming data efficiently, especially in complex communications networks that handle multiple signal formats simultaneously. By lowering the frequency of incoming signals, DDC technology allows for easier signal analysis, interpretation, and troubleshooting. Faststream Technologies' DDC module is crafted to support wideband signal processing applications, facilitating higher data throughput, reduced latency, and improved spectral performance. This technology is particularly significant for applications needing rapid and accurate signal decoding across various industries, ensuring timely and precise data translation and communication.
The Ceva-PentaG RAN platform offers a robust baseband processing solution for 5G infrastructure, providing the necessary components to develop open and versatile radio access networks (RAN). Ideal for macro cell base stations, small cells, and remote radio units, the platform supports scalable high-PHY/low-PHY splits. With support for enhanced 5G features like massive MIMO and beamforming, Ceva's platform ensures efficient deployment for operators transforming their infrastructure for next-generation connectivity. The inclusion of the Ceva-XC22 vector DSP core and specialized hardware accelerators helps achieve excellent power-performance area metrics.
The RF-SOI and RF-CMOS Platforms by Tower Semiconductor are designed to power the next generation of wireless communication systems, championing high-speed transmission with minimal noise disruption. These platforms offer ground-breaking low-loss RF technology solutions, perfect for applications requiring high dynamic ranges like mobile and base-station communications. The RF-SOI platform, in particular, stands out due to its enhanced switch performance, achieving new standards in efficiency and integration. This technology suite is specifically crafted for the modern demands of the wireless communication ecosystem, supporting mmWave and 5G applications which require precise signal control and propagation. The platform combines high-speed, low-noise features, ensuring exceptional signal fidelity for cutting-edge communication products. Additionally, cross-qualification across multiple Tower Semiconductor facilities ensures global supply chain security and manufacturing consistency. Empowered by a comprehensive design enablement portfolio, Tower's RF-SOI and RF-CMOS platforms facilitate accelerated market entry times and superior end-product quality for developers. These technologies are indispensable for creating innovative wireless solutions, providing the necessary tools for designers to advance their projects within this rapidly evolving industry landscape.
Designed to facilitate Bluetooth 5 Low Energy and 802.15.4 standards, the RT569 transceiver supports multiple protocol operations essential for diverse IoT networks. This IP provides cutting-edge capabilities in multi-channel communications, ensuring high levels of connectivity performance in dense wireless environments. These capabilities assure seamless interoperability across various platforms, necessary for the augmented integration of smart devices into everyday technology. Its multi-protocol support makes it a versatile choice for rapidly evolving communication landscapes like smart grids and smart cities.
Digital Pre-Distortion (DPD) is a critical component in enhancing the efficiency of RF power amplifiers, an essential part of modern telecommunications infrastructure. This technology works by mitigating signal distortion produced by power amplifiers' inherent nonlinearities, thus ensuring a clean and strong signal transmission without extensive power wastage. The process involves pre-correcting the input signals in such a way that the inevitable output distortion is effectively compensated, leading to higher efficiency and performance of RF transmitters. DPD technology is invaluable in applications that require high precision signal delivery, including wireless communications and broadcasting, where maintaining signal integrity and reducing interference is crucial. In addition to improving amplifier efficiency, DPD also leads to cost savings by reducing the energy requirements for transmitting high-quality signals. As wireless data demands escalate, technologies like DPD become increasingly important for meeting the quality standards expected by consumers and regulatory bodies alike. This technology stands as a testament to Faststream's commitment to advancing telecommunications capabilities efficiently.
AccelerComm offers a sophisticated 5G NR physical layer solution that is particularly geared for specialized applications such as O-RAN, satellite communications, and small-cell networks. This solution supports options 6 and 7.x, integrating high-performance PHY elements with AccelerComm's bespoke Low PHY. The IP is designed to balance performance, power, and scalability, enabling optimal deployment across diverse networks. The 5G NR physical layer is equipped with Acceleration IP cores that leverage innovative signal processing techniques to boost link performance. Openly licensable, this IP supports a wide array of platforms, making it adaptable for ARM-based, FPGA, and ASIC implementations. It enhances project assurance with accessible reference systems that allow thorough integration and testing on commercially available boards. AccelerComm's complete physical layer IP is dedicated to ushering in transformative power and performance improvements to 5G networks, underpinning the infrastructure with superior signal processing to meet the rising demand for high-capacity data transmission.
The 5G NR Software Stack from Lekha offers a comprehensive software suite that supports the essential functionalities of enhanced mobile broadband, ultra-reliable low latency, and massive machine-type communications. With compliance to the Release 15 specifications, this software enables network operators to accelerate deployment of 5G networks. It's developed in a modular framework, allowing compatibility with different network splits and SoC architectures, providing flexibility and scalability. The stack information is vital for OEMs, helping integrate advanced 5G capabilities seamlessly into their products. Designed for diverse applications such as public network rural broadband and private 5G networks, this stack addresses the high-capacity demands and efficiencies needed in today's dynamic connectivity environments. It is tailored to support both central and distributed unit configurations, ensuring that operators can implement next-generation networks with confidence in performance and interoperability. Through its modular nature, the 5G NR Software provides adaptability for evolving network requirements while maintaining strict adherence to international standards. This results in strong interoperability capabilities and a platform that is forward-compatible with future developments in the telecommunications sector.
Crest Factor Reduction (CFR) technology is a sophisticated signal processing technique that addresses the challenges faced by power amplifiers in handling peak power demands. By managing the peak-to-average power ratio (PAPR), CFR helps to ensure that power amplifiers operate efficiently, thus reducing the burden on power supplies and improving overall system reliability. CFR is pivotal in telecommunications, where signal spikes can cause inefficiencies or even damage to the system. This technology carefully adjusts signal peaks to manageable levels without compromising the quality of the transmitted information, thereby extending the life span of equipment while reducing operational costs. The implementation of CFR can lead to substantial cost savings associated with power efficiency and infrastructure longevity. It also enhances the ability of providers to meet regulatory and performance standards in modern communication systems, positioning the technology as a vital tool in the arsenal of those aiming to maintain top-quality service in high-demand scenarios.
The PCS1100 is a sophisticated Wi-Fi 6E RF transceiver designed by Palma Ceia SemiDesign, catering to the latest demands in connectivity. This transceiver, adhering to the IEEE 802.11ax specification, supports tri-band operations over 2.4 GHz, 5 GHz, and the newer 6 GHz band. Its design is well-suited for both Access Point (AP) and Station (STA) roles, highlighting capabilities such as MU-MIMO for enhanced simultaneous user connections. Engineered for power optimization, the PCS1100 offers superior radio frequency architecture with dual-band concurrent capabilities, allowing it to handle multiple data streams efficiently. It supports a wide range of modulations including 1024-QAM, which significantly boosts data throughput, reaching up to 4.2 Gbps. The transceiver's design focuses on reliability, boasting excellent receiver sensitivity and low phase noise, guaranteeing high-quality wireless communication over long ranges. This device is crafted with high standards, demanding strict RF performance under diverse conditions. Industries can leverage it for various applications, from smart cities to electronics requiring robust connectivity. Additionally, its integration is facilitated through simple interfaces such as SerDes and analog I/Q, enabling seamless cooperation with other chips ensuring error vector magnitude significantly exceeds standard requirements.