All IPs > Wireline Communication
Wireline Communication semiconductor IPs are critical components in the semiconductor industry, playing a vital role in enabling efficient data transmission across fixed networks. They are designed to optimize the performance of data transfer over physical media like copper cables, fiber optics, or hybrid systems. Given the growing demand for faster and more reliable data transmission, these IPs are indispensable in the development of network infrastructure and communication devices.
Products within this category cover a wide array of technologies essential for different communication protocols. For instance, Ethernet IPs are fundamental for creating network interfaces capable of high-speed data exchange, contributing to the performance of local and wide-area networks. The Fibre Channel IPs are specifically tailored for storage area networks, providing high-speed, lossless data transmission which is crucial for data-intensive applications in enterprise environments.
Additionally, this category includes Error Correction/Detection IPs, critical for maintaining data integrity during transmission by identifying and rectifying errors without needing retransmission. Our portfolio also comprises IPs for Modulation/Demodulation which play a key role in preparing data for transmission and ensuring it is correctly interpreted upon receipt. Other pivotal subcategories include ATM/Utopia, which aid in asynchronous transfer mode communications, and CEI, which contribute to high-speed chip-to-chip and board-to-board communications.
Overall, Wireline Communication semiconductor IPs facilitate the development of robust and efficient communication solutions across various industries. Whether for building telecommunication infrastructure or advancing next-generation networking devices, these IPs are central to achieving high performance, scalability, and reliability in wireline communication networks.
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
The CT25205 is a sophisticated digital controller designed for 10BASE-T1S Ethernet communications. Compatible with IEEE 802.3cg, it integrates the PMA, PCS, and PLCA Reconciliation sublayers, making it highly suitable for standard cells and FPGA systems. This synthesizable IP core supports seamless integration into any standard IEEE CSMA/CD Clause 4 Ethernet MAC via MII, which enhances its versatility for a multitude of applications. Its embedded PLCA RS uniquely allows existing MAC implementations to adopt advanced PLCA capabilities effortlessly, ensuring an increase in functionality without hardware overhauls. In conjunction with other Canova Tech IPs, such as the CT25208 MAC controller and CT25210 topology discovery IP, it provides a complete solution for implementing 10BASE-T1S within Zonal Gateways System on Chips (SoCs) and microcontrollers. The amalgamation of these components offers a streamlined approach to developing efficient network communication protocols, paving the way for innovative uses in industrial and automotive sectors where reliable data transmission is critical. This IP is especially adept at working alongside standard OPEN Alliance 10BASE-T1S PMD interfaces, reinforcing its compatibility with established industry protocols. For those developing multi-drop Ethernet solutions, the CT25205 stands as a premier choice. Its design, which ensures adherence to IEEE standards while promoting enhanced reliability and performance, makes it an attractive option for a range of applications, from simplifying connectivity in industrial setups to fortifying communications in vehicular networks, underscoring Canova Tech’s commitment to technological advancement and innovation.
This high-powered TCP Offload Engine aims to deliver superior efficiency by offloading TCP processing from the CPU. By integrating a MAC interface, it reduces processing latencies and broadens throughput, thereby optimizing network operations substantially. This IP suite maintains rapid data processing speeds and addresses a broad array of network optimization needs for today's high-demand environments. Optimized for high-speed networking environments, the TOE offers unprecedented latency reduction through its hardware-accelerated design. The integration of a refined MAC interface plays a crucial role in translating packet data into usable formats swiftly, a crucial factor in enhancing overall system performance, particularly in data-intensive industries. This technology’s edge lies in its ability to seamlessly deliver full data transfer acceleration. Its design caters to enterprises that prioritize low-processing overheads and need to maximize network efficiency without the traditional constraints of higher CPU usage. Thus, Intilop's 10G TCP Offload Engine represents a benchmark in high-performance data handling systems.
The ePHY-5616 is a high-performance SerDes solution from eTopus, designed for versatile use across enterprise, data center, and 5G applications. Operating efficiently at data rates from 1 to 56 Gbps, this product exploits advanced DSP techniques for superior signal integrity and robustness. It accommodates wide insertion loss ranges of 10dB to over 35dB, thus ensuring reliable performance in challenging communication environments. Its architecture supports direct optical drives and quad/octal configurations, making it ideal for network interface cards, routers, and high-speed switches in a data center setup. The embedded DSP architecture is developed with eTopus's proprietary algorithms, which enable rapid SerDes tuning and performance optimization. The ePHY-5616 is also characterized by its low Bit Error Rate (BER), ensuring data reliability and integrity. Moreover, it supports multiple protocols, including Ethernet and PCIe, enhancing its integration potential in modern broadband networks.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
The Ethernet Real-Time Publish-Subscribe (RTPS) Core is designed to deliver complete hardware solutions for the Ethernet RTPS protocol. It stands out by providing reliable networking capabilities needed in environments that demand stringent real-time data exchanges. This core enhances data communication efficiencies by facilitating rapid publish-subscribe interactions within complex network ecosystems. Optimized for environments that require high data throughput and consistency, it ensures that data exchanges are executed with precision and timeliness. Its architectural elegance supports seamless integration into existing networks, promoting a resilient exchange of information crucial for operational continuity. This core is pivotal for ensuring robust communication frameworks in mission-critical systems where delays and data losses are unacceptable.
The Ultra-Low Latency 10G Ethernet MAC IP core is engineered to optimize network performance by reducing latency and increasing data throughput. It provides an essential solution for applications requiring high-speed, reliable network connectivity through the use of FPGA technologies. Designed to fit efficiently within FPGA architectures, this MAC core consumes fewer resources while maintaining performance. It achieves this by offering a streamlined all-RTL solution that minimizes complexity, reliance on CPUs, and power consumption. Available in both cut-through and store-and-forward modes, this MAC allows for adaptable network configurations to suit project-specific requirements. The Ultra-Low Latency Ethernet MAC IP features advanced capabilities such as Deficit Idle Control, which optimizes throughput by controlling the inter-frame gap, ensuring smooth data streaming. The integration of a robust error-checking and correction mechanism further supports reliable, high-performance data transfer, making it ideal for demanding applications.
The ntRSC_DP1.4 IP core is compliant with Display Port 1.4 standard as published by Video Electronics Standards Association (VESA) for use in DSC (Display Stream Compression) technology. It is based on Reed-Solomon RS(254,250), 10 bit symbols, forward error correction code, where the codeword block consists of 250 information symbols and 4 RS parity symbols. The ntRSC_DP1.4 FEC IP Core ensures error resilient / glitch-free compressed video transport (DSC) to external displays. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The 10G Ethernet MAC and PCS from Chevin Technology is designed to offer high-speed Ethernet connectivity for FPGAs. This IP core maximizes throughput with low latency and fits within a compact architecture that utilizes minimal FPGA resources. It adheres to IEEE 802.3by standards, making it ideal for seamless integration in various FPGA designs, including those with a focus on ultra-fast duplex Ethernet. Chevin Technology’s 10G MAC simplifies synthesis by offering a user-friendly guide and expert support, ensuring minimal disruption to your existing design. It is compatible with both Intel and Xilinx FPGA families, and features an all-logic architecture which lowers energy consumption and reduces latency by not requiring additional CPU or software overheads. The design offers both cut-through and store-and-forward operational modes, along with a powerful CRC32 engine for error detection and correction during data transmission. Reference designs for boards such as Bittware IA-840F and Alpha Data ADM-PCIE-8V3 are available to aid in rapid deployment and integration.
The HOTLink II Product Suite is a powerful video transmission solution that enables secure and rapid data exchange for avionics applications. This suite by Great River Technology is designed to facilitate seamless high-speed digital communications, minimizing latency while enhancing the system's reliability in demanding environments. The suite encompasses a range of tools that streamline the development and deployment of HOTLink II systems, which are crucial for managing high-bandwidth data flows. It offers extensive support mechanisms through well-crafted documentation and robust simulation tools, aiding engineers in achieving optimized system performance and regulatory compliance. By leveraging the HOTLink II Product Suite, users can achieve improved data integrity and support for multiple video interfaces, ensuring the readiness of systems for various missions. This makes the suite a vital component for both military and civilian aerospace projects, offering extensive scalability and customization to suit specific operational needs.
The CT25203 serves as an analog front-end module for implementing 10BASE-T1S PHY solutions, conforming to IEEE 802.3cg standards. It is an essential component for engineers and researchers focused on creating efficient Ethernet networks within industrial and automotive ecosystems. This IP core facilitates seamless communication via standard pins, ensuring optimal interaction between the physical layer and digital control counterparts. Featuring high EMC performance, it is implemented on high-voltage process technology, underscoring its reliability for robust communication solutions. The CT25203 allows the development of devices that communicate effectively over standard OPEN Alliance TC14 interfaces, bridging connections between the MAC and PHY layers while supporting various configurations that enhance data integrity and transmission efficiency across the network. This analog front-end represents a critical building block within Canova Tech’s suite of Ethernet solutions. By enabling sturdy and efficient connections in Ethernet-based systems, it directly contributes to easing the path toward modern industrial and vehicular network implementations. Whether for facilitating data flow or ensuring system stability, the CT25203 highlights Canova Tech’s dedication to delivering high-performance IP solutions tailored to complex real-world demands.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The NaviSoC is a cutting-edge system-on-chip (SoC) that integrates a GNSS receiver and an application processor on one silicon die. Known for its high precision and reliability, it provides users with a compact and energy-efficient solution for various applications. Capable of supporting all GNSS bands and constellations, it offers fast time-to-first-fix, centimeter-level accuracy, and maintains high sensitivity even in challenging environments. The NaviSoC's flexible design allows it to be customized to meet specific user requirements, making it suitable for a wide range of applications, from location-based services to asset tracking and smart agriculture. The incorporation of a RISC-V application microcontroller, along with an array of peripherals and interfaces, introduces expanded functionality, optimizing it for advanced IoT and industrial applications. Engineered for power efficiency, the NaviSoC supports a range of supply voltages, ensuring low power consumption across its operations. The chip's design provides for efficient integration into existing systems with the support of a comprehensive SDK and IDE, allowing developers to tailor solutions to their precise needs in embedded systems and navigation infrastructures.
Time-Triggered Ethernet is a specialized communication protocol developed to incorporate the deterministic properties of traditional time-triggered systems within the robust and widely used Ethernet networking technology. It serves industries that require high precision and reliable data transmissions, like aerospace and automotive systems, where safety is paramount and timing is critical. This protocol extends conventional Ethernet by adding timestamping and scheduling features, enabling precise control over data transmission times. By doing so, it ensures that data packets are transmitted predictably within fixed timeslots, providing a network solution that combines the widespread adoption of Ethernet with high determinism demands. Time-Triggered Ethernet thus bridges the gap between standard Ethernet's flexibility and the strict timing requirements of critical systems. Applications of Time-Triggered Ethernet span from integrating advanced avionics systems to enabling reliable communication in autonomous vehicle networks. Its design supports modularity and scalability, allowing it to adapt as systems become more complex or requirements change, without sacrificing the precise timing and reliability essential for real-time communications in critical applications.
The ntLDPC_8023CA (17664,14592) IP Core is defined in IEEE 802.3ca-2020 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCE_8023CA encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer when multiplied by the 14592 payload block pro-duces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1 to 6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_8023CA decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_8023CA decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
Roa Logic's 8b/10 Decoder provides a complete implementation of the 8b10b encoding scheme formulated by Widmer and Franaszek. This decoder is essential in ensuring accurate data transmission across communication channels by performing error detection and correction functions that are critical for maintaining data integrity. The decoder efficiently identifies special comma sequences and manages the insertion and removal of these in the data stream to align data correctly. This effective error-handling feature is crucial for systems requiring reliable data integrity throughout transmission processes. Capable of maintaining high data rates while providing robust error-checking capabilities, the 8b/10 decoder module is suitable for deployment in a wide array of digital communication systems. Offering this under a non-commercial license reinforces Roa Logic's ethos of promoting open-access tools that aid in teaching and experimenting within digital design disciplines.
eTopus's ePHY-11207 stands out in their SerDes lineup by achieving data rates up to 112 Gbps, a leap forward for scenarios demanding ultra-high bandwidth and low-latency communication. Constructed on a 7nm platform, this product is tailored for state-of-the-art applications in both enterprise and advanced data center environments. The architecture of the ePHY-11207 is conducive to handling extensive insertion loss ranges and high-sensitivity demands typical of contemporary optical and copper interconnects. Its adaptability is further enhanced by embedded proprietary DSP algorithms that permit fine-tuning of performance in sub-millisecond timeframes, a feature that assures operational stability even amidst jitter-inducing environments. In addition to backing numerous protocols such as Ethernet and PCIe, the ePHY-11207's low BER and extensive diagnostic capabilities make it a prime candidate for rapid deployment in high-density network settings. Such versatility not only supports robust infrastructure but also enhances overall throughput efficiency.
EnSilica's eSi-Comms brand houses a versatile communications IP portfolio, fundamental for supporting communications-driven ASIC designs. It includes highly parameterized OFDM-based MODEM and DFE IPs, applicable to a variety of modern air interface standards such as Wi-Fi, LTE, 5G, and DVB. This IP suite integrates advanced DSP algorithms and hardware accelerators for seamless wireless communication. By employing eSi-Comms, clients can utilize proven modem architectures to develop efficient transceivers tailored to specific communications requirements, drastically reducing development time. The adaptability of these IPs to handle data across multiple antennae systems enhances wireless sensor networks and broadcast products with robust connectivity solutions.
The UDP Offload Engine is crafted to amplify data transmission by reducing CPU intervention in the data communication process. Specifically tailored for systems requiring accelerated UDP packet handling, this IP effectively boosts performance in applications needing minimized jitter and maximum throughput efficiencies without burdening the central processor. This offload engine is a critical component in environments where data flows need to be expedited, such as high-volume streaming and real-time communication applications. Its architecture supports extensive session management and high packet rates, maintaining efficiency and reliability in large-scale network deployments. By offloading UDP processes, it streamlines data pathways which, in turn, reduces computational delays, enhancing overall system dynamics. The seamless integration that the UOE offers makes it a preferred choice for organizations looking to enhance their networking stack while reducing operational costs due to its reduced dependency on traditional CPU processes.
The nxLink Network Infrastructure solution is tailored for building and managing next-generation low-latency trading networks. By employing FPGA technology, nxLink emphasizes minimizing latencies and optimizing bandwidth management, crucial for high-demand trading environments. nxLink serves network operators by providing smart processing capabilities that keep up with wire-speed performance and nanosecond-scale latency, essential for maintaining a competitive trading edge. This solution is beneficial for both the telecommunications sector and financial institutions, aiming to enhance the reliability and performance of their network infrastructures. nxLink's smart bandwidth allocation and fair usage policies ensure equitable bandwidth distribution among services and improve the existing network capacity by up to 20%. A distinctive feature of nxLink is its ability to arbitrate fiber optics and wireless links, ensuring seamless data service even under adverse conditions such as weather disruptions. This flexibility in routing data over various paths enhances link reliability without compromising latency, which is crucial for ensuring continuous and predictable network performance in volatile trading environments.
AccelerComm presents the Polar encoding and decoding suite for the 3GPP NR, featuring a comprehensive chain that enables quick integration and minimizes additional developmental efforts. This advanced IP utilizes PC and CRC-aided SCL decoding methods to deliver uncompromising error correction performance, adeptly handling the intricacies of 5G applications.\n\nThe Polar IP supports an extensive range of block sizes, tightly integrating each component to optimize performance while reducing latency and resource use. Its flexibility is further highlighted by its highly configurable parameters, which allow users to tailor its implementation to specific performance demands and power efficiency expectations.\n\nBy offering support for prevalent FPGA platforms like AMD and Intel, alongside ASIC optimizations, this Polar solution is a versatile option for developers seeking robust and integral solutions for burgeoning 5G networks. With ease of integration and superior performance metrics, it remains a leading solution in comprehensive 5G data processing.
The FC Upper Layer Protocol (ULP) Core is a sophisticated hardware implementation catering to the FC-AE-RDMA or FC-AV protocols. Designed to offer comprehensive network stack support, it includes features like hardware-based buffer mapping, DMA controllers, and message chain engines. Its pivotal role in managing high-efficiency data transactions ensures reduced latency and increased throughput, which are cardinal for applications within sensitive and precision-driven environments such as aviation and defense. The core provides a frame for constructing robust communication protocols adhering to strict industry guidelines. By integrating this IP, users can expect a significant boost in the performance of their network systems due to its efficiency in data handling and resource consumption. This core is integral to achieving seamless data operations, essential for maintaining readiness and performance in critical military operations.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
This engine features ultra-low latency FPGA IP, providing a robust TCP Offload in networking systems. The integration includes MAC, PCIe, and Host Interface, ensuring sector-leading performance with minimal latency. Built on a background of efficient data transfer protocols, the system enhances throughput while reducing CPU overhead, which is particularly advantageous for high-frequency trading or real-time applications. Characterized by its ultra-low latency capabilities, the IP facilitates enhanced data handling that allows for immediate processing, making it ideal for data-heavy environments like data centers and financial services. The integration of a MAC interface alongside PCIe provides a cohesive solution that rapidly processes network traffic, addressing both data-heavy and computationally demanding tasks. Designed for environments demanding reduced latency, this IP underscores Intilop's commitment to cutting-edge data solutions. It accommodates concurrent sessions with high-speed data throughputs, thereby minimizing the computational load on conventional processing units and achieving execution speeds that are unparalleled in the market.
InnoSilicon's 56G SerDes Solution provides a high-speed interface offering breathtaking transmission rates of up to 56Gbps per channel. Supporting both PAM-4 and NRZ modulation schemes, it adapts easily to various high-speed protocols to serve diverse applications like data center network systems and telecom infrastructure. This IP reinforces robust signal integrity and low power consumption, making it suitable for advanced ESD and BIST functionalities. Its flexible architecture meets modern network demands, ensuring future-proof customization opportunities.
The EW6181 is a cutting-edge multi-GNSS silicon solution offering the lowest power consumption and high sensitivity for exemplary accuracy across a myriad of navigation applications. This GNSS chip is adept at processing signals from numerous satellite systems including GPS L1, Glonass, BeiDou, Galileo, and several augmentation systems like SBAS. The integrated chip comprises an RF frontend, a digital baseband processor, and an ARM microcontroller dedicated to operating the firmware, allowing for flexible integration across devices needing efficient power usage. Designed with a built-in DC-DC converter and LDOs, the EW6181 silicon streamlines its bill of materials, making it perfect for battery-powered devices, providing extended operational life without compromising on performance. By incorporating patent-protected algorithms, the EW6181 achieves a remarkably compact footprint while delivering superior performance characteristics. Especially suited for dynamic applications such as action cameras and wearables, its antenna diversity capabilities ensure exceptional connectivity and positioning fidelity. Moreover, by enabling cloud functionality, the EW6181 pushes boundaries in power efficiency and accuracy, catering to connected environments where greater precision is paramount.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
The High Speed Data Bus (HSDB) core offers an integrated hardware solution, providing full MAC and PHY layer functionalities. Engineered to support complex and high-demand scenarios, this core ensures reliable data transfer, making it compatible with F-22 systems. The seamless integration with the frame interface simplifies the implementation, even within the most stringent system architectures. Engineered for robustness, HSDB provides full compliance with necessary standards, facilitating coherent data transmission across subsystems. Its adaptability and high reliability make it suitable for diverse applications, particularly where precision and high-speed data handling are pivotal. This core is preferred for its minimal system overhead and ease of deployment, which are critical to mission success. The sophistication of the HSDB core lies in its architectural design, completely optimizing it for effective operation within high-security environments. With its integrated elements, the core reduces both latency and power consumption while maintaining high throughput, thereby pushing the limits of high-speed data transfer capabilities.
The SerDes (Serializer/Deserializer) PHY offered by Terminus Circuits represents an integral component essential for various data communication technologies, where heightened bandwidth and speed are critical. This technology is crafted to accommodate diverse nodes, multiple foundries, and protocols, ensuring their solutions meet even the most demanding customer requirements. Features include low power consumption, minimal latency, and compact physical design, setting it apart for users demanding efficient SerDes technology. Terminus Circuits provides a comprehensive set of deliverables for their SerDes PHY, including user guides for integration, meticulous timing libraries, and Verilog code. This solution is adaptable to a broad spectrum of market segments, encompassing sectors like network communication, data storage, and enterprise networking, thanks to its seamless interoperability with existing controllers. With the ability to support diverse protocols such as PCI Express, USB 3.1, and various optical interfaces, the SerDes PHY provides an essential backbone for robust high-speed data exchange. The SerDes PHY is particularly noted for its capacity to handle conventional as well as emerging networking and storage protocols, with configurations that support variations across different data rates and standards. Such versatility in supporting bifurcation modes and progressive equalization techniques ensures optimal signal integrity and minimized data latency, catering to sophisticated applications requiring high-speed, reliable data transfer.
The Tyr Superchip is engineered to tackle the most daunting computational challenges in edge AI, autonomous driving, and decentralized AIoT applications. It merges AI and DSP functionalities into a single, unified processing unit capable of real-time data management and processing. This all-encompassing chip solution handles vast amounts of sensor data necessary for complete autonomous driving and supports rapid AI computing at the edge. One of the key challenges it addresses is providing massive compute power combined with low-latency outputs, achieving what traditional architectures cannot in terms of energy efficiency and speed. Tyr chips are surrounded by robust safety protocols, being ISO26262 and ASIL-D ready, making them ideally suited for the critical standards required in automotive systems. Designed with high programmability, the Tyr Superchip accommodates the fast-evolving needs of AI algorithms and supports modern software-defined vehicles. Its low power consumption, under 50W for higher-end tasks, paired with a small silicon footprint, ensures it meets eco-friendly demands while staying cost-effective. VSORA’s Superchip is a testament to their innovative prowess, promising unmatched efficiency in processing real-time data streams. By providing both power and processing agility, it effectively supports the future of mobility and AI-driven automation, reinforcing VSORA’s position as a forward-thinking leader in semiconductor technology.
The FC Anonymous Subscriber Messaging (ASM) Core serves as a full hardware implementation for the FC-AE-ASM protocol, optimizing network stack components through integrated label lookups, DMA controllers, and message chain engines. This IP core offers a sophisticated and reliable solution for military and aerospace communication systems. Intensely capable within high-demand environments, the ASM Core ensures secure and efficient processing of data streams, critical for time-sensitive deployments like those involving F-35 type interfaces. The dedication to high-speed data management and robust control systems sets a high operational standard. Delivering enhanced data throughput and streamlined handling, the core minimizes delays and maximizes operational uptime. It is indispensable for complex mission-critical scenarios demanding resilience and swift communication without compromising efficiency.
The Flexibilis Redundant Switch (FRS) is a versatile and high-speed Ethernet Layer-2 switch IP core capable of implementing the High-availability Seamless Redundancy (HSR) and the Parallel Redundancy Protocol (PRP) across a network. This core offers triple-speed operation (10Mbps/100Mbps/1Gbps), facilitating seamless communication for mission-critical systems. FRS is uniquely designed to work in FPGA environments, providing from three to eight Ethernet ports to match various networking requirements. One key feature is its IEEE1588v2 PTP transparent clock support, which ensures precision timing and synchronization across the network for applications that cannot afford time discrepancies. Its architecture supports HSR and PRP without the need for separate RedBox implementations, integrating redundancy directly into the networked devices. The switch supports full-duplex operation and wire-speed Ethernet packet forwarding, making it a top choice for applications demanding redundancy, such as smart grid and industrial automation.
Secure Protocol Engines are designed to significantly enhance network and security processing capabilities. This IP offers high-performance processing of network traffic with secure protocol applications. It includes efficient engines for SSL/TLS handshakes and algorithms such as MACsec and IPsec, enabling swift encryption and decryption, thus enhancing security for data centers and similar infrastructures. These engines help in offloading intensive cryptographic operations from CPUs, thereby optimizing performance and resource allocation.
The 100G Transponder CAUI-10 facilitates seamless optical-to-electrical signal conversion, doubling as an efficient intermediary in high-capacity network systems. These transponders are invaluable for telecommunications setups that demand high data rates and extended reach, providing the necessary tools to manage complex digital signal demands.
Designed for advanced network diagnostics, the 10G Universal Network Probe enables comprehensive traffic monitoring and analysis across OTN and other high-capacity networks. This probe offers versatile compatibility, ensuring streamlined integration into existing infrastructure, a critical function for maintaining high-speed data transmission fidelity and efficiency.
APIX3 represents Inova's third generation of high-speed data link technology, significantly improving the capabilities over previous APIX versions. Designed to meet the demanding requirements of modern vehicle infotainment and cockpit architectures, APIX3 supports data rates of up to 6 Gbps over a single shielded twisted pair cable and up to 12 Gbps using quad twisted pairs. This enhances the functionality of automotive displays, allowing multiple ultra-high-definition video channels to be transmitted over a single connection. The technology is backward compatible with APIX2, allowing integration into a range of automotive networking setups without needing extensive reconfiguration. APIX3 features advancements such as improved diagnostic tools for monitoring cable integrity and longevity, as well as built-in compensation mechanisms for cable age and temperature variations. APIX3 technology not only facilitates advanced multimedia transmission within vehicles but also ensures robust and reliable data exchange, fundamental for next-generation infotainment systems. With added Ethernet channels and wide-ranging interface support, Inova's APIX3 offers a versatile communication solution for real-time data processing, ensuring seamless connectivity across different in-car systems.
ASPER is a 79 GHz short-range radar sensor designed to exceed the capabilities of traditional ultrasonic parking assist technologies. With a 180-degree field of view, ASPER provides unparalleled coverage with a single module. This ensures that vehicles ranging from passenger cars to AGVs benefit from complete side coverage without blind spots. The sensor's ability to detect low-lying objects like curbs enhances safety and situational awareness for drivers across a variety of contexts. ASPER integrates seamlessly into vehicle systems, allowing for effective monitoring of front, rear, and side zones for enhanced collision avoidance and traffic awareness. Its robust design optimizes it for urban blind spot detection, providing critical alerts to drivers regarding potential hazards. This technology is crucial for improving both safety and driver confidence in busy urban environments. Designed for scalability, the ASPER radar sensor can be employed in a variety of vehicles, including motorcycles and larger transportation vehicles. Its adaptability ensures comprehensive monitoring, contributing to more effective navigation and obstacle avoidance in all weather conditions. With edge-processing technology, ASPER boasts a host of features that maximize performance while maintaining affordability.
Nextera's NMOS control software stands as a pivotal solution for achieving multi-vendor IP network interoperability with SMPTE ST 2110-based systems. Developed in conjunction with the Advanced Media Workflow Association (AMWA) and the Joint Taskforce on Networked Media (JT-NM), it provides plug-and-play simplicity for AV over IP environments. Key NMOS specifications include IS-04 for discovery and registration, IS-05 for connection management, and IS-08 for audio channel mapping, all essential for achieving seamless network integration. It facilitates the easy integration and operation of varied devices by ensuring compliance with European Broadcaster Union's minimum IP media requirements. With a focus on enhancing flexibility and control within media environments, this platform enables efficient media flow management, assuring users of a secure, reliable, and interoperable AV experience.
The VIDIO 12G SDI FMC Daughter Card is engineered to facilitate next-level broadcast video applications. Equipped with 12G SDI and 10G IP interfaces, this card supports 4K resolution at 60 frames per second, making it compatible with various AMD and Intel development boards. Manufactured with the latest chip technology, the card utilizes a single board design, incorporating full-size edge launch BNCs along with an SFP+ cage. This enables developers to integrate additional SFP-BNC inputs and outputs, extending versatility in signal configurations. The card is thoroughly tested for quality, fulfilling requirements for jitter performance over extended cable runs, ensuring signal reliability in demanding broadcast environments. With a focus on ease of use, it requires no software for initialization, making it ready-to-use for rapid deployment.
The BlueLynx Chiplet Interconnect facilitates seamless communication between chiplets, vital for modern semiconductor designs that emphasize modularity and efficiency. This technology supports both physical and link layer interfaces, adhering to the Universal Chiplet Interconnect Express (UCIe) and Open Compute Project (OCP) Bunch of Wires (BoW) standards. BlueLynx ensures high-speed data transfer, offering customizable options to tailor designs for specific workloads and application needs. Optimized for AI, high-performance computing, and mobile markets, BlueLynx's die-to-die adaptability provides system architects with the leeway to integrate a variety of packaging types and process nodes, including 2D, advanced 2.5D, and innovative 3D packaging options. The solution is recognized for delivering a balance of bandwidth, energy efficiency, and latency, ensuring robust system performance while minimizing power consumption. This IP has been silicon-proven across multiple process nodes, including advanced technologies like 3nm, 4nm, and 5nm, and is supported by major semiconductor foundries. It offers valuable features such as low latency, improved PPA (Power, Performance, Area), and industry-standard compliance, positioning it as a reliable and high-performing interconnect solution within the semiconductor industry.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The TimeServoPTP expands on the capabilities of the TimeServo by offering a fully compliant IEEE 1588v2 Precision Time Protocol (PTP) ordinary clock implementation. Specifically designed as an FPGA component, it supports both 1-step and 2-step synchronization processes, ensuring cohesive operation in synchronization tasks involving network time grandmasters. With capabilities that include up to 32 'time now' outputs with clock domain crossing logic, TimeServoPTP is engineered for applications where maintaining coherent time is crucial. This is especially beneficial in scenarios requiring precise timekeeping over Ethernet using PTP/1588 EtherType frames. The internal Gardner Type-2 DPLL further adds to its high precision in synchronization tasks. The solution is straightforward to implement, functioning independently from host processors post-initialization. Compatible with Intel and Xilinx FPGA devices, TimeServoPTP is an ideal choice for applications in autonomous synchronization where minimal host interaction is preferred, and is well-suited for both complex and standard timekeeping challenges in network infrastructure.
The DVB-S2-LDPC-BCH system provides a formidable forward error correction platform crucial for satellite communication. Utilizing LDPC coupled with BCH codes, this IP ensures quasi-error-free operation, pushing system performance near the Shannon limit. Compliant with ETSI standards, it offers robust error correction capabilities with varied throughput rates, facilitated by its synthesizable Verilog model, making it adaptable for ASIC implementations.
InfiniBand Transport Layer Cores are integral components for high-performance computing, data acquisition, and networking scenarios, aimed at enhancing data management and reducing latency in transport operations. These cores are specially designed to function at optimal speeds and support crucial operations like UC SEND and UC RDMA Write across varied volumes and applications. The Transport Layer Cores from Polybus are equipped to handle a range of data processes involving up to eight virtual lanes and 1024 Queue Pairs, reflecting exceptional versatility. The design of these cores ensures minimal latency and high throughput, meeting the demands of modern networking environments and computational resource management. By combining these cores with Link Layer elements, Polybus provides a comprehensive, high-speed solution for channel adapter applications. Beyond standard functionalities, Polybus offers customization, ensuring the Transport Layer Cores cater specifically to project requirements. This bespoke approach reinforces Polybus's role in fostering technological advancements through top-tier products that can seamlessly integrate into high-demand computing environments.
The JPEG Encoder for Image Compression is designed to deliver efficient lossy compression for various imaging applications. This encoder is compliant with the Baseline JPEG standard (ITU T.81), ensuring a balance between compression efficiency and image quality. It supports pixel depths of up to 12 bits, although 8 bits is the default setting. The encoder provides super low latency, making it ideal for rolling shutter cameras, and is available in multiple configurations to suit different application needs. This encoder is particularly adaptable for multimedia applications requiring high-speed processing, including motion JPEG, thanks to its dual-pipe design that allows simultaneous encoding for formats like YUV422. This setup supports resolutions such as 1280x720 at 60 fps with a pixel clock of 100 MHz, although platform-specific optimizations can increase speed. The encoder operates without external RAM, relying only on FPGA and Ethernet PHY, which not only reduces power consumption but also simplifies hardware requirements. Additionally, the JPEG Encoder is verified extensively against standard compliance through detailed simulation models that ensure both bit and cycle accuracy. The encoder can be implemented in various SoCs and integrates smoothly with existing systems, thanks to its adaptable architecture that supports various network streaming standards and embedded applications.
The Advanced Flexibilis Ethernet Controller (AFEC) is an advanced IP block tailored for both FPGA and ASIC implementations, offering comprehensive Ethernet Interface solutions for networking needs. Designed for triple-speed operation (10Mbps/100Mbps/1Gbps), AFEC enhances Ethernet device communication with robust capabilities. AFEC seamlessly connects to Ethernet PHY devices through standard interfaces like MII and GMII while supporting both copper and fiber Ethernet networks. This ensures a versatile application range across devices and networking setups. It includes a dedicated DMA controller for RX and TX data handling to ease CPU processing loads, allowing less powerful processors to achieve maximum data throughput. Supporting the IEEE1588 Precision Time Protocol, AFEC allows for precise time stamping of all transmitted and received frames, vital for applications where accurate time logging is crucial. Its flexible interrupt management and configuration options make it a highly adaptable controller for complex Ethernet setups seeking enhanced performance and synchronization capabilities.
The PCD03D Turbo Decoder is adept at handling multiple state decoding for standards such as DVB-RCS and IEEE 802.16 WiMAX. Its core design features an 8-state duobinary decoding structure, facilitating precise and quick signal deconstruction. Additionally, the optional inclusion of a 64-state Viterbi decoder enhances versatility and performance in various environments. This decoder is tailored for applications where agility and high data throughput are critical, making it an invaluable asset in wireless communication infrastructures. The decoder’s architecture supports expansive VHDL core integration, providing durable solutions across FPGA platforms.
The HOTLink II core delivers a comprehensive layer 2 hardware implementation tailored for High-Speed Interface (HSI) applications. This core facilitates easy integration through its adept frame interface, supporting full-rate, half-rate, and quarter-rate operations, adhering strictly to established standards. Its design is tailored to seamlessly fit within the F-18 compatible interfaces. Strategically developed for efficiency, it allows precise control processes at the data link layer, reducing latency and optimizing transmission speed. Whether integrated into aerospace systems or complex defense architectures, HOTLink II ensures high-speed, error-free communications crucial for mission-critical scenarios. This solution provides essential functionalities that bolster data exchange in sophisticated environments by minimizing the risk factors inherent in high-velocity data transmissions. With its ability to maintain consistent performance across various rates, HOTLink II stands as a critical solution for modern high-frequency connectivity challenges.
The LDPC solution by AccelerComm is meticulously optimized for the 5G NR standard, ensuring superior efficiency and performance. This encoder and decoder IP triumphantly addresses the pivotal needs of the 5G network by combining maximal hardware efficiency with enhanced power efficiency. It is adeptly designed to fulfill the rigorous throughput and error correction targets outlined by 3GPP standards.\n\nIntended for integration into both FPGA and ASIC environments, the LDPC IP is highly configurable, providing numerous settings to cater to a broad array of applications. Its capability to support maximum data rates while minimizing latency makes it an indispensable element in advanced communication infrastructures.\n\nWith enhanced BLER performance and an innovative design that outstrips generic LDPC solutions, this implementation significantly reduces latency and resource utilization. Offering low power consumption and half the energy per bit compared to competitors, it provides a balanced approach to meeting both diverse operational demands and stringent power budgets.
The RWM6050 baseband modem from Blu Wireless underpins their mmWave solutions, providing a powerful platform for high-bandwidth, multi-gigabit connectivity. Co-developed with Renesas, this modem pairs seamlessly with mmWave RF chipsets to offer a configurable radio interface, capable of scaling data across sectors requiring both access and backhaul services. This modem features flexible channelization and modulation coding schemes, enabling it to handle diverse data transmission needs with remarkable efficacy. Integrated dual modems and a mixed-signal front-end allow for robust performance in varying deployment scenarios. The RWM6050 supports multiple frequency bands, and its modulation capabilities enable it to adapt dynamically to optimize throughput under different operational conditions. The modem includes advanced beamforming support and digital front-end processing, which facilitates enhanced data routing and network synchronization. These features are pivotal for managing shifting network loads and ensuring resilient performance amidst irregular traffic and environmental variances. A real-time scheduler further augments its capabilities, enabling dynamic response to complex connectivity challenges faced in modern communication landscapes.
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