All IPs > Wireline Communication
Wireline Communication semiconductor IPs are critical components in the semiconductor industry, playing a vital role in enabling efficient data transmission across fixed networks. They are designed to optimize the performance of data transfer over physical media like copper cables, fiber optics, or hybrid systems. Given the growing demand for faster and more reliable data transmission, these IPs are indispensable in the development of network infrastructure and communication devices.
Products within this category cover a wide array of technologies essential for different communication protocols. For instance, Ethernet IPs are fundamental for creating network interfaces capable of high-speed data exchange, contributing to the performance of local and wide-area networks. The Fibre Channel IPs are specifically tailored for storage area networks, providing high-speed, lossless data transmission which is crucial for data-intensive applications in enterprise environments.
Additionally, this category includes Error Correction/Detection IPs, critical for maintaining data integrity during transmission by identifying and rectifying errors without needing retransmission. Our portfolio also comprises IPs for Modulation/Demodulation which play a key role in preparing data for transmission and ensuring it is correctly interpreted upon receipt. Other pivotal subcategories include ATM/Utopia, which aid in asynchronous transfer mode communications, and CEI, which contribute to high-speed chip-to-chip and board-to-board communications.
Overall, Wireline Communication semiconductor IPs facilitate the development of robust and efficient communication solutions across various industries. Whether for building telecommunication infrastructure or advancing next-generation networking devices, these IPs are central to achieving high performance, scalability, and reliability in wireline communication networks.
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
WAVE6 represents the pinnacle of multi-standard video coding. It supports AV1 encoding, known for its efficient use of bandwidth and high compression quality. Featuring a simple architecture, it boasts a single-clock domain that synchronizes the entropy and video codec engines on the fly. The efficiency of WAVE6 is further enhanced by its power-efficient design, which minimizes consumer energy requirements through effective clock gating. It serves various sectors, including data centers and surveillance systems, operating with a remarkable performance of up to 8K60fps @ 1GHz. The integration of advanced coding techniques ensures a reduced need for external memory, thanks to the proprietary CFrame lossless compression.
Chevin Technology's Ultra-Low Latency 10G Ethernet MAC is engineered to meet the demanding performance needs of modern telecommunications environments. This IP core optimizes data processing speed with its cutting-edge design, ensuring minimal latency and consistent data throughput. The Ultra-Low Latency 10G Ethernet MAC is particularly suited for real-time data exchange applications where swift data transmission is essential. It leverages a compact logic structure to achieve outstanding efficiency, minimizing resource requirements while bolstering performance capabilities. The core's versatile design supports straightforward integration into both new and existing systems across various FPGA platforms. It stands out for its energy-efficient operation, offering sizeable power savings over CPU-based implementations, and provides a robust licensing model to offer cost flexibility for developers.
The CT25205 Digital IP core is engineered to provide the core building blocks for 10BASE-T1S Ethernet applications, including PMA, PCS, and PLCA Reconciliation Sublayer adherence. Written in Verilog 2005 HDL, it is fully synthesizable with standard cells and FPGA, working cohesively with standard IEEE CSMA/CD Ethernet MAC via MII. The unit supports advanced PLCA features, enabling seamless communication with existing MAC devices. Connectivity is ensured through a standard OPEN Alliance 10BASE-T1S PMD Interface, creating an optimal solution for Zonal Gateway SoCs and MCUs adopting innovative 10BASE-T1S communication.
The NaviSoC, a flagship product of ChipCraft, combines a GNSS receiver with an on-chip application processor, providing an all-in-one solution for high-precision navigation and timing applications. This product is designed to meet the rigorous demands of industries such as automotive, UAVs, and smart agriculture. One of its standout features is the ability to support all major global navigation satellite systems, offering versatile functionality for various professional uses. The NaviSoC is tailored for high efficiency, delivering performance that incorporates low power consumption with robust computational capabilities. Specifically tailored for next-generation applications, NaviSoC offers flexibility through its ability to be adapted for different tasks, making it a preferred choice for many industries. It integrates seamlessly into systems requiring precision and reliability, providing developers with a wide array of programmable peripherals and interfaces. The foundational design ethos of the NaviSoC revolves around minimizing power usage while ensuring high precision and accuracy, making it an ideal component for battery-powered and portable devices. Additionally, ChipCraft provides integrated software development tools and navigation firmware, ensuring that clients can capitalize on fast time-to-market for their products. The design of the NaviSoC takes a comprehensive approach, factoring in real-world application requirements such as temperature variation and environmental challenges, thus providing a resilient and adaptable product for diverse uses.
Silicon Library provides the LVDS/OpenLDI solution to cater to the needs of systems requiring reliable data communication. LVDS, or Low Voltage Differential Signaling, is a standardized method for transmitting high-speed digital data with minimum power consumption and radiation. This technology is utilized in a broad range of applications like LCD screens and point-to-point links because of its fast data transmission capabilities and ability to support significant distances without compromising signal integrity. The OpenLDI variant extends these benefits further, supporting broader implementation such as industrial and consumer displays. With power-efficient designs, this LVDS/OpenLDI IP ensures enhanced performance with minimal power usage. Its design facilitates integration into systems where compact form factors and robust performance are vital, making it a staple in many high-performance display environments and communications systems.
The V-By-One HS technology from Silicon Library is aimed at providing a robust solution for high-speed video signal transmission over extended distances. It is used primarily in display technologies where the need for high data rates and minimal cabling is essential. V-By-One HS supports ultra-high-definition video and is designed to reduce the complexity of cabling in large displays and panels, making it a preferred choice in industries that manufacture televisions and digital signage displays. This technology enhances the quality of video signaling by ensuring smooth and uninterrupted data flow, which is vital for premium screen displays. The compact design of V-By-One HS lowers the overall system cost and footprint, while also cutting down on power consumption, essential for meeting the latest environmental and performance standards. This makes it an ideal solution for advanced display technologies requiring efficient data transmission with minimal hardware.
Intilopās UDP Offload Engine (UOE) is engineered to process UDP packets efficiently, reducing CPU overhead and improving data transfer speeds. This ultra-low latency engine is crucial for applications where rapid data transmission is key, such as multimedia streaming, VoIP, and real-time gaming. The UOE provides robust functionality with its capability of supporting high-throughput processing and multiple concurrent sessions, which is vital for maintaining quality service in data-heavy environments. Its integration into networking systems ensures minimal latency while maximizing data integrity and reliability. Leveraging the UOE contributes to significant performance improvements in network devices, allowing for the handling of vast data volumes without compromising speed or reliability. This IP exemplifies Intilopās commitment to delivering superior networking solutions that meet modern demands for speed and efficiency.
The 100G Transponder CAUI-10 facilitates seamless optical-to-electrical signal conversion, doubling as an efficient intermediary in high-capacity network systems. These transponders are invaluable for telecommunications setups that demand high data rates and extended reach, providing the necessary tools to manage complex digital signal demands.
The 10G Ethernet MAC and PCS from Chevin Technology is designed to deliver exceptional network performance for FPGA systems. This IP core boasts high throughput and low latency, ensuring efficient data transmission capabilities. Tailored for flexibility, it can integrate seamlessly into a variety of systems, providing reliability and reduced hardware complexity through its all-logic architecture. Offering compatibility with both Intel and Xilinx FPGAs, the core is intended for high-efficiency applications, making it suitable for use in environments where space and power consumption are critical factors. With its support for the latest Ethernet standards, it enhances network communication within embedded systems. Engineered for design efficiency, this MAC and PCS IP can lower system costs and footprint by fitting numerous cores on a single chip. By maximizing space for other logic components, it provides a cost-effective solution without compromising on performance.
The CT25203 is a component of Canova Tech's comprehensive IP offering, designed for facilitating the development of PMD transceivers compliant with the OA TC14 specification. It interacts efficiently with host MCUs, Zonal Gateway Controllers, or Ethernet switches, delivering robust performance for 10BASE-T1S digital PHY applications. The transceiver's high-voltage process technology enhances EMC performance, with an 8-pin package optimized for compact and efficient design, tailored for automotive and industrial communication requirements.
The eSi-Comms solution provides a highly parameterisable and configurable suite for communication ASIC designs. This comprehensive collection includes OFDM-based modem and DFE IPs supporting a vast array of contemporary air interface standards such as 4G, 5G, Wi-Fi, and DVB among others. It offers robust and efficient solutions for modulation, equalization, and error correction using advanced digital signal processing algorithms. With its capabilities specific to synchronization and demodulation across multiple standards, it equips systems for optimal data flow management. The adaptable DFE features support precision in digital frequency conversion and other enhancements, fortifying both the transmitting and receiving ends of communication systems. This IP empowers wireless sensors, remote metering, and cellular devices, ensuring seamless integration into a diverse range of communication applications.
Building on its predecessor, the WAVE5 series offers robust multi-standard video encoding capabilities with an established reputation within media and entertainment sectors. WAVE5 is versatile, boasting formats like HEVC and AVC, and delivers outstanding performance, with outputs like 4K240fps at 1GHz. It has been fine-tuned to handle complex multi-instance operations by efficiently managing data transfer and conversion tasks. Its ability to maintain high visual fidelity while offering low installation costs makes it a strategic choice for multiple application fields such as automotive and mobile entertainment. The use of secondary AXI ports and a fully integrated rotation and scaling mechanic add to its versatility.
The 10G TCP Offload Engine (TOE) by Intilop is meticulously engineered to offer high-speed TCP processing, reducing the computational burden on host CPUs. This ultra-low latency solution integrates seamlessly into network infrastructure, significantly improving data throughput and system performance. With robust design architecture, the TOE facilitates complete offloading of the TCP stack, allowing for enhanced speed and reduced jitter in data transactions. This makes the component ideal for applications demanding high-frequency data exchanges, such as financial trading platforms and high-performance computing systems. Additionally, the IP guarantees consistent performance across multiple sessions, supporting extensive concurrent connections without loss of speed or reliability. The design priorities robust security and data integrity, ensuring that systems utilizing this engine can achieve greater network efficiency and reliability.
The ePHY-5616 product is crafted to handle data rates from 1 to 56Gbps. Operating prominently on 16 and 12nm technology nodes, this solution is ideal for applications that demand scalable insertion loss and data rate adaptability. The architecture is robust, leveraging advanced DSP techniques to provide exceptional clock data recovery and superior BER (Bit Error Rate), catering to both enterprise and data center needs. Its utility extends to routers, switches, and other critical data infrastructure components.
The HOTLink II Product Suite from Great River Technology is tailored for high-speed data transmission in demanding aerospace environments. This solution integrates seamlessly into avionics systems, providing robust performance for data-intensive applications. Known for its efficiency and reliability, the HOTLink II suite is ideal for organizations requiring consistent and high-speed data transfer capabilities. Designed for maximum compatibility, the HOTLink II suite supports various hardware configurations and software interfaces, ensuring smooth transitions between system components. The suite offers a comprehensive array of tools that facilitate the integration and management of high-speed data links within sophisticated avionics architectures. Whether in development or deployment, the HOTLink II suite provides unparalleled support and flexibility. In addition to its core functionalities, the HOTLink II suite assists in optimizing data integrity and system robustness throughout the system's lifecycle. Its design reflects Great River Technology's expertise in data solutions, promising long-term reliability and performance in mission-critical applications.
Secure Protocol Engines by Secure-IC are designed to offload network and security processing tasks in high-performance computing environments. These engines provide specialized IP blocks that can handle complex cryptographic protocols efficiently. The solution optimizes system performance by allowing primary processors to focus on core functionalities while the protocol engines manage the security operations. This capability is crucial for systems requiring robust security without compromising on speed or efficiency, such as in telecommunication or data center applications.
This Ethernet Chiplet by YorChip is engineered to meet the high-performance networking needs of modern data-centric applications. With capabilities of supporting up to 400G Ethernet, it is primed for deployment in data centers and high-speed networking equipment. The design focuses on offering maximum bandwidth and low latency, catering to the robust data exchanges typical in these environments. A key feature of this chiplet is its ability to integrate with existing chiplet ecosystems, ensuring compatibility and ease of integration for manufacturers looking to upgrade their systems. The focus on low power consumption in its design highlights its suitability for large-scale deployment where energy efficiency is paramount. The chiplet also assures adaptability across numerous platforms with varied process node compatibilities, showing its versatility and robustness in multiple fabrication contexts. Its implementation can significantly enhance network throughput and reliability, ensuring efficient handling of large data volumes typical of sophisticated network architectures.
The Titanium Ti375 FPGA from Efinix boasts a high-density, low-power configuration, ideal for numerous advanced computing applications. Built on the well-regarded Quantum compute fabric, this FPGA integrates a robust set of features including a hardened RISC-V block, SerDes transceiver, and LPDDR4 DRAM controller, enhancing its versatility in challenging environments. The Ti375 model is designed with an intuitive I/O interface, allowing seamless communication and data handling. Its innovative architecture ensures minimal power consumption without compromising on processing speed, making it highly suitable for portable and edge devices. The inclusion of MIPI D-PHY further expands its applications in image processing and high-speed data transmission tasks. This FPGA is aligned with current market demands, emphasizing efficiency and scalability. Its architecture allows for diverse design challenges, supporting applications that transcend traditional boundaries. Efinixās commitment to delivering sophisticated yet energy-efficient solutions is embodied in the Titanium Ti375, enabling new possibilities in the realm of computing.
The RWM6050 baseband modem by Blu Wireless represents a highly efficient advancement in mmWave technology, offering an economical and energy-saving option for high bandwidth and capacity applications. Developed alongside Renesas, the modem is configured to work with mmWave RF chipsets to deliver scalable multi-gigabit throughput across access and backhaul networks. This modem is ideal for applications requiring substantial data transfer across several hundred meters.\n\nThe RWM6050 leverages flexible channelization and advanced modulation support to enhance data rates with dual modems and integrated mixed-signal front-end processing. This ensures that the modem can effectively handle diverse use cases with varying bandwidth demands. Its versatile subsystems, including PHY, MAC, ADC/DAC, and beamforming, facilitate adaptive solutions for complex networking environments.\n\nA standout feature of the RWM6050 is its integrated network synchronization, ensuring high precision in data delivery. Designed to meet the futuristic needs of communication networks, it helps end-users achieve superior performance through its programmable real-time scheduler and digital front-end processing. Additionally, the modem's highly digital design supports robust, secure connections needed for next-generation connectivity solutions.
TimeServoPTP extends the capabilities of the TimeServo System Timer to provide a complete IEEE 1588v2 Precision Time Protocol (PTP) Ordinary Clock (OC) solution for FPGAs. This implementation supports both 1-Step and 2-Step synchronization with a network time grandmaster, ensuring accurate time alignment within a communication system. The IP is designed to interface directly with a PTP master through Ethernet, utilizing L2 EtherType frames for communication. It features flexible clocking options and independent time output domains, providing up to 32 precise timing outputs. Each output can be individually configured in various formats and includes a pulse-per-second signal for precise timing applications. TimeServoPTP employs a Gardner Type-2 digital phase-locked loop (DPLL) to maintain synchronization accuracy, leveraging FPGA resources efficiently. This solution supports Intel Agilex and Xilinx UltraScalePlus devices, demonstrating its adaptability across different hardware platforms.
The D2200 is a high-performance PCIe SSD designed by Swissbit for enterprise and data center applications. It combines exceptional data speeds with low power consumption to enhance system performance. This SSD is equipped with state-of-the-art NAND technology, ensuring sustained performance even under intense workloads. The D2200's design prioritizes temperature and performance management, making it resilient against environmental extremes and suitable for mission-critical applications.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCĪ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layersā LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
Enyxās nxLink is a forward-thinking network management suite tailored for constructing low-latency, high-efficiency trading environments. Leveraging FPGA technology, nxLink enhances network capabilities by enabling advanced link management and bandwidth distribution, critical for the infrastructure of financial firms and telecommunication sectors. The product suite is designed to tackle common networking challenges like latency, signal reliability, and bandwidth inefficiency, offering solutions that ensure minimal data loss and enhanced transmission stability by integrating wireless links with fiber backups. nxLinkās Share and Secure modules provide bandwidth management and redundancy handling, safeguarding network operations from outages or performance dips. Built for next-generation trading networks, nxLink supports features such as Ethernet fragmentation, link redundancy, and packet arbitration, thus boosting network performance and maintaining wire-speed processing. This adaptable network solution is well-suited for organizations keen on optimizing their communication infrastructures for rapid, stable data exchanges across multiple sites.
The Reed Solomon Error Correcting Code ECC targets environments where error minimization during high-speed data processing is paramount. Its design capitalizes on a zero-latency, asynchronous processing model that negates the need for clocks and iterative data storage, using basic combinatorial logic to streamline error correction. This error correction code stands out due to its adjustable parameters, including the symbol size and the count of correctable error symbols, enabling operators to modify the code for optimal performance based on specific requirements. This flexibility extends to its coding structure, which uses minimal clock cycles for execution, thus fast-tracking error detection and recovery processes. It is ideally suited for an array of applications such as digital storage systems, communication networks, and wherever data robustness is critically assessed. The IPās reliability is further enhanced through a verified and lint-clean RTL, tailored to meet diverse error correction needs efficiently and effectively.
The Trion FPGA family by Efinix addresses the dynamic needs of edge computing and IoT applications. These devices range from 4K to 120K logic elements, balancing computational capability with efficient power usage for a wide range of general-purpose applications. Trion FPGAs are designed to empower edge devices with rapid processing capabilities and flexible interfacing. They support a diverse array of use-cases, from industrial automation systems to consumable electronics requiring enhanced connectivity and real-time data processing. Offering a pragmatic solution for designers, Trion FPGAs integrate seamlessly into existing systems, facilitating swift development and deployment. They provide unparalleled adaptability to meet the intricate demands of modern technological environments, thereby enabling innovative edge and IoT solutions to flourish.
Dream Chip Technologies' Arria 10 System on Module (SoM) emphasizes embedded and automotive vision applications. Utilizing Altera's Arria 10 SoC Devices, the SoM is compact yet packed with powerful capabilities. It features a dual-core Cortex A9 CPU and supports up to 480 KLEs of FPGA logic elements, providing ample space for customization and processing tasks. The module integrates robust power management features to ensure efficient energy usage, with interfaces for DDR4 memory, PCIe Gen3, Ethernet, and 12G SDI among others, housed in a form factor measuring just 8 cm by 6.5 cm. Engineered to support high-speed data processing, the Arria 10 SoM includes dual DDR4 memory interfaces and 12 transceivers at 12 Gbit/s and above. It provides comprehensive connectivity options, including two USB ports, Gigabit Ethernet, and multiple GPIOs with level-shifting capabilities. This level of integration makes it optimal for developing solutions for automotive systems, particularly in scenarios requiring high-speed data and image processing. Additionally, the SoM comes with a suite of reference designs, such as the Intel Arria 10 Golden System Reference Design, to expedite development cycles. This includes pre-configured HPS and memory controller IP, as well as customized U-Boot and Angstrƶm Linux distributions, further enriching its utility in automotive and embedded domains.
The Ethernet Real-Time Publish-Subscribe (RTPS) core provides a comprehensive hardware solution for implementing the Ethernet RTPS protocol, crucial for applications that require deterministic data transfer with minimal latency. Ideal for real-time environments, this core enhances system performance by ensuring reliable data synchronization and fast publish-subscribe mechanisms, crucial in mission-critical operations. The core's design prioritizes streamlined data exchange processes, which improve system efficiency and reliability. Its robust framework is well-suited to applications needing high-speed online data exchanges, paired with enhanced system communication architecture that ensures effective bandwidth management without compromising data integrity.
The FC Anonymous Subscriber Messaging (ASM) IP core provides an advanced full-network stack, adeptly handling the FC-AE-ASM protocol for secure, high-speed communication. Built for military applications, it offers hardware-enabled label lookups, DMA control, and efficient message chain processing. Particularly suitable for environments requiring utmost data security, this core supports critical military-grade systems, including F-35 interfaces, reflecting its capability to manage complex message queuing and retrieval effectively. The core supports dynamic buffer management and system reliability, crucial for defense integrations that demand high data integrity and minimal transmission delay. It proves essential for network security needs, consistently meeting the rigorous requirements of modern defense communications.
The Flexibilis Ethernet Switch (FES) is a multi-functional Ethernet Layer 2 switch IP core providing high-speed data forwarding and advanced clock synchronization. This IP core supports triple-speed Ethernet functionality, ensuring comprehensive integration into various network environments where performance and reliability are paramount. Designed to maintain high throughput, the FES offers twelve full-duplex Gigabit Ethernet ports, prepared for the demands of complex industrial and telecommunication networks. The IP core's sophisticated memory management allows efficient use of FPGA resources, accommodating varying frame sizes without excessive resource allocation, which is especially beneficial during high network loads. FES integrates end-to-end and peer-to-peer IEEE 1588v2 transparent clock functionalities, providing critical precision in time-sensitive applications. By supporting VLAN tagging, traffic prioritization, and advanced packet filtering, it enhances both network performance and security. Available in multiple configurations, FES is adaptable to meet various network requirements, making it an ideal choice for engineering next-generation networks needing high-speed and robust communication capabilities.
Certus Semiconductor specializes in advanced RF/Analog IP solutions, tackling the intricate needs of high-performance wireless communication systems. Their cutting-edge technology provides ultra-low power wireless front-end integration, verified across a range of silicon contexts to ensure reliability and excellence. These solutions cover a comprehensive spectrum of RF configurations from silicon-proven RF IPs to fully integrated RF transceivers used in state-of-the-art wireless devices. Features of Certus's RF/Analog solutions include finely tuned custom PLLs and LNAs with frequencies reaching up to 6GHz, tailored for superior phase noise performance and minimal jitter. This level of precision ensures optimized signal integrity and power efficiency, crucial for maintaining peak operations in wireless systems like LTE, WiFi, and GNSS. Furthermore, the innovative next-generation wireless IPs cater to ultra-low latency operations necessary for modern communication protocols, demonstrating Certus Semiconductor's commitment to driving forward-thinking technology in RF design. With an inclusive approach covering custom designs and off-the-shelf IP offerings, Certus ensures that each product meets specific project demands with exceptional precision and efficiency.
Efinix's Topaz FPGA series is engineered for mass-market applications, delivering a perfect mix of efficiency and adaptability. These FPGAs encapsulate a highly efficient architecture, combined with the industry's essential features and protocols, such as PCIe Gen3, MIPI, and LPDDR4. This configuration allows users to harness substantial performance while maintaining ample room for future innovations. Topaz FPGAs are optimized for high-volume production environments where cost-effectiveness and swift integration are paramount. Their design promotes ease of implementation in various applications, spanning from automotive to deeply embedded systems, where reliability and robustness are key. Featuring a streamlined architecture, Topaz series FPGAs support modern connectivity standards and data processing capabilities. These devices are tailored for industries requiring scalable solutions that can adapt to evolving technological landscapes, ensuring that Efinix customers remain competitive in their respective fields.
VSORA's Tyr Superchip epitomizes high-performance capabilities tailored for the demanding worlds of autonomous driving and generative AI. With its advanced multi-core architecture, this superchip can execute any algorithm efficiently without relying on CUDA, which promotes versatility in AI deployment. Built to deliver a seamless combination of AI and general-purpose processing, the Tyr Superchip utilizes sparsity techniques, supporting quantization on-the-fly, which optimizes its performance for a wide array of computational tasks. The Tyr Superchip is distinctive for its ability to support the simultaneous execution of AI and DSP tasks, selectable on a layer-by-layer basis, which provides unparalleled flexibility in workload management. This flexibility is further complemented by its low latency and power-efficient design, boasting performance near theoretical maximums, with support for next-generation algorithms and software-defined vehicles (SDVs). Safety is prioritized with the implementation of ISO26262/ASIL-D features, making the Tyr Superchip an ideal solution for the automotive industry. Its hardware is designed to handle the computational load required for safe and efficient autonomous driving, and its programmability allows for ongoing adaptations to new automotive standards and innovations.
AccelerComm's Polar coding solution is a state-of-the-art offering tailored for the 5G NR control channel, providing efficiencies that redefine how fast data can be accurately processed and transmitted. This IP is groundbreaking due to its ability to enable higher degrees of parallelism and scalability, essential for high-demand network uses. The architecture stands out due to its high degree of resource efficiency, significantly lessening the use of computational resources while ensuring top-tier performance. Its compliance with 3GPP standards ensures smooth integration within existing frameworks, making it an invaluable asset for operators focusing on control channel integrity. Particularly advantageous for its configurability, the Polar solution scales to meet exacting BLER performance parameters. This level of adaptability underpins the capability to achieve superior spectral efficiency gains, crucial for modern wireless communications.
Creonic delivers advanced Polar Encoders/Decoders that offer high flexibility and efficiency for cutting-edge communications. The companyās Polar solutions capitalize on polar code technology, which is recognized for its channel capacity achievement capabilities in the field of communications. These encoders and decoders are particularly input for Ultra Reliable Low Latency Communications (URLLC), with applications extending to 5G networks and beyond. Creonicās solution supports various coding rates and code lengths, providing a robust framework for creating customized configurations based on customer specifications. Compatibility with major FPGA platforms allows for seamless integration into existing systems, ensuring optimal performance and scalability across numerous applications. The Polar Encoder/Decoder IP is designed to handle both short and long frames, providing enhanced reliability and ensuring data is efficiently and accurately transmitted over different communication channels.
Creonic's Turbo Encoders/Decoders offer advanced error correction features for modern digital communication systems. Originating from iterative decoding theory, the turbo codes provided are known for their efficiency and performance close to Shannonās limit. These encoders and decoders come in various configurations to suit both existing and emergent network standards such as DVB-RCS2 and 4G LTE. Engineered with scalability in mind, Creonic's Turbo solutions support a wide range of data rates and frame sizes, making them a flexible choice for operators targeting satellite or terrestrial networks. Their modular design ensures easy integration and adaptability across various digital platforms and communication technologies. The products maintain high data integrity, enabling reliable data delivery even in high-noise environments. Creonic ensures that each turbo code solution is compliant with international standards, providing a seamless interoperability experience across diverse network architectures.
Algo-Logic's FPGA Tick-To-Trade platform focuses on optimizing the critical path in high-frequency trading by incorporating trading algorithms into FPGA-based systems for rapid execution. The solution significantly enhances the performance of order management systems by reducing the time between receiving and executing trading data, termed as 'Tick-To-Trade.' This reduction in latency is especially beneficial for proprietary trading firms and market makers who thrive on the speed of trade execution. This platform capitalizes on the speed advantage inherent in FPGA technology, combined with Algo-Logicās proprietary logic designs aimed at providing deterministic performance. By minimizing variables such as jitter and latency, the Tick-To-Trade solution ensures that trading algorithms can execute trades as quickly as the market environment allows. Supported across multiple FPGA platforms from industry giants like Cisco and Xilinx, Algo-Logicās solution integrates seamlessly into existing infrastructures, allowing clients to leverage ultra-low latency networking capabilities without overhauling their current systems. The emphasis on adaptability and robustness makes it a preferred choice for institutions investing in high-frequency trading architectures.
Creonic's LDPC Encoders/Decoders are engineered to deliver high throughput and low latency for communications and data applications. The exceptional performance of these encoders and decoders ensures that they are ideally suited for applications such as satellite communications, broadband wireless, and high-speed networking. Creonic provides a comprehensive range of LDPC solutions that can be customized to match various standards, including DVB-S2X, 5G NR, IEEE, and CCSDS. Each LDPC solution is robustly engineered, offering maximum flexibility to adapt to different code rates and frame sizes. These cores are implemented to ensure compatibility with diverse FPGA platforms like Xilinx and Intel. Customers benefit from a solid framework that integrates efficient encoding and decoding mechanisms, ensuring reliable data transfer across challenging communication environments. The LDPC products stand out for their superior error correction capabilities, which help in mitigating the adverse effects of signal degradation. Creonic's solutions target both existing and emerging communications standards, ensuring future-proof reliability and performance enhancement.
The 100 Gbps Polar Encoder and Decoder is engineered for the next-generation communication systems demanding ultra-high data rates and reliability. It employs Polar coding, a recent advancement in code theory, which provides a capacity achieving solution to enhance data transfer efficiency in modern networks, particularly suitable for 5G technologies. This IP core supports data rates up to 100 Gbps, enabling rapid data encoding and decoding essential for high-speed communication backbones. The technology ensures robust error correction and maximal utilization of spectral resources by leveraging the power of Polar code combined with optimized algorithmic implementations. Strategically designed for industry-leading performance, this Polar Encoder and Decoder is applicable in systems where bandwidth efficiency and processing speed are critical. It is highly applicable to the telecommunication industries involved in mobile networks, data centers, and any large-scale data streaming operations.
XtremeSilica's 100G UDP Offload Engine is engineered for performance, delivering outstanding speed and efficiency for large volumes of data transmission. Ideal for specialized applications, this solution empowers users to achieve superior network performance with minimum system overhead.
This advanced engine combines multiple functionalities, integrating TCP offloading with Ethernet MAC and PCIe interface, designed for ultra-low latency operations. It ensures efficient data transfer with minimal CPU intervention, making it ideal for high-frequency trading and real-time applications. The integration of host interfaces further optimizes connectivity, providing seamless interaction between networked systems and processing units. The IP demonstrates high throughput, maintaining performance consistency irrespective of the network load, thus offering exceptional stability and reliability. This feature is crucial in dynamic data environments where constant data flow is essential. The offload engine also supports wide protocol compatibility, making it a versatile choice for various networking equipment. Moreover, this solution underscores Intilop's commitment to delivering cutting-edge technology in IP cores, facilitating enhanced network management and operational efficiency. The IP is designed to withstand the demands of high-speed data environments, bringing a new level of speed and accuracy to data handling.
The Advanced Flexibilis Ethernet Controller (AFEC) serves as a powerful Ethernet controller IP block for both programmable devices and ASICs. It provides a comprehensive interface for network communication while significantly reducing system overhead, thanks to its selective features like bus master DMA and scatter-gather capabilities. AFEC supports triple-speed Ethernet, engaging both copper and fiber interfaces. Its robust design accommodates gigabit transfer rates, enhancing network throughput even when integrated with less powerful processing units. The inclusion of IEEE 1588 Precision Time Protocol allows for precise time stamping of network frames, enabling effective time synchronization across complex systems. This controller is equipped with additional functionalities to streamline network operations, such as automatic CRC handling and advanced interrupt management. These features make AFEC an optimal component in applications where performance and precision are critical, such as financial trading platforms and mission-critical communication systems.
ArrayNav represents a significant leap forward in navigation technology through the implementation of multiple antennas which greatly enhances GNSS performance. With its capability to recognize and eliminate multipath signals or those intended for jamming or spoofing, ArrayNav ensures a high degree of accuracy and reliability in diverse environments. Utilizing four antennas along with specialized firmware, ArrayNav can place null signals in the direction of unwanted interference, thus preserving the integrity of GNSS operations. This setup not only delivers a commendable 6-18dB gain in sensitivity but also ensures sub-meter accuracy and faster acquisition times when acquiring satellite data. ArrayNav is ideal for urban canyons and complex terrains where signal integrity is often compromised by reflections and multipath. As a patented solution from EtherWhere, it efficiently remedies poor GNSS performance issues associated with interference, making it an invaluable asset in high-reliability navigation systems. Moreover, the system provides substantial improvements in sensitivity, allowing for robust navigation not just in clear open skies but also in challenging urban landscapes. Through this additive capability, ArrayNav promotes enhanced vehicular ADAS applications, boosting overall system performance and achieving higher safety standards.
The BCH Error Correcting Code ECC is crafted to provide paramount error correction capabilities, ideal for applications demanding high data fidelity and error resilience. This code is quintessentially designed to operate asynchronously with zero latency, optimized for minimal power use and gate count. It eliminates the necessity for synchronous logic by adopting a purely combinatorial gate-driven process. The BCH Code supports a variety of environments through configurable parameters, such as symbol size and error symbol corrigibility, thereby offering a flexible use-case across multiple domains. This IP is particularly beneficial in high-performance computing and communication systems, ensuring data integrity in storage devices like SSD controllers and high-speed interface applications. Its capacity to handle several error types without requiring sequential logic resources enhances its applicability in modern integrated circuits, where space and power constraints are pivotal.
The ePHY-11207 marks the frontier of eTopus's high-speed SerDes capabilities, facilitating data rates from 1 to 112Gbps. This 7nm nodal innovation is particularly significant in environments where latency precision and bandwidth are critical, such as in advanced networking interfaces and server applications. It integrates seamlessly with the existing network fabric, supporting high throughput demands and lower latency metrics, bolstered by eTopus's proprietary algorithms.
The LDPC Decoder tailored for 5G New Radio (NR) applications offers robust decoding capabilities with the implementation of the Min-Sum algorithm. This decoder's architecture includes advanced features such as early iteration termination, programmable bit widths, and support for HARQ-related functionalities, all aimed at optimizing decoding performance. It is a key component in managing link reliability and efficiency, suitable for advanced wireless communication systems.
Time-Triggered Ethernet is an enhanced network solution tailored for environments requiring stringent timing and synchronization. By leveraging the principles of time-triggered communication, it enhances standard Ethernet with deterministic capabilities. This advanced protocol is instrumental in ensuring timely and predictable data exchange, making it ideal for complex network architectures where timing precision is a must. Utilizing synchronized clocks across the network, Time-Triggered Ethernet virtually eliminates latency variability. This predictability across the Ethernet infrastructure supports a variety of applications, from aviation systems requiring certified safety levels to automotive networks needing high reliability. The protocol helps in managing critical tasks efficiently by scheduling communication activities down to precise microsecond accuracy. Time-Triggered Ethernet enhances both the fault tolerance and robustness of networks it supports, making it a preferred choice for high-stakes scenarios. Its ability to carry safety-critical and time-sensitive data over existing Ethernet infrastructure ensures wide applicability and adaptability. By optimizing performance while maintaining compatibility with Ethernet standards, it supports diverse applications from smart industry automation to critical aerospace systems.
Algo-Logicās ULL 10GE PHY+MAC is designed to deliver exceptional low-latency performance tailored for 10 Gigabit Ethernet environments. The product, targeted for high-frequency trading (HFT) and high-performance computing (HPC) systems, ensures that data transactions are completed swiftly and reliably. This IP core stands out with its compliance with IEEE802.3 standards and support for both Avalon-ST and AXI4-Stream interfaces, making it a versatile choice for various FPGA platforms. Key features include local and remote fault detection, frame check sequence processing, and compatibility with SERDES. The core is engineered to offer a straightforward replacement for default high-latency vendor cores, providing trading firms with a robust solution to enhance the performance of their systems significantly. Optimizations within the core reduce gate count while maintaining system flexibility, which is crucial for maintaining the competitive edge in trading applications.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: āflat parity bits puncturing instead of Rate Matching Bit Selectionā, āmaintaining the first 2xZc payload bits instead of eliminating it before transmissionā, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
CLOP Technologies' 60GHz Wireless Solution offers businesses an impressive alternative to traditional networking systems. Leveraging the IEEE 802.11ad WiFi standard and Wireless Gigabit Alliance MAC/PHY specifications, this solution achieves a peak data rate of up to 4.6Gbps. This makes it particularly suited for applications that require significant bandwidth, such as real-time, uncompressed HD video streaming and high-speed data transfers ā operations that are notably quicker compared to current WiFi systems. The solution is engineered to support 802.11ad IP networking, providing a platform for IP-based applications like peer-to-peer data transfer and serving as a router or access point. Its architecture includes a USB 3.0 host interface and mechanisms for RF impairment compensation, ensuring both ease of access for host compatibility and robust performance even under high data rate operations. Operating on a frequency band ranging from 57GHz to 66GHz, the wireless solution utilizes modulation modes such as BPSK, QPSK, and 16QAM. It incorporates forward error correction (FEC) with LDPC codes, providing various coding rates for enhanced data integrity. Furthermore, the system boasts AES-128 hardware security, with quality of service maintained through IEEE 802.11e standards.