All IPs > Wireline Communication > Error Correction/Detection
In the realm of wireline communication, ensuring the integrity and reliability of data transmission is a critical concern. This is where Error Correction and Detection semiconductor IPs play a pivotal role. These IPs are designed to identify and rectify errors that occur during data transmission, thus enhancing the overall performance and reliability of wireline communication systems. Whether it involves correcting single-bit errors or detecting complex data discrepancies, these IPs are essential for maintaining the fidelity of data transmission.
Error Correction and Detection IPs utilize various sophisticated algorithms and techniques such as Reed-Solomon, Hamming Code, and Cyclic Redundancy Check (CRC). These technologies work by adding redundancy to the data being transmitted, allowing the receiver to detect errors and, in many cases, automatically correct them. This process not only protects data integrity but also ensures higher quality of service, reducing the need for retransmissions and improving network efficiency.
These semiconductor IP blocks are implemented in a wide array of applications including broadband networks, data centers, and telecommunication systems where uninterrupted and accurate data transmission is paramount. For engineers and developers, leveraging these IPs can significantly accelerate the development process of wireline systems by providing ready-to-integrate solutions that uphold communication standards.
In this category, you will find a vast selection of Error Correction and Detection semiconductor IPs suited for various applications. These IPs are available from leading suppliers, offering solutions that support multiple protocols and data rates. With these IPs, developers can ensure their wireline communication products are robust, reliable, and capable of delivering the highest levels of performance needed in today's data-driven world.
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
The D2200 is a high-performance PCIe SSD designed by Swissbit for enterprise and data center applications. It combines exceptional data speeds with low power consumption to enhance system performance. This SSD is equipped with state-of-the-art NAND technology, ensuring sustained performance even under intense workloads. The D2200's design prioritizes temperature and performance management, making it resilient against environmental extremes and suitable for mission-critical applications.
The Reed Solomon Error Correcting Code ECC targets environments where error minimization during high-speed data processing is paramount. Its design capitalizes on a zero-latency, asynchronous processing model that negates the need for clocks and iterative data storage, using basic combinatorial logic to streamline error correction. This error correction code stands out due to its adjustable parameters, including the symbol size and the count of correctable error symbols, enabling operators to modify the code for optimal performance based on specific requirements. This flexibility extends to its coding structure, which uses minimal clock cycles for execution, thus fast-tracking error detection and recovery processes. It is ideally suited for an array of applications such as digital storage systems, communication networks, and wherever data robustness is critically assessed. The IP’s reliability is further enhanced through a verified and lint-clean RTL, tailored to meet diverse error correction needs efficiently and effectively.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
AccelerComm's Polar coding solution is a state-of-the-art offering tailored for the 5G NR control channel, providing efficiencies that redefine how fast data can be accurately processed and transmitted. This IP is groundbreaking due to its ability to enable higher degrees of parallelism and scalability, essential for high-demand network uses. The architecture stands out due to its high degree of resource efficiency, significantly lessening the use of computational resources while ensuring top-tier performance. Its compliance with 3GPP standards ensures smooth integration within existing frameworks, making it an invaluable asset for operators focusing on control channel integrity. Particularly advantageous for its configurability, the Polar solution scales to meet exacting BLER performance parameters. This level of adaptability underpins the capability to achieve superior spectral efficiency gains, crucial for modern wireless communications.
Creonic delivers advanced Polar Encoders/Decoders that offer high flexibility and efficiency for cutting-edge communications. The company’s Polar solutions capitalize on polar code technology, which is recognized for its channel capacity achievement capabilities in the field of communications. These encoders and decoders are particularly input for Ultra Reliable Low Latency Communications (URLLC), with applications extending to 5G networks and beyond. Creonic’s solution supports various coding rates and code lengths, providing a robust framework for creating customized configurations based on customer specifications. Compatibility with major FPGA platforms allows for seamless integration into existing systems, ensuring optimal performance and scalability across numerous applications. The Polar Encoder/Decoder IP is designed to handle both short and long frames, providing enhanced reliability and ensuring data is efficiently and accurately transmitted over different communication channels.
Creonic's Turbo Encoders/Decoders offer advanced error correction features for modern digital communication systems. Originating from iterative decoding theory, the turbo codes provided are known for their efficiency and performance close to Shannon’s limit. These encoders and decoders come in various configurations to suit both existing and emergent network standards such as DVB-RCS2 and 4G LTE. Engineered with scalability in mind, Creonic's Turbo solutions support a wide range of data rates and frame sizes, making them a flexible choice for operators targeting satellite or terrestrial networks. Their modular design ensures easy integration and adaptability across various digital platforms and communication technologies. The products maintain high data integrity, enabling reliable data delivery even in high-noise environments. Creonic ensures that each turbo code solution is compliant with international standards, providing a seamless interoperability experience across diverse network architectures.
Creonic's LDPC Encoders/Decoders are engineered to deliver high throughput and low latency for communications and data applications. The exceptional performance of these encoders and decoders ensures that they are ideally suited for applications such as satellite communications, broadband wireless, and high-speed networking. Creonic provides a comprehensive range of LDPC solutions that can be customized to match various standards, including DVB-S2X, 5G NR, IEEE, and CCSDS. Each LDPC solution is robustly engineered, offering maximum flexibility to adapt to different code rates and frame sizes. These cores are implemented to ensure compatibility with diverse FPGA platforms like Xilinx and Intel. Customers benefit from a solid framework that integrates efficient encoding and decoding mechanisms, ensuring reliable data transfer across challenging communication environments. The LDPC products stand out for their superior error correction capabilities, which help in mitigating the adverse effects of signal degradation. Creonic's solutions target both existing and emerging communications standards, ensuring future-proof reliability and performance enhancement.
The 100 Gbps Polar Encoder and Decoder is engineered for the next-generation communication systems demanding ultra-high data rates and reliability. It employs Polar coding, a recent advancement in code theory, which provides a capacity achieving solution to enhance data transfer efficiency in modern networks, particularly suitable for 5G technologies. This IP core supports data rates up to 100 Gbps, enabling rapid data encoding and decoding essential for high-speed communication backbones. The technology ensures robust error correction and maximal utilization of spectral resources by leveraging the power of Polar code combined with optimized algorithmic implementations. Strategically designed for industry-leading performance, this Polar Encoder and Decoder is applicable in systems where bandwidth efficiency and processing speed are critical. It is highly applicable to the telecommunication industries involved in mobile networks, data centers, and any large-scale data streaming operations.
The BCH Error Correcting Code ECC is crafted to provide paramount error correction capabilities, ideal for applications demanding high data fidelity and error resilience. This code is quintessentially designed to operate asynchronously with zero latency, optimized for minimal power use and gate count. It eliminates the necessity for synchronous logic by adopting a purely combinatorial gate-driven process. The BCH Code supports a variety of environments through configurable parameters, such as symbol size and error symbol corrigibility, thereby offering a flexible use-case across multiple domains. This IP is particularly beneficial in high-performance computing and communication systems, ensuring data integrity in storage devices like SSD controllers and high-speed interface applications. Its capacity to handle several error types without requiring sequential logic resources enhances its applicability in modern integrated circuits, where space and power constraints are pivotal.
The LDPC Decoder tailored for 5G New Radio (NR) applications offers robust decoding capabilities with the implementation of the Min-Sum algorithm. This decoder's architecture includes advanced features such as early iteration termination, programmable bit widths, and support for HARQ-related functionalities, all aimed at optimizing decoding performance. It is a key component in managing link reliability and efficiency, suitable for advanced wireless communication systems.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
Creonic’s Miscellaneous FEC and DSP IP Cores are an essential toolkit for enhancing digital signal processing capabilities across various fields. These include solutions like Viterbi Decoders, FFT/IFFT processors, and advanced BCH code implementations, which are cornerstones in data correction and signal processing. These DSP cores are engineered for high performance and efficiency, vital for applications demanding robust signal integrity and processing speed. From Doppler Channel processing found in satellite and radio communications to sophisticated stream processing in broadband networks, every core is fine-tuned for specific performance requirements. Creonic provides adaptable designs that are geared for seamless integration into existing platforms, ensuring continued enhancement of network efficiency and data reliability. The flexibility of these cores means they can be tailored to fit diverse operational standards, making them invaluable in meeting complex communication challenges.
Implementing the Widmer and Franaszek 8b/10b scheme, this decoder handles error detection and correction by identifying specific comma sequences and automatically recognizing K28.5 characters. It's integral to maintaining data integrity and reliability across high-speed data transmission systems and supports industries requiring robust communication protocols.
The ntLDPC_DVBS2X IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2X decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the DVB-S2 and DVB-S2X standards. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2X encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. Actual encoding is performed as a three part recursive computation process, where row sums, checksums of all produced rows column-wise and finally transposed parity bit sums are calculated. The ntLDPC_DVBS2X decoder IP implements a 360-bit parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. The decoder IP permutes each block’s parity LLRs to become compatible with the layered decoding scheme and stores channel LLRs to processes them in layered format. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity submatrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit.
The ntLDPC_8023CA (17664,14592) IP Core is defined in IEEE 802.3ca-2020 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCE_8023CA encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer when multiplied by the 14592 payload block pro-duces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1 to 6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_8023CA decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_8023CA decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
AccelerComm's High PHY Accelerators are advanced solutions featuring a library of IP cores that cater to a range of 5G NR needs, including key signal processing algorithms. These accelerators are aimed at maximizing efficiency in data throughput and reducing latency, which are essential for modern communication standards. Providing enhancements such as LDPC that improves BLER significantly, these accelerators deliver reduced spectral costs and power consumption. They are available in several forms - ASICs, FPGAs, or software-only configurations - and can be deployed in varied hardware environments. The integration of complex algorithms like Hybrid Automatic Repeat reQuest (HARQ) and channel estimation signify their role in enhancing the robustness and reliability of 5G communications. Born from rigorous academic research, the High PHY Accelerators are highly configurable, adapting to specific network demands. Their success is validated by compliance with key 3GPP standards, making them a cornerstone technology for achieving superior network performance and efficiency.
AccelerComm offers an LDPC solution meticulously crafted for 5G NR channels that promises efficient error correction and superior throughput. This solution represents the best of block-parallel and row-parallel decode architectures, enhancing efficiency while maintaining top-notch performance. Widely recognized for its hardware efficiency, the LDPC enhances signal integrity in the data channel, ensuring minimal latency. It adheres to the complete 3GPP standardization, supporting code and transport block processing. The architecture's configurability supports diverse deployment needs, allowing seamless integration into existing network environments. Delivered in ASIC, FPGA, or software-only form factors, AccelerComm's LDPC block is ideal for operators seeking to maximize reliability and performance in their communications infrastructures. This IP stands as a testament to AccelerComm's innovation, marrying tradition with modern demands for enhanced digital communications.
The Convolutional Encoder and Viterbi Decoder are integral components of modern digital communication systems, specifically designed to enhance error correction capabilities. This setup is aimed at achieving superior Bit Error Rates (BER) with sustained Signal-to-Noise Ratios (SNRs), leveraging forward error correction mechanisms. The Convolutional Encoder established here operates with a configuration of (3, 1, 4), optimally structuring data for robust transmission by applying a series of generator polynomials. On the decoding end, the Viterbi algorithm is employed, a maximum likelihood convolutional decoder known for its efficacy in decoding convolutional codes. The integration of these components into wireless communication systems affords improved reliability and performance, especially crucial in maintaining data integrity over unstable or noisy communication channels. This solution is highly adaptable, supporting various polynomial configurations and customization needs per customer requirements. Such technology serves wireless applications that demand efficient correction and recovery of transmitted data, and it is suitable for systems where minimal intervention is desired while maintaining high data integrity. This systematic approach integrates support for complex encryption methods, allowing secure and reliable data transfer across multiple communication protocols.
The DVB-RCS and IEEE 802.16 WiMAX Turbo Decoder is expertly crafted for decoding tasks in high-speed data networks, particularly those using satellite and broadband wireless communication standards. This 8 state Duobinary Turbo Decoder features an optional 64 state Viterbi decoder, highlighting its capacity for intricate data throughput and error correction. Functional in a multitude of data environments, this decoder can handle a variety of signal paths, ensuring robust data recovery and integrity. Its architecture is especially suited for dynamic network conditions, offering adaptability and reliability-critical factors in maintaining service quality in challenging communication scenarios. This Decoder is ideal for systems operating under diverse protocols, ensuring seamless interoperability and efficient error detection and correction. By optimizing data processing technologies, it supports high-speed data exchanges across broader channels, catering to the growing demand for superior network performance in modern telecommunication infrastructures.
The ntRSC_DP1.4 IP core is compliant with Display Port 1.4 standard as published by Video Electronics Standards Association (VESA) for use in DSC (Display Stream Compression) technology. It is based on Reed-Solomon RS(254,250), 10 bit symbols, forward error correction code, where the codeword block consists of 250 information symbols and 4 RS parity symbols. The ntRSC_DP1.4 FEC IP Core ensures error resilient / glitch-free compressed video transport (DSC) to external displays. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The Galois Error Correcting Code offers sophisticated error correction capabilities using zero latency asynchronous logic. It employs advanced Galois Field arithmetic to ensure that errors, particularly those resulting from heightened environmental noise or electromagnetic interference, are correctly identified and rectified. The key features of this code include its scalability, allowing for adjustments in the degree of the primitive polynomial, and the number of correctable error symbols, thereby supporting a wide range of data transmission scenarios. Typically applied where stringent data integrity is required, this code is optimal for long-range communication systems and high-speed digital interfaces. The design provides a fully programmable RTL environment, ensuring adaptability across varying deployment contexts without reliance on traditional memory or feedback loops. This makes it an ideal choice for sectors demanding high reliability and swift correction capabilities, such as telecommunications and storage applications.
The Reed Solomon Erasure Code by Secantec is designed for applications requiring robust data integrity, especially in RAID and data center environments. This code operates using zero latency and a low gate count due to its asynchronous, combinatorial logic framework which eliminates cyclical dependencies and clock requirements. Notably, it does not utilize traditional storage methods such as SRAMs, ROMs, or flip-flops, ensuring efficient and rapid error correction. The design focuses on all Galois Field operations using m bit symbol sizes, offering programmability for a variety of parameters like the degree of primitive polynomial and maximum correctable errors. Applications include correcting known erasure locations and recovering data accurately in high-speed communication channels and storage systems. The IP stands out for its configurable RTL parameters that adapt to various error correction needs, maintaining lint-clean code for assured operational fidelity.
In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used in the decoder to eliminate the channel noise. The error correction capability of a FEC system strongly depends on the amount of redundancy as well as on the coding algorithm itself. TPCs perform well in the moderate to high SNRs because the effect of error floor is less. As TPCs have more advantage when a high rate code is used, they are suitable for commercial applications in wireless and satellite communications. The ntTPC Turbo Product Codec IP core is consisted of the Turbo Product Encoder (ntTPCe) and the Turbo Product Decoder (ntTPCd) blocks. The product code C is derived from two/three constituent codes, namely C1, C2 and optionally C3. The information data is encoded in two/three dimensions. Every row of C is a code of C2 and every column of C is a code of C1. When the third coding dimension is enabled, then there are C3 C1*C2 data planes. The ntTPC core supports both e-Hamming and Single Parity Codes as the constituent codes. The core also supports shortening of rows or columns of the product table, as well as turbo shortening. Shortening is a way of providing more powerful codes by removing information bits from the code. The ntTPCe core receives the information bits row by row from left to right and transmits the encoded bits in the same order. It consists of a row, column and 3D encoder. The ntTPCd decoder receives soft information from the channel in the 2’s complement number system and the input samples are received row by row from left to right. The implemented decoding algorithm computes the extrinsic information for every dimension C1, C2, C3 by iteratively decoding words that are near the soft-input word. An advanced scalable and parametric design approach produces custom design versions tailored to end customer applications design tradeoffs.
The DVB-RCS and IEEE 802.16 WiMAX Turbo Encoder provides a sophisticated solution for broadband wireless access systems. Featuring an 8 state configuration, it ensures robust data encoding processes suited for high-capacity networks. This encoder is pivotal in enhancing error control and efficiency across satellite and wireless communication systems, where maintaining high uptime and performance is vital. This encoder is optimized to integrate with DVB-RCS systems, allowing for standardized communication across varied platforms. Its design not only enhances signal integrity but also supports extensive customizations, accommodating specific project requirements and streamlining deployment processes in complex environments. The turbo encoder is also compatible with IEEE 802.16 WiMAX, making it a versatile choice for companies developing wireless infrastructure. By offering unparalleled data processing speeds and reliability, this encoder plays a critical role in modern telecommunication setups. It leverages cutting-edge technology to minimize latency and maximize throughput, addressing the rigorous demands of cutting-edge wireless networks.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
The ntLDPC_Ghn IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCD_Ghn decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the ITU-T G.9960 G.hn standard. The ntLDPCE_Ghn encoder IP implements a 360-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. The ntLDPCD_Ghn decoder IP implements a 360-LLR parallel systematic LDPC layered decoder. A separate off-line profiling Matlab script is used to profile the layered matrices and resolve any possible memory access conflicts. Each layer corresponds to Z=[14, 80, 360, 60, 270, 48 or 216] expanded rows of the original LDPC matrix, depending on the mode selected expansion factor. Each layer element corresponds to the active ZxZ shifted identity sub-matrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been executed. The decoder also IP features a powerful optional early termination (ET) criterion, to maintain practically the same error correction performance, while significantly increasing its throughput rate. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI.
The G13 and G13X IP cores are engineered to accomplish 512-bit correction blocks, which are commonly used in NAND devices with 2KB and 4KB page sizes. As SLC NAND transitions toward smaller geometries, this IP extends existing controller capabilities to meet more demanding ECC requirements. Not only available in standard configurations, Cyclic Design can tailor this IP to perfectly align with the specific needs of any controller hardware, addressing latency, bandwidth, and area prerequisites.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
ntRSD_UF core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length, maximum number of parity symbols as well as I/O data width, internal datapath and decoding engines parallelism. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD_UF core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The core is designed and optimized for applications that need very high throughput data rates. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The SOQPSK-TG LDPC Modulator supports advanced modulating techniques tailored for aerospace telemetry applications. This modulator utilizes Spectrally Efficient Constant Envelope Modulation with a highly efficient LDPC (Low-Density Parity-Check) coding scheme that ensures reliable data transmission even in challenging conditions. Built for robust performance, it integrates seamlessly with modern communication systems to enhance signal integrity and data throughput. Engineered for precision, this modulator offers low error rates by leveraging sophisticated LDPC algorithms, thereby optimizing network capacity and spectral efficiency. It is ideal for systems requiring high resilience against signal degradation, such as satellite and telemetry networks. Equipped with cutting-edge encoding technology, the SOQPSK-TG LDPC Modulator is designed to operate over a wide range of frequency bands, making it adaptable for various telemetry and aerospace applications. Its compact architecture allows for easy integration into existing infrastructures, thus facilitating quick deployment and operational flexibility.
Designed for advanced network diagnostics, the 10G Universal Network Probe enables comprehensive traffic monitoring and analysis across OTN and other high-capacity networks. This probe offers versatile compatibility, ensuring streamlined integration into existing infrastructure, a critical function for maintaining high-speed data transmission fidelity and efficiency.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The 3GPP LTE Turbo Decoder is engineered to enhance data processing in high-performance mobile networks. With an 8 state configuration and options for 1, 2, 4, or 8 parallel MAP decoders, it is designed to significantly improve error correction, ensuring reliable and high-speed data transmission in LTE environments. This decoder is optimized for networks where bandwidth efficiency is crucial, achieving peak performance while effectively handling the noise and interference prevalent in mobile networks. The option to integrate multiple parallel decoders allows for customized implementations, aligning with specific mobile network demands and optimizing overall system throughput and reliability. Deploying this decoder can vastly improve application responsiveness and network resource management. It plays a pivotal role in the tech infrastructure necessary to support 4G LTE services, meeting the high expectations for connectivity and data integrity demanded by users and service providers alike.
IP-Maker's BCH Encoder/Decoder IP core is designed to enhance the reliability and lifespan of NAND Flash-based storage by correcting errors in data writes. Incorporating the BCH algorithm, this core supports up to 76 error-bits per block, ensuring data integrity during storage reads and writes. This capability is crucial for maintaining performance and accuracy in data-intensive applications. The core's customization options enable optimization for different use scenarios, balancing between latency and gate count. In FPGA and ASIC designs, the IP is highly configurable, allowing specifications adjustments such as block size and data throughput. This makes it adaptable for various application scales, from small IoT devices to large data centers. Delivered as Verilog RTL with synthesis scripts and technical documentation, the BCH core simplifies development and integration processes. Fully tested in both simulated and hardware environments, it brings great reliability to storage solutions, reducing time-to-market and ensuring a smooth development cycle for OEMs.
Designed for multi-standard networks, the 3GPP LTE and 3GPP2 1xEV-DO Turbo Decoder excels in environments requiring flexibility and advanced error correction. It features an 8 state turbo decoding system, utilizing ping-pong input and output memories for enhanced data processing and throughput. This decoder ensures consistency in data communication, a necessity for networks that support LTE and 1xEV-DO standards. It is engineered for efficient operation across different network types, supporting varied communication protocols and improving signal integrity and data correctness. Optimizing both data transfer speeds and network reliability, this decoder supports robust implementations for telecom operators, facilitating smoother transitions and reduced error rates within network infrastructure. It significantly contributes to improved user experiences and reliable data exchanges, even under heavy network demands.
ntRSE core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The G15 ECC core represents a sophisticated error correction IP optimized for 2KB correction blocks, directly applicable to NAND devices with larger page sizes. With a compatibility that extends across 512B and 1KB correction blocks, the G15 is designed to be adaptable and performance-oriented. Enhanced architectural features ensure optimal integration into existing systems when partnered with Cyclic Design’s expertise, providing a comprehensive solution tailored for demanding ECC requirements.
ntRSC_IESS core is a highly integrated solution implementing a time-domain Reed-Solomon Forward Error Correction algorithm. The core supports several programming features including codeword size, error threshold, number of parity bytes, reverse or forward order of the output, mode of operation (encode, decode or pass-through), shortened code support, erasures or error only decoding. Very low latency, high speed, simple interfacing and programmability make this core ideal for many applications including Intelsat IESS-308, DTV, DBS, ADSL, Satellite Communications, High performance modems and networks.
The G14 and G14X IP cores are specialized for 1KB correction blocks, suitable for NAND devices with 8KB page sizes. Initially designed for MLC, its capabilities extend to SLC flash controllers, providing increased wear leveling and long-term compliance with evolving ECC standards. Available in an off-the-shelf model or customized configuration, the G14X is crucial for advanced applications requiring significant error correction capabilities.
The Interlaken PHY Solution provides an efficient interface for high-bandwidth data streams, targeting the needs of networking and communications where low latency and high throughput are critical. This solution is suitable for large data center applications, where it mitigates congestion by supporting scalable networking infrastructures. The Interlaken protocol blends data transfer efficiency with robust error correction, allowing seamless data flow even as network scales increase. It supports multiple lanes and channels, enabling parallel data transactions that boost performance. This IP core is configurable to fit diverse requirements, making it adaptable for various industrial and commercial applications. By implementing the Interlaken protocol, organizations benefit from reduced power consumption and increased operational efficiency, essential traits in today's energy-conscious ecosystems.
AccelerComm offers a sophisticated 5G NR physical layer solution that is particularly geared for specialized applications such as O-RAN, satellite communications, and small-cell networks. This solution supports options 6 and 7.x, integrating high-performance PHY elements with AccelerComm's bespoke Low PHY. The IP is designed to balance performance, power, and scalability, enabling optimal deployment across diverse networks. The 5G NR physical layer is equipped with Acceleration IP cores that leverage innovative signal processing techniques to boost link performance. Openly licensable, this IP supports a wide array of platforms, making it adaptable for ARM-based, FPGA, and ASIC implementations. It enhances project assurance with accessible reference systems that allow thorough integration and testing on commercially available boards. AccelerComm's complete physical layer IP is dedicated to ushering in transformative power and performance improvements to 5G networks, underpinning the infrastructure with superior signal processing to meet the rising demand for high-capacity data transmission.
The D-Series DDR5/4/3 Controller by MEMTECH is a high-performance memory controller that excels in latency management and bandwidth optimization. It is specifically tailored for applications requiring seamless physical layer integration and supports a range of standard interfaces such as DFI 5.0. With advanced command schedulers, sequencers, and error correction capabilities, this controller ensures data integrity and high-speed processing. Its design includes versatile support for multiple DDR generations, making it ideal for diverse technological environments and expanding the potential for product differentiation through customizable features.
Tailored for high-speed data networks, the IEEE 802.16 WiMAX Turbo Decoder operates with an 8 state Duobinary Turbo Decoder design, incorporating 4 parallel MAP decoders. This configuration offers exceptional data processing speeds critical for expansive broadband networks. The decoder is adept at managing complex data environments, adapting to various network conditions and maintaining high performance and minimal error rates. Its capabilities support robust signal recovery and data integrity, essential for modern communication infrastructures. Ideal for broadband wireless applications, this decoder supports high data throughput and efficient error correction, catering to the demanding expectations of today's network architectures. It serves as a pivotal tool for maximizing network capabilities and ensuring consistent service delivery across wide-ranging operating conditions.
The TETRA-TEDS Turbo Decoder is essential for telecommunications networks that operate under the TETRA-TEDS protocol, offering an 8 state turbo decoding with an optional 16 state Viterbi decoder. This decoder ensures reliable data transmission, which is critical in public safety and professional mobile radio applications where prompt and precise communication is paramount. Strong emphasis is placed on data integrity and low latency, making this decoder an invaluable tool for industries that require consistent, high-quality communication links. Its adaptive capabilities allow it to perform exceptionally in high-interference environments, maintaining clear and accurate data streams even in challenging conditions. The TETRA-TEDS Turbo Decoder integrates seamlessly into existing infrastructures, supporting services that require quick deployments and minimal downtime. By enhancing error correction and data processing speeds, it significantly bolsters communication reliability, allowing professionals to maintain uninterrupted contact and streamline operations effectively.
Specialized for dual-standard networks, the 3GPP UMTS/LTE and 3GPP2 Turbo Decoder accommodates systems requiring heightened flexibility and error correction capabilities. It operates using an 8 state design, with optional configurations of 16, 32, 64, or even 256 state Viterbi decoders. This wide range supports extensive error correction and aligns with various protocol demands. The decoder facilitates seamless transitions and data exchanges between UMTS and LTE networks, ensuring stability and continuity in service provision. Its adaptable design enables integration across varying network architectures, promoting improved data throughput and network efficiency for telecom providers looking to enhance their service quality. This decoder's sophisticated error correction capabilities make it suitable for advanced telecom applications, reducing error rates and enhancing signal integrity across different channels and frequencies. It is instrumental in ensuring strong connectivity and robust performance essential in today's complex mobile network environments.
Creonic specializes in high-performance Demodulation IP Cores designed to serve the most demanding communication environments. These demodulators are equipped to handle various standards, including DVB-S2X and CCSDS, optimized for applications ranging from satellite communications to high-frequency trading networks. Each demodulation core is engineered for high efficiency, supporting wide bandwidths and offering robust interference resistance. This makes them particularly suitable for complex communication systems where signal integrity can be threatened by bandwidth limitations and noise. The cores are built with MIMO detection capabilities, ensuring high data throughput and spectral efficiency. Creonic’s expertise ensures that these demodulation solutions are easily integrable with existing network infrastructures, supporting both current and future communication protocols effectively.
The ntDVBS2_FEC transmitter and receiver IPs, each instantiate an outer BCH and inner LDPC concatenated pair of encoders and decoders respectively. The Bose, Chaudhuri, and Hocquenghem (BCH) codes are the largest category of the powerful error-correction cyclic codes and belong to the block codes that are a generalization of the Hamming codes for multiple-error corrections. The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The concatenation of these two error correction algorithms enable performance well close to the Shannon limit. The ntBCH_DVBS2 encoder performs BCH encoding to payload frames by appending calculated parity bits at the end of each frame. The ntBCH_DVBS2 decoder finds the error locations within a received frame, tries to correct them and indicates a successful or failed decoding procedure. The ntLDPC_DVBS2 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2 encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants, associated with the matrix and hardcoded in the RTL encoder. Encoding is performed as a three part recursive computation process, where row sums, checksums of all rows column-wise and parity bit sums are calculated. The ntLDPC_DVBS2 decoder IP implements an approximation of the log-domain LDPC iterative decoding algorithm (Belief propagation), known as Layered Lambda-min2 Algorithm. The core is highly reconfigurable in terms of area, throughput and error correction performance trade-offs and is fully compliant to the DVB-S2 standard. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2 decoder IP implements a 360-LLR parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity sub-matrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder also IP features two powerful optional early termination (ET) criteria (convergence and parity check), to maintain practically the same error correction performance, while significantly increasing its throughput rate. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control hand-shaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI.
The Inmarsat Turbo Encoder is designed for high-speed satellite communication systems, enabling robust data transmission with enhanced error correction capabilities. It operates with a 16 state configuration, which is a significant improvement for achieving reliable communication over long distances. The Turbo Encoder is built to seamlessly integrate with Inmarsat platforms, optimizing for efficiency and performance. The encoder's specialized architecture supports a variety of configurations, making it suitable for applications that require dynamic adaptation to different channel conditions. This flexibility is crucial for maintaining high data integrity and throughput in the ever-changing satellite communication landscape. Furthermore, the encoder's modular design allows for tailored solutions, meeting specific needs of advanced telecommunication infrastructures. In addition to its standard functionalities, the Inmarsat Turbo Encoder can be enhanced with optional features such as pseudo-randomisers and input memory adaptation, which further extends its application range. By focusing on scalability and durability, this encoder provides a competitive edge in the field of satellite communications.
The Inmarsat Turbo Decoder is tailored for satellite communication networks, delivering reliable and high-speed data processing capabilities. It leverages a 16 state turbo decoding framework, supporting advanced error correction and data integrity essential for aerospace and satellite communication applications. The decoder includes optional 64 or 256 state Viterbi decoders, further refining data processing accuracy and efficiency. This sophisticated decoding structure supports seamless communication across satellite networks, optimizing data throughput and maintaining service quality. Ideal for use in Inmarsat systems, this decoder provides robust performance under challenging conditions, ensuring sustained data integrity and reliability. It is a vital component for satellite service providers seeking to enhance their communication infrastructure with cutting-edge technology.