All IPs > Wireline Communication > Ethernet
The wireline communication category of Ethernet semiconductor IPs is pivotal in the development of modern high-speed data transfer technologies. Ethernet technology, a mainstay in networking, facilitates the connection of computers to local networks (LANs) and wide-area networks (WANs). This category focuses on semiconductor IPs that implement Ethernet protocols, enabling manufacturers to integrate high-performance networking capabilities into their electronic devices efficiently and cost-effectively.
Ethernet semiconductor IPs are crucial for designing networking chips used in a variety of enterprise, consumer, and industrial applications. These IPs provide the foundational building blocks for implementing Ethernet standards from legacy 10/100 Mbps to the latest Multi-Gigabit Ethernet, including 1G, 10G, 25G, and beyond. Enhanced with features like Energy Efficient Ethernet (EEE) and advanced security mechanisms, these semiconductor IPs ensure optimized performance and reliability essential for today’s data-intensive applications.
The products in this category include a diverse range of Ethernet MAC(medium access control) cores, PHY(physical layer) cores, and network interface controllers, among others. These components work together to manage data packet transmission over Ethernet networks, ensuring seamless communication between connected devices. Designers leverage these Ethernet IPs to create routers, switches, servers, and Internet of Things (IoT) devices that require sophisticated data handling capabilities.
By integrating Ethernet semiconductor IPs, developers and OEMs can achieve faster time-to-market while reducing design risk and cost. These IPs are pre-verified, ensuring compliance with the current Ethernet standards, which accelerates the development cycle for networking equipment. Consequently, Ethernet semiconductor IPs are indispensable for any entity aiming to innovate within the competitive landscape of wireline communication technologies.
Chevin Technology's Ultra-Low Latency 10G Ethernet MAC is engineered to meet the demanding performance needs of modern telecommunications environments. This IP core optimizes data processing speed with its cutting-edge design, ensuring minimal latency and consistent data throughput. The Ultra-Low Latency 10G Ethernet MAC is particularly suited for real-time data exchange applications where swift data transmission is essential. It leverages a compact logic structure to achieve outstanding efficiency, minimizing resource requirements while bolstering performance capabilities. The core's versatile design supports straightforward integration into both new and existing systems across various FPGA platforms. It stands out for its energy-efficient operation, offering sizeable power savings over CPU-based implementations, and provides a robust licensing model to offer cost flexibility for developers.
The CT25205 Digital IP core is engineered to provide the core building blocks for 10BASE-T1S Ethernet applications, including PMA, PCS, and PLCA Reconciliation Sublayer adherence. Written in Verilog 2005 HDL, it is fully synthesizable with standard cells and FPGA, working cohesively with standard IEEE CSMA/CD Ethernet MAC via MII. The unit supports advanced PLCA features, enabling seamless communication with existing MAC devices. Connectivity is ensured through a standard OPEN Alliance 10BASE-T1S PMD Interface, creating an optimal solution for Zonal Gateway SoCs and MCUs adopting innovative 10BASE-T1S communication.
The NaviSoC, a flagship product of ChipCraft, combines a GNSS receiver with an on-chip application processor, providing an all-in-one solution for high-precision navigation and timing applications. This product is designed to meet the rigorous demands of industries such as automotive, UAVs, and smart agriculture. One of its standout features is the ability to support all major global navigation satellite systems, offering versatile functionality for various professional uses. The NaviSoC is tailored for high efficiency, delivering performance that incorporates low power consumption with robust computational capabilities. Specifically tailored for next-generation applications, NaviSoC offers flexibility through its ability to be adapted for different tasks, making it a preferred choice for many industries. It integrates seamlessly into systems requiring precision and reliability, providing developers with a wide array of programmable peripherals and interfaces. The foundational design ethos of the NaviSoC revolves around minimizing power usage while ensuring high precision and accuracy, making it an ideal component for battery-powered and portable devices. Additionally, ChipCraft provides integrated software development tools and navigation firmware, ensuring that clients can capitalize on fast time-to-market for their products. The design of the NaviSoC takes a comprehensive approach, factoring in real-world application requirements such as temperature variation and environmental challenges, thus providing a resilient and adaptable product for diverse uses.
Silicon Library provides the LVDS/OpenLDI solution to cater to the needs of systems requiring reliable data communication. LVDS, or Low Voltage Differential Signaling, is a standardized method for transmitting high-speed digital data with minimum power consumption and radiation. This technology is utilized in a broad range of applications like LCD screens and point-to-point links because of its fast data transmission capabilities and ability to support significant distances without compromising signal integrity. The OpenLDI variant extends these benefits further, supporting broader implementation such as industrial and consumer displays. With power-efficient designs, this LVDS/OpenLDI IP ensures enhanced performance with minimal power usage. Its design facilitates integration into systems where compact form factors and robust performance are vital, making it a staple in many high-performance display environments and communications systems.
The V-By-One HS technology from Silicon Library is aimed at providing a robust solution for high-speed video signal transmission over extended distances. It is used primarily in display technologies where the need for high data rates and minimal cabling is essential. V-By-One HS supports ultra-high-definition video and is designed to reduce the complexity of cabling in large displays and panels, making it a preferred choice in industries that manufacture televisions and digital signage displays. This technology enhances the quality of video signaling by ensuring smooth and uninterrupted data flow, which is vital for premium screen displays. The compact design of V-By-One HS lowers the overall system cost and footprint, while also cutting down on power consumption, essential for meeting the latest environmental and performance standards. This makes it an ideal solution for advanced display technologies requiring efficient data transmission with minimal hardware.
Intilop’s UDP Offload Engine (UOE) is engineered to process UDP packets efficiently, reducing CPU overhead and improving data transfer speeds. This ultra-low latency engine is crucial for applications where rapid data transmission is key, such as multimedia streaming, VoIP, and real-time gaming. The UOE provides robust functionality with its capability of supporting high-throughput processing and multiple concurrent sessions, which is vital for maintaining quality service in data-heavy environments. Its integration into networking systems ensures minimal latency while maximizing data integrity and reliability. Leveraging the UOE contributes to significant performance improvements in network devices, allowing for the handling of vast data volumes without compromising speed or reliability. This IP exemplifies Intilop’s commitment to delivering superior networking solutions that meet modern demands for speed and efficiency.
The 100G Transponder CAUI-10 facilitates seamless optical-to-electrical signal conversion, doubling as an efficient intermediary in high-capacity network systems. These transponders are invaluable for telecommunications setups that demand high data rates and extended reach, providing the necessary tools to manage complex digital signal demands.
The 10G Ethernet MAC and PCS from Chevin Technology is designed to deliver exceptional network performance for FPGA systems. This IP core boasts high throughput and low latency, ensuring efficient data transmission capabilities. Tailored for flexibility, it can integrate seamlessly into a variety of systems, providing reliability and reduced hardware complexity through its all-logic architecture. Offering compatibility with both Intel and Xilinx FPGAs, the core is intended for high-efficiency applications, making it suitable for use in environments where space and power consumption are critical factors. With its support for the latest Ethernet standards, it enhances network communication within embedded systems. Engineered for design efficiency, this MAC and PCS IP can lower system costs and footprint by fitting numerous cores on a single chip. By maximizing space for other logic components, it provides a cost-effective solution without compromising on performance.
The CT25203 is a component of Canova Tech's comprehensive IP offering, designed for facilitating the development of PMD transceivers compliant with the OA TC14 specification. It interacts efficiently with host MCUs, Zonal Gateway Controllers, or Ethernet switches, delivering robust performance for 10BASE-T1S digital PHY applications. The transceiver's high-voltage process technology enhances EMC performance, with an 8-pin package optimized for compact and efficient design, tailored for automotive and industrial communication requirements.
The eSi-Comms solution provides a highly parameterisable and configurable suite for communication ASIC designs. This comprehensive collection includes OFDM-based modem and DFE IPs supporting a vast array of contemporary air interface standards such as 4G, 5G, Wi-Fi, and DVB among others. It offers robust and efficient solutions for modulation, equalization, and error correction using advanced digital signal processing algorithms. With its capabilities specific to synchronization and demodulation across multiple standards, it equips systems for optimal data flow management. The adaptable DFE features support precision in digital frequency conversion and other enhancements, fortifying both the transmitting and receiving ends of communication systems. This IP empowers wireless sensors, remote metering, and cellular devices, ensuring seamless integration into a diverse range of communication applications.
The 10G TCP Offload Engine (TOE) by Intilop is meticulously engineered to offer high-speed TCP processing, reducing the computational burden on host CPUs. This ultra-low latency solution integrates seamlessly into network infrastructure, significantly improving data throughput and system performance. With robust design architecture, the TOE facilitates complete offloading of the TCP stack, allowing for enhanced speed and reduced jitter in data transactions. This makes the component ideal for applications demanding high-frequency data exchanges, such as financial trading platforms and high-performance computing systems. Additionally, the IP guarantees consistent performance across multiple sessions, supporting extensive concurrent connections without loss of speed or reliability. The design priorities robust security and data integrity, ensuring that systems utilizing this engine can achieve greater network efficiency and reliability.
The ePHY-5616 product is crafted to handle data rates from 1 to 56Gbps. Operating prominently on 16 and 12nm technology nodes, this solution is ideal for applications that demand scalable insertion loss and data rate adaptability. The architecture is robust, leveraging advanced DSP techniques to provide exceptional clock data recovery and superior BER (Bit Error Rate), catering to both enterprise and data center needs. Its utility extends to routers, switches, and other critical data infrastructure components.
This Ethernet Chiplet by YorChip is engineered to meet the high-performance networking needs of modern data-centric applications. With capabilities of supporting up to 400G Ethernet, it is primed for deployment in data centers and high-speed networking equipment. The design focuses on offering maximum bandwidth and low latency, catering to the robust data exchanges typical in these environments. A key feature of this chiplet is its ability to integrate with existing chiplet ecosystems, ensuring compatibility and ease of integration for manufacturers looking to upgrade their systems. The focus on low power consumption in its design highlights its suitability for large-scale deployment where energy efficiency is paramount. The chiplet also assures adaptability across numerous platforms with varied process node compatibilities, showing its versatility and robustness in multiple fabrication contexts. Its implementation can significantly enhance network throughput and reliability, ensuring efficient handling of large data volumes typical of sophisticated network architectures.
Secure Protocol Engines by Secure-IC are designed to offload network and security processing tasks in high-performance computing environments. These engines provide specialized IP blocks that can handle complex cryptographic protocols efficiently. The solution optimizes system performance by allowing primary processors to focus on core functionalities while the protocol engines manage the security operations. This capability is crucial for systems requiring robust security without compromising on speed or efficiency, such as in telecommunication or data center applications.
The Titanium Ti375 FPGA from Efinix boasts a high-density, low-power configuration, ideal for numerous advanced computing applications. Built on the well-regarded Quantum compute fabric, this FPGA integrates a robust set of features including a hardened RISC-V block, SerDes transceiver, and LPDDR4 DRAM controller, enhancing its versatility in challenging environments. The Ti375 model is designed with an intuitive I/O interface, allowing seamless communication and data handling. Its innovative architecture ensures minimal power consumption without compromising on processing speed, making it highly suitable for portable and edge devices. The inclusion of MIPI D-PHY further expands its applications in image processing and high-speed data transmission tasks. This FPGA is aligned with current market demands, emphasizing efficiency and scalability. Its architecture allows for diverse design challenges, supporting applications that transcend traditional boundaries. Efinix’s commitment to delivering sophisticated yet energy-efficient solutions is embodied in the Titanium Ti375, enabling new possibilities in the realm of computing.
The RWM6050 baseband modem by Blu Wireless represents a highly efficient advancement in mmWave technology, offering an economical and energy-saving option for high bandwidth and capacity applications. Developed alongside Renesas, the modem is configured to work with mmWave RF chipsets to deliver scalable multi-gigabit throughput across access and backhaul networks. This modem is ideal for applications requiring substantial data transfer across several hundred meters.\n\nThe RWM6050 leverages flexible channelization and advanced modulation support to enhance data rates with dual modems and integrated mixed-signal front-end processing. This ensures that the modem can effectively handle diverse use cases with varying bandwidth demands. Its versatile subsystems, including PHY, MAC, ADC/DAC, and beamforming, facilitate adaptive solutions for complex networking environments.\n\nA standout feature of the RWM6050 is its integrated network synchronization, ensuring high precision in data delivery. Designed to meet the futuristic needs of communication networks, it helps end-users achieve superior performance through its programmable real-time scheduler and digital front-end processing. Additionally, the modem's highly digital design supports robust, secure connections needed for next-generation connectivity solutions.
TimeServoPTP extends the capabilities of the TimeServo System Timer to provide a complete IEEE 1588v2 Precision Time Protocol (PTP) Ordinary Clock (OC) solution for FPGAs. This implementation supports both 1-Step and 2-Step synchronization with a network time grandmaster, ensuring accurate time alignment within a communication system. The IP is designed to interface directly with a PTP master through Ethernet, utilizing L2 EtherType frames for communication. It features flexible clocking options and independent time output domains, providing up to 32 precise timing outputs. Each output can be individually configured in various formats and includes a pulse-per-second signal for precise timing applications. TimeServoPTP employs a Gardner Type-2 digital phase-locked loop (DPLL) to maintain synchronization accuracy, leveraging FPGA resources efficiently. This solution supports Intel Agilex and Xilinx UltraScalePlus devices, demonstrating its adaptability across different hardware platforms.
The D2200 is a high-performance PCIe SSD designed by Swissbit for enterprise and data center applications. It combines exceptional data speeds with low power consumption to enhance system performance. This SSD is equipped with state-of-the-art NAND technology, ensuring sustained performance even under intense workloads. The D2200's design prioritizes temperature and performance management, making it resilient against environmental extremes and suitable for mission-critical applications.
Enyx’s nxLink is a forward-thinking network management suite tailored for constructing low-latency, high-efficiency trading environments. Leveraging FPGA technology, nxLink enhances network capabilities by enabling advanced link management and bandwidth distribution, critical for the infrastructure of financial firms and telecommunication sectors. The product suite is designed to tackle common networking challenges like latency, signal reliability, and bandwidth inefficiency, offering solutions that ensure minimal data loss and enhanced transmission stability by integrating wireless links with fiber backups. nxLink’s Share and Secure modules provide bandwidth management and redundancy handling, safeguarding network operations from outages or performance dips. Built for next-generation trading networks, nxLink supports features such as Ethernet fragmentation, link redundancy, and packet arbitration, thus boosting network performance and maintaining wire-speed processing. This adaptable network solution is well-suited for organizations keen on optimizing their communication infrastructures for rapid, stable data exchanges across multiple sites.
Dream Chip Technologies' Arria 10 System on Module (SoM) emphasizes embedded and automotive vision applications. Utilizing Altera's Arria 10 SoC Devices, the SoM is compact yet packed with powerful capabilities. It features a dual-core Cortex A9 CPU and supports up to 480 KLEs of FPGA logic elements, providing ample space for customization and processing tasks. The module integrates robust power management features to ensure efficient energy usage, with interfaces for DDR4 memory, PCIe Gen3, Ethernet, and 12G SDI among others, housed in a form factor measuring just 8 cm by 6.5 cm. Engineered to support high-speed data processing, the Arria 10 SoM includes dual DDR4 memory interfaces and 12 transceivers at 12 Gbit/s and above. It provides comprehensive connectivity options, including two USB ports, Gigabit Ethernet, and multiple GPIOs with level-shifting capabilities. This level of integration makes it optimal for developing solutions for automotive systems, particularly in scenarios requiring high-speed data and image processing. Additionally, the SoM comes with a suite of reference designs, such as the Intel Arria 10 Golden System Reference Design, to expedite development cycles. This includes pre-configured HPS and memory controller IP, as well as customized U-Boot and Angström Linux distributions, further enriching its utility in automotive and embedded domains.
The Ethernet Real-Time Publish-Subscribe (RTPS) core provides a comprehensive hardware solution for implementing the Ethernet RTPS protocol, crucial for applications that require deterministic data transfer with minimal latency. Ideal for real-time environments, this core enhances system performance by ensuring reliable data synchronization and fast publish-subscribe mechanisms, crucial in mission-critical operations. The core's design prioritizes streamlined data exchange processes, which improve system efficiency and reliability. Its robust framework is well-suited to applications needing high-speed online data exchanges, paired with enhanced system communication architecture that ensures effective bandwidth management without compromising data integrity.
The FC Anonymous Subscriber Messaging (ASM) IP core provides an advanced full-network stack, adeptly handling the FC-AE-ASM protocol for secure, high-speed communication. Built for military applications, it offers hardware-enabled label lookups, DMA control, and efficient message chain processing. Particularly suitable for environments requiring utmost data security, this core supports critical military-grade systems, including F-35 interfaces, reflecting its capability to manage complex message queuing and retrieval effectively. The core supports dynamic buffer management and system reliability, crucial for defense integrations that demand high data integrity and minimal transmission delay. It proves essential for network security needs, consistently meeting the rigorous requirements of modern defense communications.
The Flexibilis Ethernet Switch (FES) is a multi-functional Ethernet Layer 2 switch IP core providing high-speed data forwarding and advanced clock synchronization. This IP core supports triple-speed Ethernet functionality, ensuring comprehensive integration into various network environments where performance and reliability are paramount. Designed to maintain high throughput, the FES offers twelve full-duplex Gigabit Ethernet ports, prepared for the demands of complex industrial and telecommunication networks. The IP core's sophisticated memory management allows efficient use of FPGA resources, accommodating varying frame sizes without excessive resource allocation, which is especially beneficial during high network loads. FES integrates end-to-end and peer-to-peer IEEE 1588v2 transparent clock functionalities, providing critical precision in time-sensitive applications. By supporting VLAN tagging, traffic prioritization, and advanced packet filtering, it enhances both network performance and security. Available in multiple configurations, FES is adaptable to meet various network requirements, making it an ideal choice for engineering next-generation networks needing high-speed and robust communication capabilities.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
Efinix's Topaz FPGA series is engineered for mass-market applications, delivering a perfect mix of efficiency and adaptability. These FPGAs encapsulate a highly efficient architecture, combined with the industry's essential features and protocols, such as PCIe Gen3, MIPI, and LPDDR4. This configuration allows users to harness substantial performance while maintaining ample room for future innovations. Topaz FPGAs are optimized for high-volume production environments where cost-effectiveness and swift integration are paramount. Their design promotes ease of implementation in various applications, spanning from automotive to deeply embedded systems, where reliability and robustness are key. Featuring a streamlined architecture, Topaz series FPGAs support modern connectivity standards and data processing capabilities. These devices are tailored for industries requiring scalable solutions that can adapt to evolving technological landscapes, ensuring that Efinix customers remain competitive in their respective fields.
XtremeSilica's 100G UDP Offload Engine is engineered for performance, delivering outstanding speed and efficiency for large volumes of data transmission. Ideal for specialized applications, this solution empowers users to achieve superior network performance with minimum system overhead.
Algo-Logic's FPGA Tick-To-Trade platform focuses on optimizing the critical path in high-frequency trading by incorporating trading algorithms into FPGA-based systems for rapid execution. The solution significantly enhances the performance of order management systems by reducing the time between receiving and executing trading data, termed as 'Tick-To-Trade.' This reduction in latency is especially beneficial for proprietary trading firms and market makers who thrive on the speed of trade execution. This platform capitalizes on the speed advantage inherent in FPGA technology, combined with Algo-Logic’s proprietary logic designs aimed at providing deterministic performance. By minimizing variables such as jitter and latency, the Tick-To-Trade solution ensures that trading algorithms can execute trades as quickly as the market environment allows. Supported across multiple FPGA platforms from industry giants like Cisco and Xilinx, Algo-Logic’s solution integrates seamlessly into existing infrastructures, allowing clients to leverage ultra-low latency networking capabilities without overhauling their current systems. The emphasis on adaptability and robustness makes it a preferred choice for institutions investing in high-frequency trading architectures.
The Advanced Flexibilis Ethernet Controller (AFEC) serves as a powerful Ethernet controller IP block for both programmable devices and ASICs. It provides a comprehensive interface for network communication while significantly reducing system overhead, thanks to its selective features like bus master DMA and scatter-gather capabilities. AFEC supports triple-speed Ethernet, engaging both copper and fiber interfaces. Its robust design accommodates gigabit transfer rates, enhancing network throughput even when integrated with less powerful processing units. The inclusion of IEEE 1588 Precision Time Protocol allows for precise time stamping of network frames, enabling effective time synchronization across complex systems. This controller is equipped with additional functionalities to streamline network operations, such as automatic CRC handling and advanced interrupt management. These features make AFEC an optimal component in applications where performance and precision are critical, such as financial trading platforms and mission-critical communication systems.
The BCH Error Correcting Code ECC is crafted to provide paramount error correction capabilities, ideal for applications demanding high data fidelity and error resilience. This code is quintessentially designed to operate asynchronously with zero latency, optimized for minimal power use and gate count. It eliminates the necessity for synchronous logic by adopting a purely combinatorial gate-driven process. The BCH Code supports a variety of environments through configurable parameters, such as symbol size and error symbol corrigibility, thereby offering a flexible use-case across multiple domains. This IP is particularly beneficial in high-performance computing and communication systems, ensuring data integrity in storage devices like SSD controllers and high-speed interface applications. Its capacity to handle several error types without requiring sequential logic resources enhances its applicability in modern integrated circuits, where space and power constraints are pivotal.
The ePHY-11207 marks the frontier of eTopus's high-speed SerDes capabilities, facilitating data rates from 1 to 112Gbps. This 7nm nodal innovation is particularly significant in environments where latency precision and bandwidth are critical, such as in advanced networking interfaces and server applications. It integrates seamlessly with the existing network fabric, supporting high throughput demands and lower latency metrics, bolstered by eTopus's proprietary algorithms.
Time-Triggered Ethernet is an enhanced network solution tailored for environments requiring stringent timing and synchronization. By leveraging the principles of time-triggered communication, it enhances standard Ethernet with deterministic capabilities. This advanced protocol is instrumental in ensuring timely and predictable data exchange, making it ideal for complex network architectures where timing precision is a must. Utilizing synchronized clocks across the network, Time-Triggered Ethernet virtually eliminates latency variability. This predictability across the Ethernet infrastructure supports a variety of applications, from aviation systems requiring certified safety levels to automotive networks needing high reliability. The protocol helps in managing critical tasks efficiently by scheduling communication activities down to precise microsecond accuracy. Time-Triggered Ethernet enhances both the fault tolerance and robustness of networks it supports, making it a preferred choice for high-stakes scenarios. Its ability to carry safety-critical and time-sensitive data over existing Ethernet infrastructure ensures wide applicability and adaptability. By optimizing performance while maintaining compatibility with Ethernet standards, it supports diverse applications from smart industry automation to critical aerospace systems.
Algo-Logic’s ULL 10GE PHY+MAC is designed to deliver exceptional low-latency performance tailored for 10 Gigabit Ethernet environments. The product, targeted for high-frequency trading (HFT) and high-performance computing (HPC) systems, ensures that data transactions are completed swiftly and reliably. This IP core stands out with its compliance with IEEE802.3 standards and support for both Avalon-ST and AXI4-Stream interfaces, making it a versatile choice for various FPGA platforms. Key features include local and remote fault detection, frame check sequence processing, and compatibility with SERDES. The core is engineered to offer a straightforward replacement for default high-latency vendor cores, providing trading firms with a robust solution to enhance the performance of their systems significantly. Optimizations within the core reduce gate count while maintaining system flexibility, which is crucial for maintaining the competitive edge in trading applications.
This advanced engine combines multiple functionalities, integrating TCP offloading with Ethernet MAC and PCIe interface, designed for ultra-low latency operations. It ensures efficient data transfer with minimal CPU intervention, making it ideal for high-frequency trading and real-time applications. The integration of host interfaces further optimizes connectivity, providing seamless interaction between networked systems and processing units. The IP demonstrates high throughput, maintaining performance consistency irrespective of the network load, thus offering exceptional stability and reliability. This feature is crucial in dynamic data environments where constant data flow is essential. The offload engine also supports wide protocol compatibility, making it a versatile choice for various networking equipment. Moreover, this solution underscores Intilop's commitment to delivering cutting-edge technology in IP cores, facilitating enhanced network management and operational efficiency. The IP is designed to withstand the demands of high-speed data environments, bringing a new level of speed and accuracy to data handling.
The LDPC Decoder tailored for 5G New Radio (NR) applications offers robust decoding capabilities with the implementation of the Min-Sum algorithm. This decoder's architecture includes advanced features such as early iteration termination, programmable bit widths, and support for HARQ-related functionalities, all aimed at optimizing decoding performance. It is a key component in managing link reliability and efficiency, suitable for advanced wireless communication systems.
CLOP Technologies' 60GHz Wireless Solution offers businesses an impressive alternative to traditional networking systems. Leveraging the IEEE 802.11ad WiFi standard and Wireless Gigabit Alliance MAC/PHY specifications, this solution achieves a peak data rate of up to 4.6Gbps. This makes it particularly suited for applications that require significant bandwidth, such as real-time, uncompressed HD video streaming and high-speed data transfers — operations that are notably quicker compared to current WiFi systems. The solution is engineered to support 802.11ad IP networking, providing a platform for IP-based applications like peer-to-peer data transfer and serving as a router or access point. Its architecture includes a USB 3.0 host interface and mechanisms for RF impairment compensation, ensuring both ease of access for host compatibility and robust performance even under high data rate operations. Operating on a frequency band ranging from 57GHz to 66GHz, the wireless solution utilizes modulation modes such as BPSK, QPSK, and 16QAM. It incorporates forward error correction (FEC) with LDPC codes, providing various coding rates for enhanced data integrity. Furthermore, the system boasts AES-128 hardware security, with quality of service maintained through IEEE 802.11e standards.
The Flexibilis Redundant Switch (FRS) is an advanced Ethernet Layer-2 switch IP core that offers comprehensive support for High-Availability Seamless Redundancy (HSR) and Parallel Redundancy Protocol (PRP). Designed for programmable hardware like FPGAs, it is an integral solution in industrial networks where fail-safe operation is critical. FRS is equipped with the ability to manage multiple types of ports, providing the flexibility needed for various configurations and redundancy schemes. With features that allow full-duplex operation and wire-speed forwarding, FRS ensures data packet processing is efficient and reliable. Its ability to support both end-to-end and peer-to-peer transparent clock synchronization with IEEE 1588v2 enhances its utility in environments that demand precise timing, such as in power grids and industrial automation systems. The switch can operate seamlessly across different link speeds and types, which is essential for diverse network infrastructures. FRS simplifies network architecture by removing the need for separate RedBoxes, encouraging cost-effective solutions in deploying redundant protocols. Its performance, ease of use, and scalability make it a key component in enhancing network resilience and responsiveness in automated systems across various industries.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
The Multi-Channel Silicon Photonic Chipset by Rockley Photonics represents a milestone in high-speed data transmission technology. It combines silicon photonics with the hybrid integration of III-V Distributed Feedback (DFB) lasers and electro-absorption modulators to deliver a high-performance chipset capable of supporting data rates of up to 400 GBASE-DR4. Each channel in the transmitter achieves substantial optical modulation amplitude (OMA) and a high extinction ratio with minimal TDECQ penalty, ensuring compliance with IEEE standards. This chipset is tailored for high-bandwidth and high-data rate applications, providing the essential infrastructure for advanced data communication networks. By merging III-V DFB lasers with electro-absorption modulators, the system can operate efficiently across multiple channels, enhancing data transfer speeds while maintaining signal integrity. The innovation of this chipset lies in its multi-channel design, which facilitates increased data throughput and reliability. It is particularly useful in data centers and network systems where rapid data exchange is critical. Rockley's chipset also emphasizes energy efficiency and signal precision, which are crucial for meeting the growing demands of modern telecommunications architectures and network environments.
Currently under research and development, the SafeIP™ TriplePHY is crafted to accommodate three distinct media dependent interfaces, enhancing its capacity for agile and versatile communication. Extending the capabilities of its predecessors, the TriplePHY promises to offer comprehensive support for diverse communication protocols, ensuring system-wide connectivity and safety adaptability. While the specifics are still evolving, the TriplePHY is expected to support substantial bandwidths, matching and exceeding current industry standards to facilitate faster communication protocols. Its design aims to comply with high-grade automotive standards, structured to meet the demands of complex safety-critical environments characteristic of modern autonomous systems. This upcoming innovation by Siliconally showcases a commitment to advancing their PHY solutions, aligning with emerging market needs and safety implementations. As the development progresses, it will likely become an integral part for industries pushing for maximized communication efficiency within secure frameworks.
Creonic’s Miscellaneous FEC and DSP IP Cores are an essential toolkit for enhancing digital signal processing capabilities across various fields. These include solutions like Viterbi Decoders, FFT/IFFT processors, and advanced BCH code implementations, which are cornerstones in data correction and signal processing. These DSP cores are engineered for high performance and efficiency, vital for applications demanding robust signal integrity and processing speed. From Doppler Channel processing found in satellite and radio communications to sophisticated stream processing in broadband networks, every core is fine-tuned for specific performance requirements. Creonic provides adaptable designs that are geared for seamless integration into existing platforms, ensuring continued enhancement of network efficiency and data reliability. The flexibility of these cores means they can be tailored to fit diverse operational standards, making them invaluable in meeting complex communication challenges.
The High Speed Data Bus (HSDB) core offers a full-featured hardware implementation of PHY and Mac layers, specifically designed to integrate seamlessly with F-22 systems. This core supports high-speed communication with easy-to-integrate frame interfaces, essential for real-time data transfers in demanding aerospace applications. It strengthens communication reliability and efficiency across the data bus, ensuring rapid and secure data exchanges. By facilitating optimal data flow with robust frequency and data management controls, the HSDB core enhances avionics systems' capability to handle high volumes with minimal latency. Its architecture is engineered to support full data rate operations, with provisions for half and quarter-rate functionalities. This adaptability ensures compatibility with various military-grade communication systems. The core stands out for its precision-tuned interfaces, which accommodate rigorous defense standards and enhance communication integrity. Its implementation facilitates robust synchronization among distributed systems, maintaining data fidelity and resilience under challenging conditions.
The 100BASE-T1 Ethernet PHY offers an innovative solution for modern Ethernet communications, providing high-speed data transmission over a single unshielded twisted pair cable supporting 100 Mbps. This PHY is optimized for low power consumption and minimal electromagnetic interference, making it ideal for automotive and industrial applications. Its compact design supports seamless integration into various devices, enhancing connectivity and data throughput in constrained environments.
The FC Upper Layer Protocol (ULP) core provides a complete, hardware-enabled network stack for managing FC-AE-RDMA or FC-AV operations. It enhances interoperability in military and aerospace protocols by providing comprehensive support for buffer mapping, DMA controllers, and message chain engines. By enabling fast, reliable communication, this core suits high-demand environments that require precise and efficient data exchanges. Its configuration is compatible with both F-18 and F-15 aircraft systems, emphasizing its versatility across various defense platforms. The core's architecture is purposefully designed to support robust network performance under challenging conditions, keeping data synchronization and integrity at the forefront. Its adaptable nature enables seamless adaptations to both legacy and new systems, further ensuring extensive utility in complex applications.
The ntLDPC_8023CA (17664,14592) IP Core is defined in IEEE 802.3ca-2020 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCE_8023CA encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer when multiplied by the 14592 payload block pro-duces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1 to 6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_8023CA decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_8023CA decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The HOTLink II core delivers a complete hardware implementation for High-Speed Interconnects (HSI), pertinent for F-18 compatible systems. This core meets rigorous bandwidth demands with a robust architecture that seamlessly supports full-rate, half-rate, and quarter-rate operations. Designed to offer a simplified frame interface, it integrates effortlessly with existing systems without added complexity. It plays a crucial role in maintaining high data throughput, suited for avionics and other data-intensive applications. By bolstering communication reliability across strategic military platforms, the HOTLink II ensures secure and efficient data management, crucial for mission-critical operations where every second counts. The core’s versatility allows it to integrate with both legacy and modern systems, making it a valuable component for enhancing existing infrastructure. Its standardized interfaces and adaptability make it an ideal choice for environments demanding both performance and reliability.
Perfect for advanced parking solutions, the ASPER radar sensor operates at 79GHz, providing superior performance compared to traditional ultrasonic systems. Designed to deliver a 180° coverage with a single module, it offers enhanced detection capabilities for both passenger and commercial vehicles. ASPER's edge processing and domain-specific features make it ideal for automotive applications like blind spot detection and tailgate protection, while ensuring accuracy unaffected by environmental conditions.
The Fibre Channel (FC) Link Layer core efficiently implements the first two layers of the Fibre Channel protocol stack, focusing on data link operations in high-demand environments. It serves a vital role in supporting consistent and reliable data transfers. Designed for applications requiring robust high-speed network operations, this core enhances communication integrity by meeting stringent protocol standards. Its architecture supports seamless data exchanges under heavy loads and variable operational conditions. This IP core is engineered to provide unmatched bandwidth management and reliability, ensuring stable and secure data handling for mission-critical operations involving sophisticated aerospace systems.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
The DVB-RCS and IEEE 802.16 WiMAX Turbo Decoder is expertly crafted for decoding tasks in high-speed data networks, particularly those using satellite and broadband wireless communication standards. This 8 state Duobinary Turbo Decoder features an optional 64 state Viterbi decoder, highlighting its capacity for intricate data throughput and error correction. Functional in a multitude of data environments, this decoder can handle a variety of signal paths, ensuring robust data recovery and integrity. Its architecture is especially suited for dynamic network conditions, offering adaptability and reliability-critical factors in maintaining service quality in challenging communication scenarios. This Decoder is ideal for systems operating under diverse protocols, ensuring seamless interoperability and efficient error detection and correction. By optimizing data processing technologies, it supports high-speed data exchanges across broader channels, catering to the growing demand for superior network performance in modern telecommunication infrastructures.
The Digital PreDistortion (DPD) Solution by Systems4Silicon is a cutting-edge technology developed to maximize the power efficiency of RF power amplifiers. Known as FlexDPD, this solution is vendor-independent, allowing it to be compiled across various FPGA or ASIC platforms. It's designed to be scalable, optimizing resources according to bandwidth, performance, and multiple antennae requirements. One of the key benefits of FlexDPD is its substantial efficiency improvements, reaching over 50% when used with modern GaN devices in Doherty configurations, surpassing distortion improvements of 45 dB. FlexDPD is versatile, operating with communication standards including multi-carrier, multi-standard, and various generations from 2G to 5G. It supports both time division and frequency division duplexing, and can accommodate wide Tx bandwidths, limited only by equipment capabilities. The technology is also agnostic to amplifier topology and transistor technology, providing broad applicability across different setups, whether class A/B or Doherty, and different transistor types like LDMOS, GaAs, or GaN. This technology integrates seamlessly with Crest Factor Reduction (CFR) and envelope tracking techniques, ensuring a low footprint on resources while maximizing efficiency. With complementary integration and performance analysis tools, Systems4Silicon provides comprehensive support and documentation, ensuring that clients can maximize the benefits of their DPD solution.