All IPs > Wireline Communication > Fibre Channel
Fibre Channel semiconductor IPs are crucial components in the infrastructure of high-speed data transfer systems tailored to enterprise storage networking. Known for their reliability and high performance, these semiconductor IPs enable efficient data communication essential for critical data center environments. Fibre Channel technology is a key driver in maintaining seamless connectivity and data flow across enterprise storage networks, ensuring that shared storage resources are accessible, robust, and efficient.
In the realm of wireline communication, Fibre Channel is often chosen for its ability to handle substantial amounts of data traffic with low latency, making it an indispensable technology in settings that require rapid storage and retrieval of information. This technology significantly boosts data handling capabilities and is particularly efficient in managing complex storage area networks (SANs). Moreover, the inherent scalability of Fibre Channel IPs offers enterprises the flexibility to expand and adapt their storage solutions as their data management needs evolve.
Products in this category of semiconductor IP range from basic cores designed for integration into larger system solutions to more advanced IP modules that provide comprehensive functionalities necessary for Fibre Channel implementation. These may include transceiver modules, protocol engines, and physical layer interfaces, all meticulously designed to adhere to industry standards and interoperability requirements. By using Fibre Channel IPs, developers can ensure that their products support high-speed data processing, offering an edge in competitive markets where performance and reliability are paramount.
The adoption of Fibre Channel semiconductor IPs in enterprise networks translates into higher efficiency and enhanced capability to support applications that require substantial bandwidth, such as virtualization and large transactional databases. As data demands continue to grow, leveraging Fibre Channel technology becomes even more critical in the strategic planning of network and storage architecture, providing foundational support for future technological advancements in data management systems.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
InnoSilicon's 56G SerDes Solution provides a high-speed interface offering breathtaking transmission rates of up to 56Gbps per channel. Supporting both PAM-4 and NRZ modulation schemes, it adapts easily to various high-speed protocols to serve diverse applications like data center network systems and telecom infrastructure. This IP reinforces robust signal integrity and low power consumption, making it suitable for advanced ESD and BIST functionalities. Its flexible architecture meets modern network demands, ensuring future-proof customization opportunities.
The SerDes (Serializer/Deserializer) PHY offered by Terminus Circuits represents an integral component essential for various data communication technologies, where heightened bandwidth and speed are critical. This technology is crafted to accommodate diverse nodes, multiple foundries, and protocols, ensuring their solutions meet even the most demanding customer requirements. Features include low power consumption, minimal latency, and compact physical design, setting it apart for users demanding efficient SerDes technology. Terminus Circuits provides a comprehensive set of deliverables for their SerDes PHY, including user guides for integration, meticulous timing libraries, and Verilog code. This solution is adaptable to a broad spectrum of market segments, encompassing sectors like network communication, data storage, and enterprise networking, thanks to its seamless interoperability with existing controllers. With the ability to support diverse protocols such as PCI Express, USB 3.1, and various optical interfaces, the SerDes PHY provides an essential backbone for robust high-speed data exchange. The SerDes PHY is particularly noted for its capacity to handle conventional as well as emerging networking and storage protocols, with configurations that support variations across different data rates and standards. Such versatility in supporting bifurcation modes and progressive equalization techniques ensures optimal signal integrity and minimized data latency, catering to sophisticated applications requiring high-speed, reliable data transfer.
The VIDIO 12G SDI FMC Daughter Card is engineered to facilitate next-level broadcast video applications. Equipped with 12G SDI and 10G IP interfaces, this card supports 4K resolution at 60 frames per second, making it compatible with various AMD and Intel development boards. Manufactured with the latest chip technology, the card utilizes a single board design, incorporating full-size edge launch BNCs along with an SFP+ cage. This enables developers to integrate additional SFP-BNC inputs and outputs, extending versatility in signal configurations. The card is thoroughly tested for quality, fulfilling requirements for jitter performance over extended cable runs, ensuring signal reliability in demanding broadcast environments. With a focus on ease of use, it requires no software for initialization, making it ready-to-use for rapid deployment.
The iCan PicoPop® System on Module (SOM) by Oxytronic is an ultra-compact computing solution designed for high-performance and space-constrained environments within the aerospace industry. Utilizing the Xilinx Zynq UltraScale+ MPSoC, this module delivers significant processing power ideal for complex signal processing and other demanding tasks. This module's design caters to embedded system applications, offering robust capabilities in avionics where size, weight, and power efficiency are critical considerations. It provides core functionalities that support advanced video processing, making it a pivotal component for those requiring cutting-edge technological support in minimal form factors. Oxytronic ensures that the iCan PicoPop® maintains compatibility with a wide range of peripherals, facilitating easy integration into existing systems. Its architectural innovation signifies Oxytronic's understanding of aviation challenges, providing solutions that are both technically superior and practically beneficial for modern aerospace applications.
The Managed Ethernet Switch IP is tailored for applications requiring efficient data handling and management in Ethernet networks. Its design includes a scalable crossbar switch model and the ability to manage data across various Ethernet ports, making it suitable for high-density networking environments requiring reliable and streamlined communication.
The Ethernet 10/100 MAC by MosChip offers robust connectivity solutions for various network-intensive applications. Focused on delivering high-speed data transfer, this MAC architecture is designed to be fully compatible with IEEE standards, ensuring seamless integration into existing network infrastructures. It supports both 10 Mbps and 100 Mbps data rates, adapting to a wide range of throughput requirements. With advanced features like full-duplex and half-duplex operations, it efficiently manages network traffic, making it an excellent choice for complex networking environments. MosChip's Ethernet 10/100 MAC is engineered to provide excellent interoperability with a variety of processors and network devices. Its low latency and high data processing capabilities make it ideal for real-time applications where speed and reliability are paramount. Additionally, the MAC includes a comprehensive set of control and status registers for enhanced diagnostics and network management, offering developers robust tools to optimize performance. Tailored for ease of integration, the MAC's modular design simplifies the implementation process, ensuring rapid deployment in consumer electronics and telecommunication devices. This adaptability and support for advanced network features make it a versatile solution for modern Ethernet applications, fulfilling the diverse needs of global technology markets.
Ethernet Solutions from PRSsemicon deliver cutting-edge network interfaces ranging from 1G to 800G, including MAC, PCS, and switch components. This extensive suite enables robust and scalable networking capabilities suited to various environments, including data centers and enterprise networks. The solutions are designed to support both traditional Ethernet and advanced functionalities, ensuring optimal performance, reliability and data integrity across various applications in telecommunications and beyond.
The Ceva-XC22 is a cutting-edge DSP core tailored for 5G and 5G-Advanced workloads, offering unprecedented processing capabilities and flexibility for demanding communications applications. This DSP core supports simultaneous processing tasks with high utilization rates, ensuring superior performance across multiple data channels and spectral layers.\n\nCeva-XC22 is built on a dual-threaded architecture with a dynamic scheduled vector processor, which provides extensive processing power for increasingly complex 5G applications. The system also includes a vector computation unit for enhanced arithmetic operations and data handling.\n\nBy leveraging its advanced execution model, Ceva-XC22 delivers significant performance improvements over its predecessors, making it ideal for a range of infrastructure applications, from massive MIMO to core network processing.
StreamDSP's complete MIPI video processing pipeline offers a comprehensive solution to simplify video integration into embedded FPGA systems. This pipeline supports both Avalon and AXI-4 streaming protocols, accommodating a vast array of sensor video formats and customizable frame rates, including 4K at 60 frames per second and beyond. The flexible architecture facilitates low-latency video processing with the capacity to handle multiple pixels per clock cycle. This enables users to make resource and clock rate trade-off decisions more effectively. The pipeline components can be seamlessly integrated into various system configurations, providing full IP integration and customization services to ensure that each design is optimized for its specific application. The solution simplifies the process of embedding complex video capabilities into FPGAs, making it well-suited for high-performance video applications across different sectors.
The Managed Redundant Switch Core combines advanced networking capabilities with redundancy features, ensuring robust connectivity and uninterrupted data flow. Integrated within FPGA, this core is optimal for systems where reliability and network integrity is vital, featuring a non-blocking crossbar matrix architecture to enable continuous data transfer across all ports.
The Multiport Time Sensitive Networking (TSN) Switch Core provides precision time synchronization across multiple network nodes, adhering to stringent time-sensitive networking standards. This IP core offers seamless integration with both hardware and software offerings, ensuring accurate data timing in applications such as industrial and vehicular networks.
CoaXPress (CXP) is a prominent global standard for high-speed imaging in professional and industrial applications, including machine vision, medical imaging, life sciences, broadcasting, and defense. It combines the simplicity of coaxial cables with high-speed serial data transmission technology, offering a beneficial solution for imaging and data transmission requirements. EASii IC has developed CoaXPress IP for both Device and Host applications to meet internal camera and recorder design requirements. The IP is compliant with CoaXPress versions 1.1.1 and 2.0, enabling up to 256 video streams from multiple cameras through 1 to 8 coaxial cable connections. This setup allows a data rate ranging from 1.25 Gbps to 12.5 Gbps per cable, with total transfer rates reaching up to 100 Gbps. Dynamic link reconfiguration and hardware-based video-stream management are key features, supporting enhanced error detection and recovery. EASii IC offers a comprehensive CoaXPress design environment, including FPGA CoaXPress Device and Host IP cores, with associated hardware like FMC-CXP boards that stack to provide increased bandwidth capabilities.
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