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The eFPGA is an advanced embedded FPGA solution designed to offer flexibility and adaptability in ASIC and SOC designs. This technology-independent IP is fully customizable to meet the diverse requirements of digital logic functions across multiple applications. The eFPGA is characterized by its seamless integration into standard RTL design flows, making it a reliable choice for enhancing the configurability and functionality of existing semiconductor products. With capabilities to adjust parameters such as LUT count, routing density, and more, the eFPGA allows for extensive optimization based on unique design constraints. ADICSYS offers the eFPGA IP as both a soft core and a hard block, delivered in various formats like GDSII, OpenAccess, or Milkyway. This IP not only supports a broad range of design environments but also comes with comprehensive synthesis and constraint files, aligned with industry-standard CAD tools. Furthermore, ADICSYS provides its own compilation software, Acompile, which facilitates the smooth transfer of designs into programmable bitstreams. This flexibility in configuration ensures that the eFPGA IP can be easily adjusted to support evolving technological demands. Designers can take advantage of the eFPGA's rich feature set, including real-time bug fixes, circuit modifications in the field, and significant reductions in design verification time. Additionally, these embedded FPGAs play a crucial role in reducing production risks by providing workaround options for potential design challenges or specification changes late in the development process.
The Synthesizable Programmable Core (SPC) by ADICSYS is a soft FPGA IP tailored for integration into ASICs, SOCs, and general silicon IPs. The primary advantage of SPC is its flexibility in addressing specification errors and changes, enabling designers to incorporate customizable logic efficiently. This IP helps reduce development and verification times while enhancing debugging capabilities, ultimately accelerating time-to-market for critical system components. SPC operates seamlessly within standard ASIC CAD tools and methods, imposing no constraints on the ASIC design flow. It offers compatibility with various stages of design processes, including simulation, synthesis, backend, and testing, thus delivering a transparent experience without introducing design phase delays. The IP is highly portable, thanks to its RTL composition, which circumvents the need for silicon-proofing new instances. This approach leverages standard cells to facilitate ease of synthesis with minimal physical design constraints. In addition to its portability and design flexibility, the SPC provides extensive customization opportunities, such as late-stage modifications and variable scale inclusion. It's based entirely on standard cell ASIC technology, benefiting from powerful modern CAD tools to extend the ASIC lifecycle. Through offering the ability to implement upgrades or modifications post-production, the SPC aids in future-proofing devices and accommodating potential late-stage project adjustments.
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