Is this your business? Claim it to manage your IP and profile
TimeServoPTP extends the capabilities of the TimeServo System Timer to provide a complete IEEE 1588v2 Precision Time Protocol (PTP) Ordinary Clock (OC) solution for FPGAs. This implementation supports both 1-Step and 2-Step synchronization with a network time grandmaster, ensuring accurate time alignment within a communication system. The IP is designed to interface directly with a PTP master through Ethernet, utilizing L2 EtherType frames for communication. It features flexible clocking options and independent time output domains, providing up to 32 precise timing outputs. Each output can be individually configured in various formats and includes a pulse-per-second signal for precise timing applications. TimeServoPTP employs a Gardner Type-2 digital phase-locked loop (DPLL) to maintain synchronization accuracy, leveraging FPGA resources efficiently. This solution supports Intel Agilex and Xilinx UltraScalePlus devices, demonstrating its adaptability across different hardware platforms.
The UDP Offload Engine (UOE) is a UDP-focused FPGA IP core designed to optimize packet throughput across a range of Ethernet speeds from 10GbE to 400GbE. With its support for UDP/IPv4 as per RFC 768/791, the UOE efficiently offloads tasks from the CPU, handling segmentation and reassembly in hardware to boost performance. This IP core is built for seamless interoperability with popular FPGA vendor Ethernet MACs, enhancing data transfer speeds without overwhelming the host system. It features a multicast pre-selector and various layers of protocol support, ensuring it can handle high-density UDP traffic efficiently. Applications benefiting from the UOE include data-centric operations requiring fast, reliable packet handling with low latency. Its low-area design allows for multiple instances on a single FPGA, and it includes interfaces like Avalon and AXI4 for streamlined integration within network architectures.
ARDSoC is Atomic Rules' solution for integrating Data Plane Development Kit (DPDK) capabilities into ARM-based System-on-Chip (SoC) architectures. By bypassing the traditional Linux network stack, ARDSoC optimizes ARM processor cycles, significantly boosting network performance and reducing latency. This IP core is well-suited for a variety of embedded applications, including those using protocol bridges like CCIX and NVMe-over-Fabrics. Bringing DPDK to the embedded space, ARDSoC supports sophisticated use cases like container-aware applications, making it ideal for cloud-edge devices requiring advanced network processing. Engineered for reduced memory pressure on the processor system's DRAM and optimized for ARM MPSoC architectures, ARDSoC enables existing DPDK applications to run with minimal modification. Its zero-copy coherent memory structure enhances cache performance, offering line-rate agnostic throughput up to 64 Gbps without packet loss.
The TimeServo System Timer is a high-resolution FPGA IP core designed to provide precise timekeeping functionalities within FPGA systems. This IP offers sub-nanosecond resolution and sub-microsecond accuracy, making it ideal for scenarios that require precise timestamping, such as network packet timing. Built as a single-component solution, TimeServo offers a coherent time source, supporting up to 32 outputs each in different clock domains. This flexibility allows it to accommodate various timing architectures within an FPGA environment, and it includes a proportional-integral controlled digital phase-locked loop (PI-DPLL) for maintaining timing accuracy with an external pulse-per-second reference. With an AXI4-Lite interface for control, TimeServo allows for software configuration and observability, enabling engineers to manage the timing outputs effectively. It is especially suited for IEEE-1588v2/PTP applications, providing the necessary infrastructure to function as a PTP ordinary slave device without requiring host interaction.
The Arkville Data Mover is a powerful DMA solution designed to seamlessly transfer data between FPGA logic and host memory. Achieving up to 60 GBytes/s in each direction, Arkville provides an efficient conduit for data transport, significantly reducing CPU overhead by enabling zero-copy data handling. This HDL core is tailored for high-performance applications, providing vendor-agnostic RTL support for both Intel and AMD/Xilinx FPGAs. Arkville supports concurrent, full-duplex data transfer, enabling burst traffic up to 1 Tbps through two AXI streams. This capability is particularly useful for applications requiring extreme data throughput without compromising on system efficiency. The core is extensively tested for reliability and performance, ensuring it can handle packet processing in demanding environments. Example designs, including implementations for 10 GbE and 100 GbE setups, are provided to help engineers quickly deploy the Arkville data mover in their solutions. Its adoption of DPDK and AXI standards lays a future-proof foundation for evolving FPGA-based networking applications.
Join the world's most advanced semiconductor IP marketplace!
It's free, and you'll get all the tools you need to evaluate IP, download trial versions and datasheets, and manage your evaluation workflow!
To evaluate IP you need to be logged into a buyer profile. Select a profile below, or create a new buyer profile for your company.
