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The TimeServoPTP expands on the capabilities of the TimeServo by offering a fully compliant IEEE 1588v2 Precision Time Protocol (PTP) ordinary clock implementation. Specifically designed as an FPGA component, it supports both 1-step and 2-step synchronization processes, ensuring cohesive operation in synchronization tasks involving network time grandmasters. With capabilities that include up to 32 'time now' outputs with clock domain crossing logic, TimeServoPTP is engineered for applications where maintaining coherent time is crucial. This is especially beneficial in scenarios requiring precise timekeeping over Ethernet using PTP/1588 EtherType frames. The internal Gardner Type-2 DPLL further adds to its high precision in synchronization tasks. The solution is straightforward to implement, functioning independently from host processors post-initialization. Compatible with Intel and Xilinx FPGA devices, TimeServoPTP is an ideal choice for applications in autonomous synchronization where minimal host interaction is preferred, and is well-suited for both complex and standard timekeeping challenges in network infrastructure.
The Arkville Data Mover is a high-performance FPGA Gen5 PCIe DMA IP designed for seamless data transport between FPGA logic and host memory. It achieves remarkable throughput rates of up to 60 GBytes per second both upstream and downstream, optimizing data flow and offloading CPU tasks to improve efficiency. Featuring industry-standard APIs, Arkville eliminates memory copies by using zero-copy user space memory buffers on the host, while supporting a wide range of FPGA devices including those from Intel and AMD/Xilinx. This robust solution is designed for scalability, accommodating industry demands for PCIe and AXI standards compliance, and offering a trusted platform for building FPGA-based packet processing solutions. Arkville also provides examples for various configurations, such as four-queue 10GbE setups and single-queue 100GbE arrangements, making it an adaptable choice for diverse networking scenarios. Built with vendor-agnostic RTL support, Arkville ensures flexibility and future-proofing for growing applications. Its modular design includes AXI streaming interfaces, a dedicated Application BAR, and is extensively tested with Jenkins CI/CD frameworks, reflecting its durability in high-speed data environments.
The TimeServo System Timer is an advanced IP core designed to provide high-resolution timekeeping for FPGAs. With its sub-nanosecond resolution and sub-microsecond accuracy, it is particularly suited for applications like packet timestamping, which demands precise time measurement. The core's PI-DPLL allows it to synchronize its operations using an external Pulse Per Second (PPS) signal. One of the key features of TimeServo is its ability to handle multiple independent clock domains, offering flexibility with up to 32 runtime-switchable outputs. This capability makes it a versatile solution for applications requiring different timing formats, including binary, IEEE ordinary, and IEEE transparent modes. The internal logical 120-bit phase accumulator and a digital phase-locked loop ensure that timekeeping operations are conducted with the utmost precision. Engineered for seamless integration, the timer’s capabilities can be further extended with the TimeServoPTP solution, providing a complete IEEE-1588v2/PTP ordinary slave device. This makes the TimeServo System Timer a comprehensive tool for network time synchronization tasks in FPGA contexts.
The ARDSoC Embedded DPDK is an innovative FPGA IP core that extends the functionality of DPDK into ARM-based systems. Designed to bypass traditional Linux network stacks, it saves precious ARM processor cycles by directly linking to data processing components. This core brings cutting-edge datacenter capabilities to embedded environments, enhancing performance in low-SWaP (Size, Weight, and Power) applications. ARDSoC excels in reducing total cost of ownership, power consumption, and latency, especially when compared to legacy x86 solutions. The core supports packet vector and container-aware applications, making it ideal for edge devices employing protocols like CCIX, RDMA, and NVMe-oF. With seamless cross-compilation to ARM and significant power and latency reductions, it provides a substantial performance boost in datacenter settings. Designed for Xilinx platforms, the core supports plug-and-play operability with Yocto Linux and Xilinx Vivado. This allows developers to quickly transition applications from prototype to production while maintaining high throughput—up to 64 Gbps—without packet loss. Its harmonized interaction between ARM processors and data structures is a hallmark of Atomic Rules' engineering expertise.
The UDP Offload Engine (UOE) from Atomic Rules is a sophisticated FPGA IP core developed to handle high-throughput UDP applications. Capable of supporting up to 400 GbE, this engine facilitates seamless data transfer across varying Ethernet environments, optimizing application throughput as network speeds advance. Engineered to offload UDP operations traditionally handled by software, the UOE enhances efficiency by bringing these tasks into hardware, thus freeing up processor resources. Its support for multiple rates—from 10 to 400 GbE—provides flexibility for current and future networking requirements. Moreover, the engine implements UDP/IPv4 standards and includes features like checksum verification, segmentation, and IGMPv2 multicast pre-selection. The UOE is designed for easy integration with a variety of FPGA-based Ethernet MACs, offering a broad compatibility with digital environments. With its capability to manage concurrent datagram sending and receiving, it offers robust support for non-UDP and direct Layer 3 applications, ensuring comprehensive data handling across network layers.
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