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The G13 and G13X IP cores are engineered to accomplish 512-bit correction blocks, which are commonly used in NAND devices with 2KB and 4KB page sizes. As SLC NAND transitions toward smaller geometries, this IP extends existing controller capabilities to meet more demanding ECC requirements. Not only available in standard configurations, Cyclic Design can tailor this IP to perfectly align with the specific needs of any controller hardware, addressing latency, bandwidth, and area prerequisites.
The G12 is a highly optimized BCH error correction solution focused on 256-byte correction blocks. Particularly beneficial for specialized applications that require smaller block sizes, this IP offers dynamic flexibility with block sizes ranging from 2 to 450 bytes. Users can maximize area efficiency by specifying the ECC level, supporting both single and multi-channel configurations. Delivered as Verilog source with SystemVerilog Assertions, the G12 can accommodate higher ECC levels upon request.
The G15 ECC core represents a sophisticated error correction IP optimized for 2KB correction blocks, directly applicable to NAND devices with larger page sizes. With a compatibility that extends across 512B and 1KB correction blocks, the G15 is designed to be adaptable and performance-oriented. Enhanced architectural features ensure optimal integration into existing systems when partnered with Cyclic Design’s expertise, providing a comprehensive solution tailored for demanding ECC requirements.
The G14 and G14X IP cores are specialized for 1KB correction blocks, suitable for NAND devices with 8KB page sizes. Initially designed for MLC, its capabilities extend to SLC flash controllers, providing increased wear leveling and long-term compliance with evolving ECC standards. Available in an off-the-shelf model or customized configuration, the G14X is crucial for advanced applications requiring significant error correction capabilities.
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